[libopenstm32-devel] Add setup for 25 MHz external clock to 72 MHz system clock

[Uwe B. <bo...@el...>]

Hello,

please review appended patch and apply or let me know any possible problems

Bye

-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>From 4d43502a0f54559320901d25f109e2f10e757287 Mon Sep 17 00:00:00 2001
From: Uwe Bonnes <bo...@el...>
Date: Sun, 3 Jul 2011 18:03:35 +0200
Subject: Add setup for 25 MHz external clock to 72 MHz system clock

---
 include/libopencm3/stm32/rcc.h |    1 +
 lib/stm32/rcc.c                |   73 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+), 0 deletions(-)

diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
index d000567..a14aecd 100644
--- a/include/libopencm3/stm32/rcc.h
+++ b/include/libopencm3/stm32/rcc.h
@@ -430,6 +430,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
 void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
 void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
 void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_25mhz_out_72mhz(void);
 void rcc_backupdomain_reset(void);
 
 #endif
diff --git a/lib/stm32/rcc.c b/lib/stm32/rcc.c
index 1da462a..90b2a69 100644
--- a/lib/stm32/rcc.c
+++ b/lib/stm32/rcc.c
@@ -753,6 +753,79 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
 	rcc_ppre2_frequency = 72000000;
 }
 
+void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
+{
+	/* Enable internal high-speed oscillator. */
+	rcc_osc_on(HSI);
+	rcc_wait_for_osc_ready(HSI);
+
+	/* Select HSI as SYSCLK source. */
+	rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
+
+	/* Enable external high-speed oscillator 25MHz. */
+	rcc_osc_on(HSE);
+	rcc_wait_for_osc_ready(HSE);
+	rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+
+	/*
+	 * Set prescalers for AHB, ADC, ABP1, ABP2.
+	 * Do this before touching the PLL (TODO: why?).
+	 */
+	rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV);	/* Set. 72MHz Max. 72MHz */
+	rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8);	/* Set. 9MHz Max. 14MHz */
+	rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2);	/* Set. 36MHz Max. 36MHz */
+	rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV);	/* Set. 72MHz Max. 72MHz */
+
+	/*
+	 * Sysclk runs with 72MHz -> 2 waitstates.
+	 * 0WS from 0-24MHz
+	 * 1WS from 24-48MHz
+	 * 2WS from 48-72MHz
+	 */
+	flash_set_ws(FLASH_LATENCY_2WS);
+
+        /* Configure PLLs ------------------------------------------------------*/
+        /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+        /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+        rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5);
+        rcc_set_pll2mult(RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8);
+        rcc_set_prediv1src(RCC_CFGR2_PREDIV1SRC_PLL2_CLK);
+        rcc_set_prediv1(RCC_CFGR2_PREDIV1_DIV5);
+
+        /* Enable PLL2 */
+        rcc_osc_on(PLL2);
+        /* Wait till PLL2 is ready */
+        rcc_wait_for_osc_ready(PLL2);
+
+
+	/*
+	 * Set the PLL multiplication factor to 9.
+	 * 8MHz (external) * 9 (multiplier) = 72MHz
+	 */
+	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9);
+
+	/* Select PREDIV as PLL source. */
+	rcc_set_pll_source(RCC_CFGR_PLLSRC_PREDIV1_CLK);
+
+	/*
+	 * External frequency undivided before entering PLL
+	 * (only valid/needed for HSE).
+	 */
+	rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
+
+	/* Enable PLL oscillator and wait for it to stabilize. */
+	rcc_osc_on(PLL);
+	rcc_wait_for_osc_ready(PLL);
+
+	/* Select PLL as SYSCLK source. */
+	rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+	/* Set the peripheral clock frequencies used */
+	rcc_ppre1_frequency = 36000000;
+	rcc_ppre2_frequency = 72000000;
+}
+
 void rcc_backupdomain_reset(void)
 {
 	/* Set the backup domain software reset. */
-- 
1.7.3.4