[libopenstm32-devel] (no subject)

[Uwe B. <bo...@el...>]

Hello,

please review appended patch and apply or let me know any possible problems

Bye

-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>From ba2d229f0eb4505be64d2e146f0897fa65c26358 Mon Sep 17 00:00:00 2001
From: Uwe Bonnes <bo...@el...>
Date: Sun, 3 Jul 2011 18:02:48 +0200
Subject: Add definitions aroundRCC_CFGR2 and PLL2

---
 include/libopencm3/stm32/rcc.h |   20 +++++++++-
 lib/stm32/rcc.c                |   86 ++++++++++++++++++++++++++++++++++++++++
 lib/stm32/rtc.c                |    1 +
 3 files changed, 106 insertions(+), 1 deletions(-)

diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
index 1072445..d000567 100644
--- a/include/libopencm3/stm32/rcc.h
+++ b/include/libopencm3/stm32/rcc.h
@@ -351,6 +351,24 @@
 #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16	0xe
 #define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20	0xf
 
+/* PREDIV1: PREDIV1 division factor */
+#define RCC_CFGR2_PREDIV1_NODIV			0x0
+#define RCC_CFGR2_PREDIV1_DIV2			0x1
+#define RCC_CFGR2_PREDIV1_DIV3			0x2
+#define RCC_CFGR2_PREDIV1_DIV4			0x3
+#define RCC_CFGR2_PREDIV1_DIV5			0x4
+#define RCC_CFGR2_PREDIV1_DIV6			0x5
+#define RCC_CFGR2_PREDIV1_DIV7			0x6
+#define RCC_CFGR2_PREDIV1_DIV8			0x7
+#define RCC_CFGR2_PREDIV1_DIV9			0x8
+#define RCC_CFGR2_PREDIV1_DIV10			0x9
+#define RCC_CFGR2_PREDIV1_DIV11			0xa
+#define RCC_CFGR2_PREDIV1_DIV12			0xb
+#define RCC_CFGR2_PREDIV1_DIV13			0xc
+#define RCC_CFGR2_PREDIV1_DIV14			0xd
+#define RCC_CFGR2_PREDIV1_DIV15			0xe
+#define RCC_CFGR2_PREDIV1_DIV16			0xf
+
 /* PREDIV2: PREDIV2 division factor */
 #define RCC_CFGR2_PREDIV2_NODIV			0x0
 #define RCC_CFGR2_PREDIV2_DIV2			0x1
@@ -376,7 +394,7 @@ extern u32 rcc_ppre2_frequency;
 /* --- Function prototypes ------------------------------------------------- */
 
 typedef enum {
-	PLL, HSE, HSI, LSE, LSI
+       PLL, HSE, HSI, LSE, LSI, PLL2
 } osc_t;
 
 void rcc_osc_ready_int_clear(osc_t osc);
diff --git a/lib/stm32/rcc.c b/lib/stm32/rcc.c
index f646168..1da462a 100644
--- a/lib/stm32/rcc.c
+++ b/lib/stm32/rcc.c
@@ -44,6 +44,9 @@ void rcc_osc_ready_int_clear(osc_t osc)
 	case LSI:
 		RCC_CIR |= RCC_CIR_LSIRDYC;
 		break;
+	case PLL2:
+		RCC_CIR |= RCC_CIR_PLL2RDYC;
+		break;
 	}
 }
 
@@ -65,6 +68,9 @@ void rcc_osc_ready_int_enable(osc_t osc)
 	case LSI:
 		RCC_CIR |= RCC_CIR_LSIRDYIE;
 		break;
+	case PLL2:
+		RCC_CIR |= RCC_CIR_PLL2RDYIE;
+		break;
 	}
 }
 
@@ -86,6 +92,9 @@ void rcc_osc_ready_int_disable(osc_t osc)
 	case LSI:
 		RCC_CIR &= ~RCC_CIR_LSIRDYIE;
 		break;
+	case PLL2:
+		RCC_CIR &= ~RCC_CIR_PLL2RDYIE;
+		break;
 	}
 }
 
@@ -107,6 +116,9 @@ int rcc_osc_ready_int_flag(osc_t osc)
 	case LSI:
 		return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
 		break;
+	case PLL2:
+		return ((RCC_CIR & RCC_CIR_PLL2RDYF) != 0);
+		break;
 	}
 
 	/* Shouldn't be reached. */
@@ -141,6 +153,9 @@ void rcc_wait_for_osc_ready(osc_t osc)
 	case LSI:
 		while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
 		break;
+	case PLL2:
+		while ((RCC_CR & RCC_CR_PLL2RDY) == 0);
+		break;
 	}
 }
 
@@ -162,6 +177,9 @@ void rcc_osc_on(osc_t osc)
 	case LSI:
 		RCC_CSR |= RCC_CSR_LSION;
 		break;
+	case PLL2:
+		RCC_CR |= RCC_CR_PLL2ON;
+		break;
 	}
 }
 
@@ -183,6 +201,9 @@ void rcc_osc_off(osc_t osc)
 	case LSI:
 		RCC_CSR &= ~RCC_CSR_LSION;
 		break;
+	case PLL2:
+		RCC_CR &= ~RCC_CR_PLL2ON;
+		break;
 	}
 }
 
@@ -205,6 +226,7 @@ void rcc_osc_bypass_enable(osc_t osc)
 	case LSE:
 		RCC_BDCR |= RCC_BDCR_LSEBYP;
 		break;
+	case PLL2:
 	case PLL:
 	case HSI:
 	case LSI:
@@ -223,6 +245,7 @@ void rcc_osc_bypass_disable(osc_t osc)
 		RCC_BDCR &= ~RCC_BDCR_LSEBYP;
 		break;
 	case PLL:
+	case PLL2:
 	case HSI:
 	case LSI:
 		/* Do nothing, only HSE/LSE allowed here. */
@@ -331,6 +354,69 @@ void rcc_set_usbpre(u32 usbpre)
 	RCC_CFGR = (reg32 | (usbpre << 22));
 }
 
+void rcc_set_prediv2(u32 prediv2)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0xf<<4);
+        RCC_CFGR2 = (reg32 | (prediv2 << 4));
+}
+
+void rcc_set_prediv1(u32 prediv1)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0xf);
+        RCC_CFGR2 = (reg32 | prediv1);
+}
+
+void rcc_set_pll2mult(u32 pll2mult)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0xf << 8);
+        RCC_CFGR2 = (reg32 | (pll2mult << 8));
+}
+
+void rcc_set_pll3mult(u32 pll3mult)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0xf << 12);
+        RCC_CFGR2 = (reg32 | (pll3mult << 12));
+}
+
+void rcc_set_prediv1src(u32 prediv1src)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0x1 << 16);
+        RCC_CFGR2 = (reg32 | (prediv1src << 16));
+}
+
+void rcc_set_i2s2src(u32 i2s2src)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0x1 << 17);
+        RCC_CFGR2 = (reg32 | (i2s2src << 17));
+}
+
+void rcc_set_i2s3src(u32 i2s3src)
+{
+        u32 reg32;
+
+        reg32 = RCC_CFGR2;
+        reg32 &= ~(0x1 << 18);
+        RCC_CFGR2 = (reg32 | (i2s3src << 18));
+}
+
 u32 rcc_system_clock_source(void)
 {
 	/* Return the clock source which is used as system clock. */
diff --git a/lib/stm32/rtc.c b/lib/stm32/rtc.c
index 4495641..bc9bf1e 100644
--- a/lib/stm32/rtc.c
+++ b/lib/stm32/rtc.c
@@ -67,6 +67,7 @@ void rtc_awake_from_off(osc_t clock_source)
 		RCC_BDCR |= (1 << 9) | (1 << 8);
 		break;
 	case PLL:
+	case PLL2:
 	case HSI:
 		/* Unusable clock source, here to prevent warnings. */
 		/* Turn off clock sources to RTC. */
-- 
1.7.3.4