Hello,
I think there's a bug in STM32 nvic_set_priority in nvic.c
There is that line:
NVIC_IPR(irqn/4) |= (priority << ((irqn % 4) * 8));
irqn/4 is right to choose the array index of the priority register array
but not to choose the right memory address because STM32
microcontrollers addresses there registers bytewise.
So if NVIC_IPR0 has the address offset 0x400 NVIC_IPR1 has the offset
0x404 and so on.
Because of set you can address the priority registers directly by 0x400
+ irqn and this line is enough to set the priority:
NVIC_IPR(irqn) |= priority;
I had problems with the priority of my interrupt because it has fired
allthough the basepri register was set to an higher priority as my
interrupt was configured.
After I had changed the line in nvic.c my interrupt doesn't fire if the
basepri register is that to an higher priority.
Regards,
Tobias Groll
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