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From: e39 <e3...@fr...> - 2010-09-22 08:03:44
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I'm experimenting on the STM32F103 MCU and I'am surprised about what this code does (in examples/other/systick/systick.c): /* 72MHz / 8 => 9000000 counts per second */ systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB_DIV8); /* 9000000/9000 = 1000 overflows per second - every 1ms one interrupt */ systick_set_reload(9000); I've found that the LED does not toggle every 1s... According to the comment and the symbol STK_CTRL_CLKSOURCE_AHB_DIV8, systick'c clock source is core clock divided by 8. Diving into the Core M3 datasheet, I've found that bit 2 of SysTick control and status register selects the clock source, not a divider: stk clk src = (STK_CTRL bit 2 == 1) ? core clock : ext ref clk I do not know yet what is this external reference clock but I've tried: systick_set_clocksource(STK_CTRL_CLKSOURCE_AHB); systick_set_reload(72000); and now the LED does toggle every 1s. Maybe it would be wise to rename: STK_CTRL_CLKSOURCE_AHB_DIV8 as STK_CTRL_CLKSOURCE_EXT and STK_CTRL_CLKSOURCE_AHB as STK_CTRL_CLKSOURCE_CORE or something like that. Tell me if I'm completely wrong, I need to learn! -- Christophe |
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From: Gareth M. <ga...@bl...> - 2010-09-20 20:45:03
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Hi Uwe Please checkout the current USB code and headers to assess how much of > it can be used/reused or merged with yours, Piotr Esden-Tempski already > worked on the USB stuff a while ago, the last status was that parts of > it worked, but not everything IIRC. > > I've looked at the USB support in git on SF, and it appears there are only register definitions and access macros. Has any more work been done that is not in the main repository? I have a mostly working USB implementation. Not everything is done yet, it doesn't support double buffered bulk transfers or isochronous transfers yet. I'm busy reworking the low level part to work with the register definitions in libopenstm32. I'll post a complete patch to the list when I've got it working (I don't have hardware to test at the moment, maybe this coming weekend.) I use the "usb.h" from libusb for descriptor definitions, this is more complete than the usb_desc.h in libopenstm32, I suggest we adopt this file. To give you an idea, I've posted an example of a cdcacm device. Feel free to comment. Let me know what your SF username is, I can give you wiki access etc. > if you want. > My SF username is 'gsmcmullin'. Regards, Gareth -- *Black Sphere Technologies Ltd.* Web: www.blacksphere.co.nz Mobile: +64 27 777 2182 Tel: +64 9 478 8885 Skype: gareth.mcmullin LinkedIn: http://nz.linkedin.com/in/gsmcmullin |
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From: Linus C. <li...@li...> - 2010-09-02 21:34:00
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I have it!! change: usart_set_mode(USART3, USART_MODE_TX); to: usart_set_mode(USART3, USART_MODE_TX_RX); and change: ch = USART_DR(USART3) & 0x00f; to: ch = usart_recv(USART3); And that is it! On Thu, Sep 2, 2010 at 5:12 PM, Linus Casassa <li...@li...> wrote: > Hi. > > I am having problems receiving data from usart3. What am I missing? > > The function usart_recv(USART3); does not return when I put data to > the rx pin and the interrupt does not get called. > > Does someone have an example of usart use? > > Thanks > > -- > Linus Casassa > Estudiante Ingeniería Civil Electrónica > Universidad Técnica Federico Santa María > Fono: 56-9-97776941 > -- Linus Casassa Estudiante Ingeniería Civil Electrónica Universidad Técnica Federico Santa María Fono: 56-9-97776941 |
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From: Linus C. <li...@li...> - 2010-09-02 21:13:12
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Hi. I am having problems receiving data from usart3. What am I missing? The function usart_recv(USART3); does not return when I put data to the rx pin and the interrupt does not get called. Does someone have an example of usart use? Thanks -- Linus Casassa Estudiante Ingeniería Civil Electrónica Universidad Técnica Federico Santa María Fono: 56-9-97776941 |
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From: Linus C. <li...@li...> - 2010-08-15 20:03:40
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I'm new to this... I added: /* without this the dma interrupt routine will never be called */ nvic_enable_irq(NVIC_DMA1_CHANNEL1_IRQ); nvic_set_priority(NVIC_DMA1_CHANNEL1_IRQ, 2); in the main function so that void dma1_channel1_isr() interrupt is called. :) On Sat, Aug 14, 2010 at 10:01 AM, Linus Casassa <li...@li...> wrote: > Hi Tommi > > This example is just what I need! Thank you! > > I have a question: Why did you call adc_setup() twice in your ADC+DMA example? > > On Sat, Aug 14, 2010 at 9:58 AM, Linus Casassa <li...@li...> wrote: >> Hello, >> >> I've created an ADC+DMA example. It needs some changes/advancements to >> the lib from my git repository. >> It reads out 3 ADC channels (3d accel sensor) and put the converted >> values per dma to an array. The array is shiftet out via USART1. >> >> Example is attached. >> >> cu Tommi >> > > > > -- > Linus Casassa > Estudiante Ingeniería Civil Electrónica > Universidad Técnica Federico Santa María > Fono: 56-9-97776941 > -- Linus Casassa Estudiante Ingeniería Civil Electrónica Universidad Técnica Federico Santa María Fono: 56-9-97776941 |
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From: Linus C. <li...@li...> - 2010-08-14 14:01:46
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Hi Tommi This example is just what I need! Thank you! I have a question: Why did you call adc_setup() twice in your ADC+DMA example? On Sat, Aug 14, 2010 at 9:58 AM, Linus Casassa <li...@li...> wrote: > Hello, > > I've created an ADC+DMA example. It needs some changes/advancements to > the lib from my git repository. > It reads out 3 ADC channels (3d accel sensor) and put the converted > values per dma to an array. The array is shiftet out via USART1. > > Example is attached. > > cu Tommi > -- Linus Casassa Estudiante Ingeniería Civil Electrónica Universidad Técnica Federico Santa María Fono: 56-9-97776941 |
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From: Edward C. <che...@gm...> - 2010-06-07 08:59:06
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Hello, Just started the timer.c file. No where near complete but I think it conforms to the libopenstm32 style, so should be a start. I will add further when I can. Edward |
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From: Thomas O. <to...@vi...> - 2010-05-12 16:14:52
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Hi Mark, I've added this to my repo. Some cosmetic changes to the coding style and the example will follow. cu Tommi Am Mittwoch, den 12.05.2010, 12:51 +1200 schrieb Mark Butler: > Hi, > > Thanks everyone for your help with the RTC. I have attached the EXTI > definitions and functions I have been using, as well as an example. Feel > free to make changes. > > Cheers, > Mark > ------------------------------------------------------------------------------ > > _______________________________________________ > libopenstm32-devel mailing list > lib...@li... > https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel |
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From: Thomas O. <to...@vi...> - 2010-05-12 14:31:04
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updated in my repo. cu Tommi Am Mittwoch, den 12.05.2010, 07:03 -0700 schrieb Jim: > Mark pointed out an error I made in the set counter function. Attached > is a fixed version, including the changes Thomas made to the RCC > header. > > Cheers, > > Jim > > > > ------------------------------------------------------------------------------ > > _______________________________________________ > libopenstm32-devel mailing list > lib...@li... > https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel |
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From: Jim <lor...@y7...> - 2010-05-12 14:16:54
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/* * This file is part of the libopenstm32 project. * * Copyright (C) 2010 Uwe Hermann <uw...@he...> * Copyright (C) 2010 Lord James <lor...@y7...> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <libopenstm32/rcc.h> #include <libopenstm32/rtc.h> #include <libopenstm32/pwr.h> void rtc_awake_from_off(osc_t clock_source) { u32 reg32; /* Enable power and backup interface clocks. */ RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* Enable access to the backup registers and the RTC. */ PWR_CR |= PWR_CR_DBP; /* * Reset the backup domain, clears everything RTC related. * If not wanted use the rtc_awake_from_standby() function. */ rcc_backupdomain_reset(); switch (clock_source) { case LSE: /* Turn the LSE on and wait while it stabilises. */ RCC_BDCR |= RCC_BDCR_LSEON; while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0); /* Choose LSE as the RTC clock source. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); RCC_BDCR |= (1 << 8); break; case LSI: /* Turn the LSI on and wait while it stabilises. */ RCC_CSR |= RCC_CSR_LSION; while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0); /* Choose LSI as the RTC clock source. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); RCC_BDCR |= (1 << 9); break; case HSE: /* Turn the HSE on and wait while it stabilises. */ RCC_CR |= RCC_CR_HSEON; while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0); /* Choose HSE as the RTC clock source. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); RCC_BDCR |= (1 << 9) | (1 << 8); break; case PLL: case HSI: /* Unusable clock source, here to prevent warnings. */ /* Turn off clock sources to RTC. */ RCC_BDCR &= ~((1 << 8) | (1 << 9)); break; } /* Enable the RTC. */ RCC_BDCR |= RCC_BDCR_RTCEN; /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ RTC_CRL &= ~RTC_CRL_RSF; while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); /* Wait for the last write operation to finish. */ /* TODO: Necessary? */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); } void rtc_enter_config_mode(void) { u32 reg32; /* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); /* Enter configuration mode. */ RTC_CRL |= RTC_CRL_CNF; } void rtc_exit_config_mode(void) { /* u32 reg32; */ /* Exit configuration mode. */ RTC_CRL &= ~RTC_CRL_CNF; /* Wait until the RTOFF bit is 1 (our RTC register write finished). */ /* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */ /* TODO: Unnecessary since we poll the bit on config entry(?) */ } void rtc_set_alarm_time(u32 alarm_time) { rtc_enter_config_mode(); RTC_ALRL = (alarm_time & 0x0000ffff); RTC_ALRH = (alarm_time & 0xffff0000) >> 16; rtc_exit_config_mode(); } void rtc_enable_alarm(void) { rtc_enter_config_mode(); RTC_CRH |= RTC_CRH_ALRIE; rtc_exit_config_mode(); } void rtc_disable_alarm(void) { rtc_enter_config_mode(); RTC_CRH &= ~RTC_CRH_ALRIE; rtc_exit_config_mode(); } void rtc_set_prescale_val(u32 prescale_val) { rtc_enter_config_mode(); RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */ RTC_PRLH = (prescale_val & 0x000f0000) >> 16; /* PRL[19:16] */ rtc_exit_config_mode(); } u32 rtc_get_counter_val(void) { return (RTC_CNTH << 16) | RTC_CNTL; } u32 rtc_get_prescale_div_val(void) { return (RTC_DIVH << 16) | RTC_DIVL; } u32 rtc_get_alarm_val(void) { return (RTC_ALRH << 16) | RTC_ALRL; } void rtc_set_counter_val(u32 counter_val) { rtc_enter_config_mode(); RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */ RTC_CNTL = counter_val & 0x0000ffff; /* CNT[15:0] */ rtc_exit_config_mode(); } void rtc_interrupt_enable(rtcflag_t flag_val) { rtc_enter_config_mode(); /* Set the correct interrupt enable. */ switch(flag_val) { case RTC_SEC: RTC_CRH |= RTC_CRH_SECIE; break; case RTC_ALR: RTC_CRH |= RTC_CRH_ALRIE; break; case RTC_OW: RTC_CRH |= RTC_CRH_OWIE; break; } rtc_exit_config_mode(); } void rtc_interrupt_disable(rtcflag_t flag_val) { rtc_enter_config_mode(); /* Disable the correct interrupt enable. */ switch(flag_val) { case RTC_SEC: RTC_CRH &= ~RTC_CRH_SECIE; break; case RTC_ALR: RTC_CRH &= ~RTC_CRH_ALRIE; break; case RTC_OW: RTC_CRH &= ~RTC_CRH_OWIE; break; } rtc_exit_config_mode(); } void rtc_clear_flag(rtcflag_t flag_val) { /* Configuration mode not needed. */ /* Clear the correct flag. */ switch(flag_val) { case RTC_SEC: RTC_CRL &= ~RTC_CRL_SECF; break; case RTC_ALR: RTC_CRL &= ~RTC_CRL_ALRF; break; case RTC_OW: RTC_CRL &= ~RTC_CRL_OWF; break; } } u32 rtc_check_flag(rtcflag_t flag_val) { u32 reg32; /* Read correct flag. */ switch(flag_val) { case RTC_SEC: reg32 = RTC_CRL & RTC_CRL_SECF; break; case RTC_ALR: reg32 = RTC_CRL & RTC_CRL_ALRF; break; case RTC_OW: reg32 = RTC_CRL & RTC_CRL_OWF; break; default: reg32 = 0; break; } return reg32; } void rtc_awake_from_standby(void) { u32 reg32; /* Enable power and backup interface clocks. */ RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* Enable access to the backup registers and the RTC. */ PWR_CR |= PWR_CR_DBP; /* Wait for the RSF bit in RTC_CRL to be set by hardware. */ RTC_CRL &= ~RTC_CRL_RSF; while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0); /* Wait for the last write operation to finish. */ /* TODO: Necessary? */ while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); } void rtc_auto_awake(osc_t clock_source, u32 prescale_val) { u32 reg32; /* Enable power and backup interface clocks. */ RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN); /* Enable access to the backup registers and the RTC. */ /* TODO: Not sure if this is necessary to just read the flag. */ PWR_CR |= PWR_CR_DBP; if ((reg32 = RCC_BDCR & RCC_BDCR_RTCEN) != 0) { rtc_awake_from_standby(); } else { rtc_awake_from_off(clock_source); rtc_set_prescale_val(prescale_val); } } |
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From: Thomas O. <to...@vi...> - 2010-05-12 13:51:08
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Hi Mark, thanks for your work. But it should match the names in the documentation. I will merge it with the AFIO parts today and put it in my repo. So it will change a little bit... cu Tommi Am Mittwoch, den 12.05.2010, 14:11 +1200 schrieb Mark Butler: > although the the example I posted did work, the clock wasn't enabled on > GPIOA. so here is the fixed version. > > Cheers, > Mark > ------------------------------------------------------------------------------ > > _______________________________________________ > libopenstm32-devel mailing list > lib...@li... > https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel |
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From: Mark B. <mb...@ph...> - 2010-05-12 02:11:42
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although the the example I posted did work, the clock wasn't enabled on GPIOA. so here is the fixed version. Cheers, Mark |
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From: Mark B. <mb...@ph...> - 2010-05-12 00:51:33
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Hi, Thanks everyone for your help with the RTC. I have attached the EXTI definitions and functions I have been using, as well as an example. Feel free to make changes. Cheers, Mark |
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From: Thomas O. <to...@vi...> - 2010-05-11 13:14:55
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Hi, during some tests with the new rtc/rcc functions i saw that we there didnt followed our coding style. So I've renamed all register bit names to RCC_Registername_bitname. Correcting the RCC functions around interrupts showed some displacements. Means we changed in a register the bits defined for another. Now all seems consistent. All examples are changed also to the new bitnames. If you have code that didt now the bit names anymore especially during clock enabling for function block, then it needs a RCC_APBxENR_Bitname instead of Bitname only. Changes are only in my private git til now. Test it please!!! cu Tommi |
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From: Lord J. <lor...@y7...> - 2010-05-09 23:41:05
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Hi, Checked the example and it still works. Cheers, Jim ________________________________ From: Uwe Hermann <uw...@he...> To: Lord James <lor...@y7...> Cc: libopenstm32-devel <lib...@li...> Sent: Mon, 10 May, 2010 8:16:05 AM Subject: Re: [libopenstm32-devel] Complete RTC functions Hi, On Sun, May 09, 2010 at 06:58:21AM -0700, Lord James wrote: > Attached are updated rtc.c, rtc.h, rcc.h, rcc.c files and a real time clock example. > > I think the RTC library is pretty complete now, and I added one function to the rcc library. Even though it only relates to the real time clock module, it only changes an RCC register. > > The example simply prints the contents of the counter register in binary over the USART1, using the seconds interrupt for timing. Thanks, I merged your changes with some cosmetic changes and simplifications. Please let me know if the example (which I also committed as examples/other/rtc/*) still works, didn't yet have the time to test or fully review the code yet. Maybe some changes will follow (consistency renames or the like). I also added your copyright line to the rtc.c and example file. Thanks, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org ------------------------------------------------------------------------------ _______________________________________________ libopenstm32-devel mailing list lib...@li... https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel |
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From: Uwe H. <uw...@he...> - 2010-05-09 22:46:19
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Hi, On Sun, May 09, 2010 at 06:58:21AM -0700, Lord James wrote: > Attached are updated rtc.c, rtc.h, rcc.h, rcc.c files and a real time clock example. > > I think the RTC library is pretty complete now, and I added one function to the rcc library. Even though it only relates to the real time clock module, it only changes an RCC register. > > The example simply prints the contents of the counter register in binary over the USART1, using the seconds interrupt for timing. Thanks, I merged your changes with some cosmetic changes and simplifications. Please let me know if the example (which I also committed as examples/other/rtc/*) still works, didn't yet have the time to test or fully review the code yet. Maybe some changes will follow (consistency renames or the like). I also added your copyright line to the rtc.c and example file. Thanks, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org |
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From: Lord J. <lor...@y7...> - 2010-05-09 13:58:29
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/* * This file is part of the libopenstm32 project. * * Copyright (C) 2009 Uwe Hermann <uw...@he...> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <libopenstm32/rcc.h> #include <libopenstm32/gpio.h> #include <libopenstm32/usart.h> #include <libopenstm32/rtc.h> #include <libopenstm32/power.h> #include <libopenstm32/nvic.h> void clock_setup(void) { rcc_clock_setup_in_hse_8mhz_out_72mhz(); /* Enable GPIOC clock. */ rcc_peripheral_enable_clock(&RCC_APB2ENR, IOPCEN); /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ rcc_peripheral_enable_clock(&RCC_APB2ENR, IOPAEN); rcc_peripheral_enable_clock(&RCC_APB2ENR, USART1EN); } void usart_setup(void) { /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX); /* Setup UART parameters. */ usart_set_baudrate(USART1, 38400); usart_set_databits(USART1, 8); usart_set_stopbits(USART1, USART_STOPBITS_1); usart_set_mode(USART1, USART_MODE_TX); usart_set_parity(USART1, USART_PARITY_NONE); usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE); /* Finally enable the USART. */ usart_enable(USART1); } void gpio_setup(void) { /* Set GPIO12 (in GPIO port C) to 'output push-pull'. */ gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); } void nvic_setup() { /* without this the rtc interrupt routine will never be called */ nvic_enable_irq(NVIC_RTC_IRQ); nvic_set_priority(NVIC_RTC_IRQ, 1); } void rtc_isr(void) { volatile u32 j = 0,c = 0; /* The interrupt flag isn't cleared by hardware, we have to do it */ rtc_clear_flag(RTC_SEC); /* Visual output */ gpio_toggle(GPIOC, GPIO12); /*Let c be the currecnt counter value */ c = rtc_get_counter_val(); /* Display the current counter value in binary via USART1*/ for (j=0;j<32;j++) { if((c & (0x80000000>>j)) != 0) { usart_send(USART1, '1'); } else { usart_send(USART1, '0'); } } usart_send(USART1, '\n'); } int main(void) { /* Start the clocks */ clock_setup(); /* Setup the GPIOs */ gpio_setup(); /* Setup the USART module */ usart_setup(); /* If the rtc is pre-configured just allow access, don't reconfigure */ /* Otherwise enable it with the LSE as clock source */ /* and 0x7fff as prescale value */ rtc_auto_awake(LSE,0x7fff); /* Setup the RTC interrupt */ nvic_setup(); /* Enable the RTC interrupt to occur off the SEC flag */ rtc_interrupt_enable(RTC_SEC); while (1) {} return 0; } |
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From: Lord J. <lor...@y7...> - 2010-05-08 11:12:14
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Hi, I hope this goes to the right place since I just joined the mailing list and don't have the original email.
@ Mark Butler: I have had success with the RTC, after a lot of poking an prodding.
Here's my working code, avoiding all the current helper functions so I could get it straight in my head:
u32 reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (PWREN | BKPEN);
/* Enable access to the backup registers and the RTC. */
/* PWR definitions implemented, enough to use. */
PWR_CR |= PWR_CR_DBP;
/* Simulate a power off situation */
RCC_BDCR |= BDRST;
RCC_BDCR &= ~BDRST;
/* Turn the LSE on */
RCC_BDCR |= LSEON;
/* Wait while it stabilises */
while((reg32 = (RCC_BDCR & LSERDY)) == 0);
/* Choose LSE as the RTC clock source */
RCC_BDCR |= (1<<8);
/* Enable the RTC */
RCC_BDCR |= RTCEN;
/* Wait for the RSF bit in RTC_CRL to be set by hardware */
RTC_CRL &= ~RTC_CRL_RSF;
while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0);
/* Wait for the last write operation to finish
(shouldn't have to wait but it prevents any stupidity
on my part when I set the prescaler later) */
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
Over the next couple of days I'll flesh out the RTC library a bit more.
Cheers,
Jim
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From: Mark B. <mb...@ph...> - 2010-05-05 05:14:39
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Hi guys,
I've been doing some work on the real time clock API but for some reason
I cannot get it to work.
I am trying to write an example that uses the LSE as the RTC clock and
uses alarm interrupts to flash an LED.
Most of the time the code hangs while waiting for the LSE to stabilize
or when waiting for RTC registers to synchronise.
Here is an example of all i'm trying to do:
void clock_setup()
{
RCC_APB1ENR |= (PWREN |BKPEN); //enable backup domain clock
pwr_enable_backup_domain_write();
//reset backup domain
RCC_BDCR |= BDRST;
RCC_BDCR &= ~BDRST;
rcc_osc_on(LSE); //enable LSE
rcc_wait_for_osc_ready(LSE); //wait until lse is stable
rtc_set_clock_source(LSE); //set LSE as RTC clock source
rtc_enable(); //enable real time clock
}
once this is working i can then call the prescaler and counter functions
I have written.
Have any of you had any success with libopenstm32 and RTC?
Thanks for your help
Mark Butler
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From: Thomas O. <to...@vi...> - 2010-05-03 17:01:42
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Hello, I've added the definitions for CRC and BKP units to my repo. cu Tommi |
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From: Thomas O. <to...@vi...> - 2010-05-03 13:41:07
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Hello, I've added the definitions for the WWDG and POWER units to my repo. cu Tommi |
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From: Uwe H. <uw...@he...> - 2010-05-02 23:45:22
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Hi, On Sun, May 02, 2010 at 06:00:25PM +0200, Thomas Otto wrote: > I've fixed a bug in the adc for setting conversion groups larger than 6. > And i've commited an SPI example which drives an dogm128 LCD display. Great, thanks! Merged. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org |
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From: Thomas O. <to...@vi...> - 2010-05-02 16:00:47
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Hello, I've fixed a bug in the adc for setting conversion groups larger than 6. And i've commited an SPI example which drives an dogm128 LCD display. cu tommi |
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From: Thomas O. <to...@vi...> - 2010-04-02 20:27:24
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Oops little typo... Patch attached. cu Tommi Am Freitag, den 02.04.2010, 22:16 +0200 schrieb Thomas Otto: > I've completed the spi.h now. Complete patch attached and also in my > repo (https://www.viadmin.org/git/libopenstm32.git). > > cu Tommi > > Am Dienstag, den 30.03.2010, 22:35 +0200 schrieb Thomas Otto: > > Hi, > > > > I've made some additions to the spi.h and .c. I've just noted that the > > spi.h isnt complete at all. I will make this in the next days... > > And as usual i will provide an example in the next days (hopefully > > DOGM-128 LCD). > > Patch attached and in my repo. > > > > cu Tommi > > ------------------------------------------------------------------------------ > > Download Intel® Parallel Studio Eval > > Try the new software tools for yourself. Speed compiling, find bugs > > proactively, and fine-tune applications for parallel performance. > > See why Intel Parallel Studio got high marks during beta. > > http://p.sf.net/sfu/intel-sw-dev > > _______________________________________________ libopenstm32-devel mailing list lib...@li... https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel > > ------------------------------------------------------------------------------ > Download Intel® Parallel Studio Eval > Try the new software tools for yourself. Speed compiling, find bugs > proactively, and fine-tune applications for parallel performance. > See why Intel Parallel Studio got high marks during beta. > http://p.sf.net/sfu/intel-sw-dev > _______________________________________________ libopenstm32-devel mailing list lib...@li... https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel |
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From: Thomas O. <to...@vi...> - 2010-04-02 20:16:57
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I've completed the spi.h now. Complete patch attached and also in my repo (https://www.viadmin.org/git/libopenstm32.git). cu Tommi Am Dienstag, den 30.03.2010, 22:35 +0200 schrieb Thomas Otto: > Hi, > > I've made some additions to the spi.h and .c. I've just noted that the > spi.h isnt complete at all. I will make this in the next days... > And as usual i will provide an example in the next days (hopefully > DOGM-128 LCD). > Patch attached and in my repo. > > cu Tommi > ------------------------------------------------------------------------------ > Download Intel® Parallel Studio Eval > Try the new software tools for yourself. Speed compiling, find bugs > proactively, and fine-tune applications for parallel performance. > See why Intel Parallel Studio got high marks during beta. > http://p.sf.net/sfu/intel-sw-dev > _______________________________________________ libopenstm32-devel mailing list lib...@li... https://lists.sourceforge.net/lists/listinfo/libopenstm32-devel |
