[libopencm3-devel] STM32F4 USB OTG HS Core / core soft reset does not work

[Christian Cier-Z. <c....@gm...>]

Hello list,

I would like to use the USB OTG HS part of my Olimex STM-H407. The board 
uses a STM32F407ZG.
The sample code which comes with the board uses the USB OTG ST libraries 
to handle the USB part.
This works without an problem, especially the USB OTG Device demo which 
emulates a USB HID mouse on the OTG HS core with the embedded FS phy.

I would like to get the USB OTG HS core running with libopencm3 as well. 
I have studied the documentation and found out that the cores (OTG FS 
and OTG HS) are very similiar.
Therefore, I have copied the usb_f107 driver. I have replaced all OTG_FS 
prefixes with OTG_HS and made sure that the correct base address is used.
https://github.com/ccier/libopencm3/blob/master/lib/usb/usb_f407.c

I would like to get a simple bootloader (forked version) with USB CDC 
support running on my board:
https://github.com/ccier/Bootloader
The original version uses the OTG FS core. Unfortunately, this core is 
connected to the USB Type A receptacle on the board for host mode.
The mini USB connector is connected to the OTG HS core. That's why I 
would like to get this running on the OTG HS core.

After fiddling around for a couple of days now, I have not managed to 
get the OTG HS core to properly to the soft reset.

     /* Do core soft reset. */
     OTG_HS_GRSTCTL |= OTG_HS_GRSTCTL_CSRST;
     while (OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_CSRST) ;

The while() loop never returns and I have no more idea why this happens.

Things I have tested and verified so far:
* the whole clock system (RCC regs including PLL and glock gate registers)
* clocks verified with oscilloscope on MCO1 and MCO2
* all necessary GPIO ports and pins (Port B: DM, DP ID)
* with JTAG IF and without

I have made sure that all those registers are the same as on the sample 
code project which is a IAR EWARM project.
Stepping through on IAR EWARM works flawlessly. Using Eclipse with GDB 
leads to the above behaviour.
My JTAG IF is Segger J-Link EDU.

At the moment I am lossed as I have run out of ideas what this might cause.
The CSRST bit never returns to 0 after setting it to 1.

Is there a clock missing which drives the clock domain of the USB part 
of the OTG HS core which is not documented properly?

The ST libs use the following sequence to enable the embedded FS phy on 
the OTG HS core:
This is NOT documented in the reference manual RM0090! It says 
"reserved" for bit7 (physel).

   else /* FS interface (embedded Phy) */
   {

     usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);;
     usbcfg.b.physel  = 1; /* FS Interface */
     USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
     /* Reset after a PHY select and set Host mode */
     // TODO
     USB_OTG_CoreReset(pdev);
     /* Deactivate the power down*/
     gccfg.d32 = 0;
     gccfg.b.pwdn = 1;

     gccfg.b.vbussensingA = 1 ;
     gccfg.b.vbussensingB = 1 ;


Any ideas?

Best regards,
Christian