The Lightweight Transaction Library / News: Recent posts

Stats from CacheGrind

In the SPAA paper submission, we claimed that we expected the vast majority of cache misses to be in public memory.

We can now confirm that stats from cachegrind back up this case.
Running the red-black-tree demo, with a tree depth of 10, we found that all but 0.5% of cache misses were for addresses in public memory.

These stats were only for a uniprocessor (cachegrind doesn't do SMP yet); however we see no reason why the results should not transfer to SMP.

Posted by Rob Ennals 2005-02-12

Provisional Cache-Miss Stats

Here are some provisional performance counter stats, running on a 4-way SPARC box. We'll hopefully soon be getting similar stats for the 106-way box and produce some pretty graphs.

When running on 4 processors, with a set power of 20. We get the following counts per executed transaction:

L2 misses per transaction:
Fraser=19.0 Ennals=7.8

L1 misses per transaction:
Fraser=37.4 Ennals=21.8

TLB misses per transaction:
Fraser=13.0 Ennals=2.9 ... read more

Posted by Rob Ennals 2005-02-10

Performance Counter Stats Coming Soon

We didn't quite have time to put cache miss stats in the submitted SPAA paper. We should hopefully be putting those stats up soon...

Posted by Rob Ennals 2005-02-10

SPAA05 Submission files online

We recently submitted a paper to SPAA05 describing the core algorithm behind LibLTX.

The paper itself, and the source code for the STM are now available for download.

Posted by Rob Ennals 2005-02-10

Source code coming soon

I'll be putting up a first version of the source code as soon as I've tidied it up a bit and finished off the paper.
Watch this space...

Posted by Rob Ennals 2005-02-07

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