The Lightweight Transaction Library News
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In the SPAA paper submission, we claimed that we expected the vast majority of cache misses to be in public memory.
We can now confirm that stats from cachegrind back up this case.
Running the red-black-tree demo, with a tree depth of 10, we found that all but 0.5% of cache misses were for addresses in public memory.
These stats were only for a uniprocessor (cachegrind doesn't do SMP yet); however we see no reason why the results should not transfer to SMP.