Menu
▾
▴
Re: [kvm-devel] QEMU/KVM [RFC]: add support for 128 PCI slots
|
From: Alexander G. <ag...@su...> - 2008-04-25 09:38:28
|
On Apr 25, 2008, at 3:01 AM, Marcelo Tosatti wrote:
>
> Add three PCI bridges to support 128 slots. Vendor and device_id have
> been stolen from my test box.
>
> I/O port addresses behind each bridge are statically allocated
> starting
> from 0x2000 with 0x1000 length. Once the bridge runs out of I/O space
> the guest (Linux at least) happily allocates outside of the region.
> That
> needs verification.
>
> I/O memory addresses are divided between 0xf0000000 -> APIC base.
>
> The PCI irq mapping function is also changed, there was the assumption
> that devices behind the bridge use the IRQ allocated to the bridge
> device itself, which is weird. Apparently this is how the SPARC ABP
> PCI
> host works (only user of the bridge code at the moment).
Is there any reason we're not using the _PIC function and give the OS
a clue on which APIC pin the device is? Right now everything boils
down to LNKA - LNKD which it does not have to.
It might even be a good idea to connect each PCI device to a specific
APIC pin, so we don't need to share too much, which might become a
problem with a lot of PCI devices. As far as I know there is no
limitation on how many pins an APIC may have.
>
>
> There was a copy&paste buglet in acpi-dsdt.dsl, slots 8 and 9 were
> sharing the same address, and that error was later copy&pasted to
> slots
> 24 and 25.
>
> Please review and give it a try (attached is the patch to increase the
> QEMU static tables).
>
> Index: kvm-userspace.pci2/hw/pci.c
> ===================================================================
> --- a/qemu/hw/pci.c
> +++ b/qemu/hw/pci.c
> @@ -532,6 +532,7 @@ uint32_t pci_data_read(void *opaque, uint32_t
> addr, int len)
> static void pci_set_irq(void *opaque, int irq_num, int level)
> {
> PCIDevice *pci_dev = (PCIDevice *)opaque;
> + PCIDevice *host_dev;
> PCIBus *bus;
> int change;
>
> @@ -539,13 +540,16 @@ static void pci_set_irq(void *opaque, int
> irq_num, int level)
> if (!change)
> return;
>
> +
> pci_dev->irq_state[irq_num] = level;
> + host_dev = pci_dev;
> for (;;) {
> - bus = pci_dev->bus;
> - irq_num = bus->map_irq(pci_dev, irq_num);
> - if (bus->set_irq)
> + bus = host_dev->bus;
> + if (bus->set_irq) {
> + irq_num = bus->map_irq(pci_dev, irq_num);
> break;
> - pci_dev = bus->parent_dev;
> + }
> + host_dev = bus->parent_dev;
> }
> bus->irq_count[irq_num] += change;
> bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] !
> = 0);
>
> Index: kvm-userspace.pci2/bios/acpi-dsdt.dsl
> ===================================================================
> --- kvm-userspace.pci2.orig/bios/acpi-dsdt.dsl
> +++ kvm-userspace.pci2/bios/acpi-dsdt.dsl
> @@ -208,218 +208,29 @@ DefinitionBlock (
> Name (_HID, EisaId ("PNP0A03"))
> Name (_ADR, 0x00)
> Name (_UID, 1)
> - Name(_PRT, Package() {
> - /* PCI IRQ routing table, example from ACPI 2.0a
> specification,
> - section 6.2.8.1 */
> - /* Note: we provide the same info as the PCI routing
> - table of the Bochs BIOS */
> -
> - // PCI Slot 0
> - Package() {0x0000ffff, 0, LNKD, 0},
> - Package() {0x0000ffff, 1, LNKA, 0},
> - Package() {0x0000ffff, 2, LNKB, 0},
> - Package() {0x0000ffff, 3, LNKC, 0},
> -
> - // PCI Slot 1
> - Package() {0x0001ffff, 0, LNKA, 0},
> - Package() {0x0001ffff, 1, LNKB, 0},
> - Package() {0x0001ffff, 2, LNKC, 0},
> - Package() {0x0001ffff, 3, LNKD, 0},
> -
> - // PCI Slot 2
> - Package() {0x0002ffff, 0, LNKB, 0},
> - Package() {0x0002ffff, 1, LNKC, 0},
> - Package() {0x0002ffff, 2, LNKD, 0},
> - Package() {0x0002ffff, 3, LNKA, 0},
> -
> - // PCI Slot 3
> - Package() {0x0003ffff, 0, LNKC, 0},
> - Package() {0x0003ffff, 1, LNKD, 0},
> - Package() {0x0003ffff, 2, LNKA, 0},
> - Package() {0x0003ffff, 3, LNKB, 0},
> -
> - // PCI Slot 4
> - Package() {0x0004ffff, 0, LNKD, 0},
> - Package() {0x0004ffff, 1, LNKA, 0},
> - Package() {0x0004ffff, 2, LNKB, 0},
> - Package() {0x0004ffff, 3, LNKC, 0},
> -
> - // PCI Slot 5
> - Package() {0x0005ffff, 0, LNKA, 0},
> - Package() {0x0005ffff, 1, LNKB, 0},
> - Package() {0x0005ffff, 2, LNKC, 0},
> - Package() {0x0005ffff, 3, LNKD, 0},
> -
> - // PCI Slot 6
> - Package() {0x0006ffff, 0, LNKB, 0},
> - Package() {0x0006ffff, 1, LNKC, 0},
> - Package() {0x0006ffff, 2, LNKD, 0},
> - Package() {0x0006ffff, 3, LNKA, 0},
> -
> - // PCI Slot 7
> - Package() {0x0007ffff, 0, LNKC, 0},
> - Package() {0x0007ffff, 1, LNKD, 0},
> - Package() {0x0007ffff, 2, LNKA, 0},
> - Package() {0x0007ffff, 3, LNKB, 0},
> -
> - // PCI Slot 8
> - Package() {0x0008ffff, 0, LNKD, 0},
> - Package() {0x0008ffff, 1, LNKA, 0},
> - Package() {0x0008ffff, 2, LNKB, 0},
> - Package() {0x0008ffff, 3, LNKC, 0},
> -
> - // PCI Slot 9
> - Package() {0x0008ffff, 0, LNKA, 0},
> - Package() {0x0008ffff, 1, LNKB, 0},
> - Package() {0x0008ffff, 2, LNKC, 0},
> - Package() {0x0008ffff, 3, LNKD, 0},
> -
> - // PCI Slot 10
> - Package() {0x000affff, 0, LNKB, 0},
> - Package() {0x000affff, 1, LNKC, 0},
> - Package() {0x000affff, 2, LNKD, 0},
> - Package() {0x000affff, 3, LNKA, 0},
> -
> - // PCI Slot 11
> - Package() {0x000bffff, 0, LNKC, 0},
> - Package() {0x000bffff, 1, LNKD, 0},
> - Package() {0x000bffff, 2, LNKA, 0},
> - Package() {0x000bffff, 3, LNKB, 0},
> -
> - // PCI Slot 12
> - Package() {0x000cffff, 0, LNKD, 0},
> - Package() {0x000cffff, 1, LNKA, 0},
> - Package() {0x000cffff, 2, LNKB, 0},
> - Package() {0x000cffff, 3, LNKC, 0},
> -
> - // PCI Slot 13
> - Package() {0x000dffff, 0, LNKA, 0},
> - Package() {0x000dffff, 1, LNKB, 0},
> - Package() {0x000dffff, 2, LNKC, 0},
> - Package() {0x000dffff, 3, LNKD, 0},
> -
> - // PCI Slot 14
> - Package() {0x000effff, 0, LNKB, 0},
> - Package() {0x000effff, 1, LNKC, 0},
> - Package() {0x000effff, 2, LNKD, 0},
> - Package() {0x000effff, 3, LNKA, 0},
> -
> - // PCI Slot 15
> - Package() {0x000fffff, 0, LNKC, 0},
> - Package() {0x000fffff, 1, LNKD, 0},
> - Package() {0x000fffff, 2, LNKA, 0},
> - Package() {0x000fffff, 3, LNKB, 0},
> -
> - // PCI Slot 16
> - Package() {0x0010ffff, 0, LNKD, 0},
> - Package() {0x0010ffff, 1, LNKA, 0},
> - Package() {0x0010ffff, 2, LNKB, 0},
> - Package() {0x0010ffff, 3, LNKC, 0},
> -
> - // PCI Slot 17
> - Package() {0x0011ffff, 0, LNKA, 0},
> - Package() {0x0011ffff, 1, LNKB, 0},
> - Package() {0x0011ffff, 2, LNKC, 0},
> - Package() {0x0011ffff, 3, LNKD, 0},
> -
> - // PCI Slot 18
> - Package() {0x0012ffff, 0, LNKB, 0},
> - Package() {0x0012ffff, 1, LNKC, 0},
> - Package() {0x0012ffff, 2, LNKD, 0},
> - Package() {0x0012ffff, 3, LNKA, 0},
> -
> - // PCI Slot 19
> - Package() {0x0013ffff, 0, LNKC, 0},
> - Package() {0x0013ffff, 1, LNKD, 0},
> - Package() {0x0013ffff, 2, LNKA, 0},
> - Package() {0x0013ffff, 3, LNKB, 0},
> -
> - // PCI Slot 20
> - Package() {0x0014ffff, 0, LNKD, 0},
> - Package() {0x0014ffff, 1, LNKA, 0},
> - Package() {0x0014ffff, 2, LNKB, 0},
> - Package() {0x0014ffff, 3, LNKC, 0},
> -
> - // PCI Slot 21
> - Package() {0x0015ffff, 0, LNKA, 0},
> - Package() {0x0015ffff, 1, LNKB, 0},
> - Package() {0x0015ffff, 2, LNKC, 0},
> - Package() {0x0015ffff, 3, LNKD, 0},
> -
> - // PCI Slot 22
> - Package() {0x0016ffff, 0, LNKB, 0},
> - Package() {0x0016ffff, 1, LNKC, 0},
> - Package() {0x0016ffff, 2, LNKD, 0},
> - Package() {0x0016ffff, 3, LNKA, 0},
> -
> - // PCI Slot 23
> - Package() {0x0017ffff, 0, LNKC, 0},
> - Package() {0x0017ffff, 1, LNKD, 0},
> - Package() {0x0017ffff, 2, LNKA, 0},
> - Package() {0x0017ffff, 3, LNKB, 0},
> -
> - // PCI Slot 24
> - Package() {0x0018ffff, 0, LNKD, 0},
> - Package() {0x0018ffff, 1, LNKA, 0},
> - Package() {0x0018ffff, 2, LNKB, 0},
> - Package() {0x0018ffff, 3, LNKC, 0},
> -
> - // PCI Slot 25
> - Package() {0x0018ffff, 0, LNKA, 0},
> - Package() {0x0018ffff, 1, LNKB, 0},
> - Package() {0x0018ffff, 2, LNKC, 0},
> - Package() {0x0018ffff, 3, LNKD, 0},
> -
> - // PCI Slot 26
> - Package() {0x001affff, 0, LNKB, 0},
> - Package() {0x001affff, 1, LNKC, 0},
> - Package() {0x001affff, 2, LNKD, 0},
> - Package() {0x001affff, 3, LNKA, 0},
> -
> - // PCI Slot 27
> - Package() {0x001bffff, 0, LNKC, 0},
> - Package() {0x001bffff, 1, LNKD, 0},
> - Package() {0x001bffff, 2, LNKA, 0},
> - Package() {0x001bffff, 3, LNKB, 0},
> -
> - // PCI Slot 28
> - Package() {0x001cffff, 0, LNKD, 0},
> - Package() {0x001cffff, 1, LNKA, 0},
> - Package() {0x001cffff, 2, LNKB, 0},
> - Package() {0x001cffff, 3, LNKC, 0},
> -
> - // PCI Slot 29
> - Package() {0x001dffff, 0, LNKA, 0},
> - Package() {0x001dffff, 1, LNKB, 0},
> - Package() {0x001dffff, 2, LNKC, 0},
> - Package() {0x001dffff, 3, LNKD, 0},
> -
> - // PCI Slot 30
> - Package() {0x001effff, 0, LNKB, 0},
> - Package() {0x001effff, 1, LNKC, 0},
> - Package() {0x001effff, 2, LNKD, 0},
> - Package() {0x001effff, 3, LNKA, 0},
> -
> - // PCI Slot 31
> - Package() {0x001fffff, 0, LNKC, 0},
> - Package() {0x001fffff, 1, LNKD, 0},
> - Package() {0x001fffff, 2, LNKA, 0},
> - Package() {0x001fffff, 3, LNKB, 0},
> - })
> +
> + Include ("acpi-irq-routing.dsl")
>
> OperationRegion(PCST, SystemIO, 0xae00, 0x08)
> Field (PCST, DWordAcc, NoLock, WriteAsZeros)
> - {
> + {
> PCIU, 32,
> PCID, 32,
> - }
> -
> + }
> OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
> Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
> {
> B0EJ, 32,
> }
>
> + Device (S0) { // Slot 0
> + Name (_ADR, 0x00000000)
> + Method (_EJ0,1) {
> + Store(0x1, B0EJ)
> + Return (0x0)
> + }
> + }
> +
> Device (S1) { // Slot 1
> Name (_ADR, 0x00010000)
> Method (_EJ0,1) {
> @@ -436,28 +247,70 @@ DefinitionBlock (
> }
> }
>
> - Device (S3) { // Slot 3
> + Device (S3) { // Slot 3, PCI-to-PCI bridge
> Name (_ADR, 0x00030000)
> - Method (_EJ0,1) {
> - Store (0x8, B0EJ)
> - Return (0x0)
> + Include ("acpi-irq-routing.dsl")
> +
> + OperationRegion(PCST, SystemIO, 0xae0c, 0x08)
> + Field (PCST, DWordAcc, NoLock, WriteAsZeros)
> + {
> + PCIU, 32,
> + PCID, 32,
> }
> +
> + OperationRegion(SEJ, SystemIO, 0xae14, 0x04)
> + Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
> + {
> + B1EJ, 32,
> + }
> +
> + Name (SUN1, 30)
> + Alias (\_SB.PCI0.S3.B1EJ, BEJ)
> + Include ("acpi-pci-slots.dsl")
> }
>
> - Device (S4) { // Slot 4
> + Device (S4) { // Slot 4, PCI-to-PCI bridge
> Name (_ADR, 0x00040000)
> - Method (_EJ0,1) {
> - Store(0x10, B0EJ)
> - Return (0x0)
> + Include ("acpi-irq-routing.dsl")
> +
> + OperationRegion(PCST, SystemIO, 0xae18, 0x08)
> + Field (PCST, DWordAcc, NoLock, WriteAsZeros)
> + {
> + PCIU, 32,
> + PCID, 32,
> + }
> +
> + OperationRegion(SEJ, SystemIO, 0xae20, 0x04)
> + Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
> + {
> + B2EJ, 32,
> }
> +
> + Name (SUN1, 62)
> + Alias (\_SB.PCI0.S4.B2EJ, BEJ)
> + Include ("acpi-pci-slots.dsl")
> }
>
> - Device (S5) { // Slot 5
> + Device (S5) { // Slot 5, PCI-to-PCI bridge
> Name (_ADR, 0x00050000)
> - Method (_EJ0,1) {
> - Store(0x20, B0EJ)
> - Return (0x0)
> + Include ("acpi-irq-routing.dsl")
> +
> + OperationRegion(PCST, SystemIO, 0xae24, 0x08)
> + Field (PCST, DWordAcc, NoLock, WriteAsZeros)
> + {
> + PCIU, 32,
> + PCID, 32,
> }
> +
> + OperationRegion(SEJ, SystemIO, 0xae2c, 0x04)
> + Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
> + {
> + B3EJ, 32,
> + }
> +
> + Name (SUN1, 94)
> + Alias (\_SB.PCI0.S5.B3EJ, BEJ)
> + Include ("acpi-pci-slots.dsl")
> }
>
> Device (S6) { // Slot 6
> @@ -1248,266 +1101,156 @@ DefinitionBlock (
> Return(0x01)
> }
> Method(_L01) {
> - /* Up status */
> - If (And(\_SB.PCI0.PCIU, 0x2)) {
> - Notify(\_SB.PCI0.S1, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x4)) {
> - Notify(\_SB.PCI0.S2, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x8)) {
> - Notify(\_SB.PCI0.S3, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x10)) {
> - Notify(\_SB.PCI0.S4, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x20)) {
> - Notify(\_SB.PCI0.S5, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x40)) {
> - Notify(\_SB.PCI0.S6, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x80)) {
> - Notify(\_SB.PCI0.S7, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x0100)) {
> - Notify(\_SB.PCI0.S8, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x0200)) {
> - Notify(\_SB.PCI0.S9, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x0400)) {
> - Notify(\_SB.PCI0.S10, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x0800)) {
> - Notify(\_SB.PCI0.S11, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x1000)) {
> - Notify(\_SB.PCI0.S12, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x2000)) {
> - Notify(\_SB.PCI0.S13, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x4000)) {
> - Notify(\_SB.PCI0.S14, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x8000)) {
> - Notify(\_SB.PCI0.S15, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x10000)) {
> - Notify(\_SB.PCI0.S16, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x20000)) {
> - Notify(\_SB.PCI0.S17, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x40000)) {
> - Notify(\_SB.PCI0.S18, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x80000)) {
> - Notify(\_SB.PCI0.S19, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x100000)) {
> - Notify(\_SB.PCI0.S20, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x200000)) {
> - Notify(\_SB.PCI0.S21, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x400000)) {
> - Notify(\_SB.PCI0.S22, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x800000)) {
> - Notify(\_SB.PCI0.S23, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x1000000)) {
> - Notify(\_SB.PCI0.S24, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x2000000)) {
> - Notify(\_SB.PCI0.S25, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x4000000)) {
> - Notify(\_SB.PCI0.S26, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x8000000)) {
> - Notify(\_SB.PCI0.S27, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x10000000)) {
> - Notify(\_SB.PCI0.S28, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x20000000)) {
> - Notify(\_SB.PCI0.S29, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x40000000)) {
> - Notify(\_SB.PCI0.S30, 0x1)
> - }
> -
> - If (And(\_SB.PCI0.PCIU, 0x80000000)) {
> - Notify(\_SB.PCI0.S31, 0x1)
> - }
> -
> - /* Down status */
> - If (And(\_SB.PCI0.PCID, 0x2)) {
> - Notify(\_SB.PCI0.S1, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x4)) {
> - Notify(\_SB.PCI0.S2, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x8)) {
> - Notify(\_SB.PCI0.S3, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x10)) {
> - Notify(\_SB.PCI0.S4, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x20)) {
> - Notify(\_SB.PCI0.S5, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x40)) {
> - Notify(\_SB.PCI0.S6, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x80)) {
> - Notify(\_SB.PCI0.S7, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x0100)) {
> - Notify(\_SB.PCI0.S8, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x0200)) {
> - Notify(\_SB.PCI0.S9, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x0400)) {
> - Notify(\_SB.PCI0.S10, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x0800)) {
> - Notify(\_SB.PCI0.S11, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x1000)) {
> - Notify(\_SB.PCI0.S12, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x2000)) {
> - Notify(\_SB.PCI0.S13, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x4000)) {
> - Notify(\_SB.PCI0.S14, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x8000)) {
> - Notify(\_SB.PCI0.S15, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x10000)) {
> - Notify(\_SB.PCI0.S16, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x20000)) {
> - Notify(\_SB.PCI0.S17, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x40000)) {
> - Notify(\_SB.PCI0.S18, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x80000)) {
> - Notify(\_SB.PCI0.S19, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x100000)) {
> - Notify(\_SB.PCI0.S20, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x200000)) {
> - Notify(\_SB.PCI0.S21, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x400000)) {
> - Notify(\_SB.PCI0.S22, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x800000)) {
> - Notify(\_SB.PCI0.S23, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x1000000)) {
> - Notify(\_SB.PCI0.S24, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x2000000)) {
> - Notify(\_SB.PCI0.S25, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x4000000)) {
> - Notify(\_SB.PCI0.S26, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x8000000)) {
> - Notify(\_SB.PCI0.S27, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x10000000)) {
> - Notify(\_SB.PCI0.S28, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x20000000)) {
> - Notify(\_SB.PCI0.S29, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x40000000)) {
> - Notify(\_SB.PCI0.S30, 0x3)
> - }
> -
> - If (And(\_SB.PCI0.PCID, 0x80000000)) {
> - Notify(\_SB.PCI0.S31, 0x3)
> - }
> -
> - Return(0x01)
> + Alias (\_SB.PCI0.PCIU, UP)
> + Alias (\_SB.PCI0.PCID, DOWN)
> + Alias (\_SB.PCI0.S0, S0)
> + Alias (\_SB.PCI0.S1, S1)
> + Alias (\_SB.PCI0.S2, S2)
> + Alias (\_SB.PCI0.S3, S3)
> + Alias (\_SB.PCI0.S4, S4)
> + Alias (\_SB.PCI0.S5, S5)
> + Alias (\_SB.PCI0.S6, S6)
> + Alias (\_SB.PCI0.S7, S7)
> + Alias (\_SB.PCI0.S8, S8)
> + Alias (\_SB.PCI0.S9, S9)
> + Alias (\_SB.PCI0.S10, S10)
> + Alias (\_SB.PCI0.S11, S11)
> + Alias (\_SB.PCI0.S12, S12)
> + Alias (\_SB.PCI0.S13, S13)
> + Alias (\_SB.PCI0.S14, S14)
> + Alias (\_SB.PCI0.S15, S15)
> + Alias (\_SB.PCI0.S16, S16)
> + Alias (\_SB.PCI0.S17, S17)
> + Alias (\_SB.PCI0.S18, S18)
> + Alias (\_SB.PCI0.S19, S19)
> + Alias (\_SB.PCI0.S20, S20)
> + Alias (\_SB.PCI0.S21, S21)
> + Alias (\_SB.PCI0.S22, S22)
> + Alias (\_SB.PCI0.S23, S23)
> + Alias (\_SB.PCI0.S24, S24)
> + Alias (\_SB.PCI0.S25, S25)
> + Alias (\_SB.PCI0.S26, S26)
> + Alias (\_SB.PCI0.S27, S27)
> + Alias (\_SB.PCI0.S28, S28)
> + Alias (\_SB.PCI0.S29, S29)
> + Alias (\_SB.PCI0.S30, S30)
> + Alias (\_SB.PCI0.S31, S31)
> + Include ("acpi-hotplug-gpe.dsl")
> + Return (0x01)
> }
> Method(_L02) {
> - Return(0x01)
> + Alias (\_SB.PCI0.S3.PCIU, UP)
> + Alias (\_SB.PCI0.S3.PCID, DOWN)
> + Alias (\_SB.PCI0.S3.S0, S0)
> + Alias (\_SB.PCI0.S3.S1, S1)
> + Alias (\_SB.PCI0.S3.S2, S2)
> + Alias (\_SB.PCI0.S3.S3, S3)
> + Alias (\_SB.PCI0.S3.S4, S4)
> + Alias (\_SB.PCI0.S3.S5, S5)
> + Alias (\_SB.PCI0.S3.S6, S6)
> + Alias (\_SB.PCI0.S3.S7, S7)
> + Alias (\_SB.PCI0.S3.S8, S8)
> + Alias (\_SB.PCI0.S3.S9, S9)
> + Alias (\_SB.PCI0.S3.S10, S10)
> + Alias (\_SB.PCI0.S3.S11, S11)
> + Alias (\_SB.PCI0.S3.S12, S12)
> + Alias (\_SB.PCI0.S3.S13, S13)
> + Alias (\_SB.PCI0.S3.S14, S14)
> + Alias (\_SB.PCI0.S3.S15, S15)
> + Alias (\_SB.PCI0.S3.S16, S16)
> + Alias (\_SB.PCI0.S3.S17, S17)
> + Alias (\_SB.PCI0.S3.S18, S18)
> + Alias (\_SB.PCI0.S3.S19, S19)
> + Alias (\_SB.PCI0.S3.S20, S20)
> + Alias (\_SB.PCI0.S3.S21, S21)
> + Alias (\_SB.PCI0.S3.S22, S22)
> + Alias (\_SB.PCI0.S3.S23, S23)
> + Alias (\_SB.PCI0.S3.S24, S24)
> + Alias (\_SB.PCI0.S3.S25, S25)
> + Alias (\_SB.PCI0.S3.S26, S26)
> + Alias (\_SB.PCI0.S3.S27, S27)
> + Alias (\_SB.PCI0.S3.S28, S28)
> + Alias (\_SB.PCI0.S3.S29, S29)
> + Alias (\_SB.PCI0.S3.S30, S30)
> + Alias (\_SB.PCI0.S3.S31, S31)
> + Include ("acpi-hotplug-gpe.dsl")
> + Return (0x01)
> }
> Method(_L03) {
> - Return(0x01)
> + Alias (\_SB.PCI0.S4.PCIU, UP)
> + Alias (\_SB.PCI0.S4.PCID, DOWN)
> + Alias (\_SB.PCI0.S4.S0, S0)
> + Alias (\_SB.PCI0.S4.S1, S1)
> + Alias (\_SB.PCI0.S4.S2, S2)
> + Alias (\_SB.PCI0.S4.S3, S3)
> + Alias (\_SB.PCI0.S4.S4, S4)
> + Alias (\_SB.PCI0.S4.S5, S5)
> + Alias (\_SB.PCI0.S4.S6, S6)
> + Alias (\_SB.PCI0.S4.S7, S7)
> + Alias (\_SB.PCI0.S4.S8, S8)
> + Alias (\_SB.PCI0.S4.S9, S9)
> + Alias (\_SB.PCI0.S4.S10, S10)
> + Alias (\_SB.PCI0.S4.S11, S11)
> + Alias (\_SB.PCI0.S4.S12, S12)
> + Alias (\_SB.PCI0.S4.S13, S13)
> + Alias (\_SB.PCI0.S4.S14, S14)
> + Alias (\_SB.PCI0.S4.S15, S15)
> + Alias (\_SB.PCI0.S4.S16, S16)
> + Alias (\_SB.PCI0.S4.S17, S17)
> + Alias (\_SB.PCI0.S4.S18, S18)
> + Alias (\_SB.PCI0.S4.S19, S19)
> + Alias (\_SB.PCI0.S4.S20, S20)
> + Alias (\_SB.PCI0.S4.S21, S21)
> + Alias (\_SB.PCI0.S4.S22, S22)
> + Alias (\_SB.PCI0.S4.S23, S23)
> + Alias (\_SB.PCI0.S4.S24, S24)
> + Alias (\_SB.PCI0.S4.S25, S25)
> + Alias (\_SB.PCI0.S4.S26, S26)
> + Alias (\_SB.PCI0.S4.S27, S27)
> + Alias (\_SB.PCI0.S4.S28, S28)
> + Alias (\_SB.PCI0.S4.S29, S29)
> + Alias (\_SB.PCI0.S4.S30, S30)
> + Alias (\_SB.PCI0.S4.S31, S31)
> + Include ("acpi-hotplug-gpe.dsl")
> + Return (0x01)
> }
> Method(_L04) {
> - Return(0x01)
> + Alias (\_SB.PCI0.S5.PCIU, UP)
> + Alias (\_SB.PCI0.S5.PCID, DOWN)
> + Alias (\_SB.PCI0.S5.S0, S0)
> + Alias (\_SB.PCI0.S5.S1, S1)
> + Alias (\_SB.PCI0.S5.S2, S2)
> + Alias (\_SB.PCI0.S5.S3, S3)
> + Alias (\_SB.PCI0.S5.S4, S4)
> + Alias (\_SB.PCI0.S5.S5, S5)
> + Alias (\_SB.PCI0.S5.S6, S6)
> + Alias (\_SB.PCI0.S5.S7, S7)
> + Alias (\_SB.PCI0.S5.S8, S8)
> + Alias (\_SB.PCI0.S5.S9, S9)
> + Alias (\_SB.PCI0.S5.S10, S10)
> + Alias (\_SB.PCI0.S5.S11, S11)
> + Alias (\_SB.PCI0.S5.S12, S12)
> + Alias (\_SB.PCI0.S5.S13, S13)
> + Alias (\_SB.PCI0.S5.S14, S14)
> + Alias (\_SB.PCI0.S5.S15, S15)
> + Alias (\_SB.PCI0.S5.S16, S16)
> + Alias (\_SB.PCI0.S5.S17, S17)
> + Alias (\_SB.PCI0.S5.S18, S18)
> + Alias (\_SB.PCI0.S5.S19, S19)
> + Alias (\_SB.PCI0.S5.S20, S20)
> + Alias (\_SB.PCI0.S5.S21, S21)
> + Alias (\_SB.PCI0.S5.S22, S22)
> + Alias (\_SB.PCI0.S5.S23, S23)
> + Alias (\_SB.PCI0.S5.S24, S24)
> + Alias (\_SB.PCI0.S5.S25, S25)
> + Alias (\_SB.PCI0.S5.S26, S26)
> + Alias (\_SB.PCI0.S5.S27, S27)
> + Alias (\_SB.PCI0.S5.S28, S28)
> + Alias (\_SB.PCI0.S5.S29, S29)
> + Alias (\_SB.PCI0.S5.S30, S30)
> + Alias (\_SB.PCI0.S5.S31, S31)
> + Include ("acpi-hotplug-gpe.dsl")
> + Return (0x01)
> }
> Method(_L05) {
> Return(0x01)
> Index: kvm-userspace.pci2/bios/acpi-hotplug-gpe.dsl
> ===================================================================
> --- /dev/null
> +++ kvm-userspace.pci2/bios/acpi-hotplug-gpe.dsl
> @@ -0,0 +1,257 @@
> + /* Up status */
> + If (And(UP, 0x1)) {
> + Notify(S0, 0x1)
> + }
> +
> + If (And(UP, 0x2)) {
> + Notify(S1, 0x1)
> + }
> +
> + If (And(UP, 0x4)) {
> + Notify(S2, 0x1)
> + }
> +
> + If (And(UP, 0x8)) {
> + Notify(S3, 0x1)
> + }
> +
> + If (And(UP, 0x10)) {
> + Notify(S4, 0x1)
> + }
> +
> + If (And(UP, 0x20)) {
> + Notify(S5, 0x1)
> + }
> +
> + If (And(UP, 0x40)) {
> + Notify(S6, 0x1)
> + }
> +
> + If (And(UP, 0x80)) {
> + Notify(S7, 0x1)
> + }
> +
> + If (And(UP, 0x0100)) {
> + Notify(S8, 0x1)
> + }
> +
> + If (And(UP, 0x0200)) {
> + Notify(S9, 0x1)
> + }
> +
> + If (And(UP, 0x0400)) {
> + Notify(S10, 0x1)
> + }
> +
> + If (And(UP, 0x0800)) {
> + Notify(S11, 0x1)
> + }
> +
> + If (And(UP, 0x1000)) {
> + Notify(S12, 0x1)
> + }
> +
> + If (And(UP, 0x2000)) {
> + Notify(S13, 0x1)
> + }
> +
> + If (And(UP, 0x4000)) {
> + Notify(S14, 0x1)
> + }
> +
> + If (And(UP, 0x8000)) {
> + Notify(S15, 0x1)
> + }
> +
> + If (And(UP, 0x10000)) {
> + Notify(S16, 0x1)
> + }
> +
> + If (And(UP, 0x20000)) {
> + Notify(S17, 0x1)
> + }
> +
> + If (And(UP, 0x40000)) {
> + Notify(S18, 0x1)
> + }
> +
> + If (And(UP, 0x80000)) {
> + Notify(S19, 0x1)
> + }
> +
> + If (And(UP, 0x100000)) {
> + Notify(S20, 0x1)
> + }
> +
> + If (And(UP, 0x200000)) {
> + Notify(S21, 0x1)
> + }
> +
> + If (And(UP, 0x400000)) {
> + Notify(S22, 0x1)
> + }
> +
> + If (And(UP, 0x800000)) {
> + Notify(S23, 0x1)
> + }
> +
> + If (And(UP, 0x1000000)) {
> + Notify(S24, 0x1)
> + }
> +
> + If (And(UP, 0x2000000)) {
> + Notify(S25, 0x1)
> + }
> +
> + If (And(UP, 0x4000000)) {
> + Notify(S26, 0x1)
> + }
> +
> + If (And(UP, 0x8000000)) {
> + Notify(S27, 0x1)
> + }
> +
> + If (And(UP, 0x10000000)) {
> + Notify(S28, 0x1)
> + }
> +
> + If (And(UP, 0x20000000)) {
> + Notify(S29, 0x1)
> + }
> +
> + If (And(UP, 0x40000000)) {
> + Notify(S30, 0x1)
> + }
> +
> + If (And(UP, 0x80000000)) {
> + Notify(S31, 0x1)
> + }
> +
> + /* Down status */
> + If (And(DOWN, 0x1)) {
> + Notify(S0, 0x3)
> + }
> +
> + If (And(DOWN, 0x2)) {
> + Notify(S1, 0x3)
> + }
> +
> + If (And(DOWN, 0x4)) {
> + Notify(S2, 0x3)
> + }
> +
> + If (And(DOWN, 0x8)) {
> + Notify(S3, 0x3)
> + }
> +
> + If (And(DOWN, 0x10)) {
> + Notify(S4, 0x3)
> + }
> +
> + If (And(DOWN, 0x20)) {
> + Notify(S5, 0x3)
> + }
> +
> + If (And(DOWN, 0x40)) {
> + Notify(S6, 0x3)
> + }
> +
> + If (And(DOWN, 0x80)) {
> + Notify(S7, 0x3)
> + }
> +
> + If (And(DOWN, 0x0100)) {
> + Notify(S8, 0x3)
> + }
> +
> + If (And(DOWN, 0x0200)) {
> + Notify(S9, 0x3)
> + }
> +
> + If (And(DOWN, 0x0400)) {
> + Notify(S10, 0x3)
> + }
> +
> + If (And(DOWN, 0x0800)) {
> + Notify(S11, 0x3)
> + }
> +
> + If (And(DOWN, 0x1000)) {
> + Notify(S12, 0x3)
> + }
> +
> + If (And(DOWN, 0x2000)) {
> + Notify(S13, 0x3)
> + }
> +
> + If (And(DOWN, 0x4000)) {
> + Notify(S14, 0x3)
> + }
> +
> + If (And(DOWN, 0x8000)) {
> + Notify(S15, 0x3)
> + }
> +
> + If (And(DOWN, 0x10000)) {
> + Notify(S16, 0x3)
> + }
> +
> + If (And(DOWN, 0x20000)) {
> + Notify(S17, 0x3)
> + }
> +
> + If (And(DOWN, 0x40000)) {
> + Notify(S18, 0x3)
> + }
> +
> + If (And(DOWN, 0x80000)) {
> + Notify(S19, 0x3)
> + }
> +
> + If (And(DOWN, 0x100000)) {
> + Notify(S20, 0x3)
> + }
> +
> + If (And(DOWN, 0x200000)) {
> + Notify(S21, 0x3)
> + }
> +
> + If (And(DOWN, 0x400000)) {
> + Notify(S22, 0x3)
> + }
> +
> + If (And(DOWN, 0x800000)) {
> + Notify(S23, 0x3)
> + }
> +
> + If (And(DOWN, 0x1000000)) {
> + Notify(S24, 0x3)
> + }
> +
> + If (And(DOWN, 0x2000000)) {
> + Notify(S25, 0x3)
> + }
> +
> + If (And(DOWN, 0x4000000)) {
> + Notify(S26, 0x3)
> + }
> +
> + If (And(DOWN, 0x8000000)) {
> + Notify(S27, 0x3)
> + }
> +
> + If (And(DOWN, 0x10000000)) {
> + Notify(S28, 0x3)
> + }
> +
> + If (And(DOWN, 0x20000000)) {
> + Notify(S29, 0x3)
> + }
> +
> + If (And(DOWN, 0x40000000)) {
> + Notify(S30, 0x3)
> + }
> +
> + If (And(DOWN, 0x80000000)) {
> + Notify(S31, 0x3)
> + }
> Index: kvm-userspace.pci2/bios/acpi-irq-routing.dsl
> ===================================================================
> --- /dev/null
> +++ kvm-userspace.pci2/bios/acpi-irq-routing.dsl
> @@ -0,0 +1,203 @@
> + External(LNKA, DeviceObj)
> + External(LNKB, DeviceObj)
> + External(LNKC, DeviceObj)
> + External(LNKD, DeviceObj)
> +
> + Name(_PRT, Package() {
> + /* PCI IRQ routing table, example from ACPI 2.0a
> specification,
> + section 6.2.8.1 */
> + /* Note: we provide the same info as the PCI routing
> + table of the Bochs BIOS */
> +
> + // PCI Slot 0
> + Package() {0x0000ffff, 0, LNKD, 0},
> + Package() {0x0000ffff, 1, LNKA, 0},
> + Package() {0x0000ffff, 2, LNKB, 0},
> + Package() {0x0000ffff, 3, LNKC, 0},
> +
> + // PCI Slot 1
> + Package() {0x0001ffff, 0, LNKA, 0},
> + Package() {0x0001ffff, 1, LNKB, 0},
> + Package() {0x0001ffff, 2, LNKC, 0},
> + Package() {0x0001ffff, 3, LNKD, 0},
> +
> + // PCI Slot 2
> + Package() {0x0002ffff, 0, LNKB, 0},
> + Package() {0x0002ffff, 1, LNKC, 0},
> + Package() {0x0002ffff, 2, LNKD, 0},
> + Package() {0x0002ffff, 3, LNKA, 0},
> +
> + // PCI Slot 3
> + Package() {0x0003ffff, 0, LNKC, 0},
> + Package() {0x0003ffff, 1, LNKD, 0},
> + Package() {0x0003ffff, 2, LNKA, 0},
> + Package() {0x0003ffff, 3, LNKB, 0},
> +
> + // PCI Slot 4
> + Package() {0x0004ffff, 0, LNKD, 0},
> + Package() {0x0004ffff, 1, LNKA, 0},
> + Package() {0x0004ffff, 2, LNKB, 0},
> + Package() {0x0004ffff, 3, LNKC, 0},
> +
> + // PCI Slot 5
> + Package() {0x0005ffff, 0, LNKA, 0},
> + Package() {0x0005ffff, 1, LNKB, 0},
> + Package() {0x0005ffff, 2, LNKC, 0},
> + Package() {0x0005ffff, 3, LNKD, 0},
> +
> + // PCI Slot 6
> + Package() {0x0006ffff, 0, LNKB, 0},
> + Package() {0x0006ffff, 1, LNKC, 0},
> + Package() {0x0006ffff, 2, LNKD, 0},
> + Package() {0x0006ffff, 3, LNKA, 0},
> +
> + // PCI Slot 7
> + Package() {0x0007ffff, 0, LNKC, 0},
> + Package() {0x0007ffff, 1, LNKD, 0},
> + Package() {0x0007ffff, 2, LNKA, 0},
> + Package() {0x0007ffff, 3, LNKB, 0},
> +
> + // PCI Slot 8
> + Package() {0x0008ffff, 0, LNKD, 0},
> + Package() {0x0008ffff, 1, LNKA, 0},
> + Package() {0x0008ffff, 2, LNKB, 0},
> + Package() {0x0008ffff, 3, LNKC, 0},
> +
> + // PCI Slot 9
> + Package() {0x0009ffff, 0, LNKA, 0},
> + Package() {0x0009ffff, 1, LNKB, 0},
> + Package() {0x0009ffff, 2, LNKC, 0},
> + Package() {0x0009ffff, 3, LNKD, 0},
> +
> + // PCI Slot 10
> + Package() {0x000affff, 0, LNKB, 0},
> + Package() {0x000affff, 1, LNKC, 0},
> + Package() {0x000affff, 2, LNKD, 0},
> + Package() {0x000affff, 3, LNKA, 0},
> +
> + // PCI Slot 11
> + Package() {0x000bffff, 0, LNKC, 0},
> + Package() {0x000bffff, 1, LNKD, 0},
> + Package() {0x000bffff, 2, LNKA, 0},
> + Package() {0x000bffff, 3, LNKB, 0},
> +
> + // PCI Slot 12
> + Package() {0x000cffff, 0, LNKD, 0},
> + Package() {0x000cffff, 1, LNKA, 0},
> + Package() {0x000cffff, 2, LNKB, 0},
> + Package() {0x000cffff, 3, LNKC, 0},
> +
> + // PCI Slot 13
> + Package() {0x000dffff, 0, LNKA, 0},
> + Package() {0x000dffff, 1, LNKB, 0},
> + Package() {0x000dffff, 2, LNKC, 0},
> + Package() {0x000dffff, 3, LNKD, 0},
> +
> + // PCI Slot 14
> + Package() {0x000effff, 0, LNKB, 0},
> + Package() {0x000effff, 1, LNKC, 0},
> + Package() {0x000effff, 2, LNKD, 0},
> + Package() {0x000effff, 3, LNKA, 0},
> +
> + // PCI Slot 15
> + Package() {0x000fffff, 0, LNKC, 0},
> + Package() {0x000fffff, 1, LNKD, 0},
> + Package() {0x000fffff, 2, LNKA, 0},
> + Package() {0x000fffff, 3, LNKB, 0},
> +
> + // PCI Slot 16
> + Package() {0x0010ffff, 0, LNKD, 0},
> + Package() {0x0010ffff, 1, LNKA, 0},
> + Package() {0x0010ffff, 2, LNKB, 0},
> + Package() {0x0010ffff, 3, LNKC, 0},
> +
> + // PCI Slot 17
> + Package() {0x0011ffff, 0, LNKA, 0},
> + Package() {0x0011ffff, 1, LNKB, 0},
> + Package() {0x0011ffff, 2, LNKC, 0},
> + Package() {0x0011ffff, 3, LNKD, 0},
> +
> + // PCI Slot 18
> + Package() {0x0012ffff, 0, LNKB, 0},
> + Package() {0x0012ffff, 1, LNKC, 0},
> + Package() {0x0012ffff, 2, LNKD, 0},
> + Package() {0x0012ffff, 3, LNKA, 0},
> +
> + // PCI Slot 19
> + Package() {0x0013ffff, 0, LNKC, 0},
> + Package() {0x0013ffff, 1, LNKD, 0},
> + Package() {0x0013ffff, 2, LNKA, 0},
> + Package() {0x0013ffff, 3, LNKB, 0},
> +
> + // PCI Slot 20
> + Package() {0x0014ffff, 0, LNKD, 0},
> + Package() {0x0014ffff, 1, LNKA, 0},
> + Package() {0x0014ffff, 2, LNKB, 0},
> + Package() {0x0014ffff, 3, LNKC, 0},
> +
> + // PCI Slot 21
> + Package() {0x0015ffff, 0, LNKA, 0},
> + Package() {0x0015ffff, 1, LNKB, 0},
> + Package() {0x0015ffff, 2, LNKC, 0},
> + Package() {0x0015ffff, 3, LNKD, 0},
> +
> + // PCI Slot 22
> + Package() {0x0016ffff, 0, LNKB, 0},
> + Package() {0x0016ffff, 1, LNKC, 0},
> + Package() {0x0016ffff, 2, LNKD, 0},
> + Package() {0x0016ffff, 3, LNKA, 0},
> +
> + // PCI Slot 23
> + Package() {0x0017ffff, 0, LNKC, 0},
> + Package() {0x0017ffff, 1, LNKD, 0},
> + Package() {0x0017ffff, 2, LNKA, 0},
> + Package() {0x0017ffff, 3, LNKB, 0},
> +
> + // PCI Slot 24
> + Package() {0x0018ffff, 0, LNKD, 0},
> + Package() {0x0018ffff, 1, LNKA, 0},
> + Package() {0x0018ffff, 2, LNKB, 0},
> + Package() {0x0018ffff, 3, LNKC, 0},
> +
> + // PCI Slot 25
> + Package() {0x0019ffff, 0, LNKA, 0},
> + Package() {0x0019ffff, 1, LNKB, 0},
> + Package() {0x0019ffff, 2, LNKC, 0},
> + Package() {0x0019ffff, 3, LNKD, 0},
> +
> + // PCI Slot 26
> + Package() {0x001affff, 0, LNKB, 0},
> + Package() {0x001affff, 1, LNKC, 0},
> + Package() {0x001affff, 2, LNKD, 0},
> + Package() {0x001affff, 3, LNKA, 0},
> +
> + // PCI Slot 27
> + Package() {0x001bffff, 0, LNKC, 0},
> + Package() {0x001bffff, 1, LNKD, 0},
> + Package() {0x001bffff, 2, LNKA, 0},
> + Package() {0x001bffff, 3, LNKB, 0},
> +
> + // PCI Slot 28
> + Package() {0x001cffff, 0, LNKD, 0},
> + Package() {0x001cffff, 1, LNKA, 0},
> + Package() {0x001cffff, 2, LNKB, 0},
> + Package() {0x001cffff, 3, LNKC, 0},
> +
> + // PCI Slot 29
> + Package() {0x001dffff, 0, LNKA, 0},
> + Package() {0x001dffff, 1, LNKB, 0},
> + Package() {0x001dffff, 2, LNKC, 0},
> + Package() {0x001dffff, 3, LNKD, 0},
> +
> + // PCI Slot 30
> + Package() {0x001effff, 0, LNKB, 0},
> + Package() {0x001effff, 1, LNKC, 0},
> + Package() {0x001effff, 2, LNKD, 0},
> + Package() {0x001effff, 3, LNKA, 0},
> +
> + // PCI Slot 31
> + Package() {0x001fffff, 0, LNKC, 0},
> + Package() {0x001fffff, 1, LNKD, 0},
> + Package() {0x001fffff, 2, LNKA, 0},
> + Package() {0x001fffff, 3, LNKB, 0},
> + })
> Index: kvm-userspace.pci2/bios/acpi-pci-slots.dsl
> ===================================================================
> --- /dev/null
> +++ kvm-userspace.pci2/bios/acpi-pci-slots.dsl
> @@ -0,0 +1,385 @@
> + Device (S0) { // Slot 0
> + Name (_ADR, 0x00000000)
> + Method (_EJ0,1) {
> + Store(0x1, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 0, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S1) { // Slot 1
> + Name (_ADR, 0x00010000)
> + Method (_EJ0,1) {
> + Store(0x2, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 1, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S2) { // Slot 2
> + Name (_ADR, 0x00020000)
> + Method (_EJ0,1) {
> + Store(0x4, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 2, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S3) { // Slot 3
> + Name (_ADR, 0x00030000)
> + Method (_EJ0,1) {
> + Store(0x4, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 3, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S4) { // Slot 4
> + Name (_ADR, 0x00040000)
> + Method (_EJ0,1) {
> + Store(0x4, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 4, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S5) { // Slot 5
> + Name (_ADR, 0x00050000)
> + Method (_EJ0,1) {
> + Store(0x4, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 5, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S6) { // Slot 6
> + Name (_ADR, 0x00060000)
> + Method (_EJ0,1) {
> + Store(0x40, BEJ)
> + Return (0x0)
> + }
> +
> + Method(_SUN) {
> + Add (SUN1, 6, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S7) { // Slot 7
> + Name (_ADR, 0x00070000)
> + Method (_EJ0,1) {
> + Store(0x80, BEJ)
> + Return (0x0)
> + }
> +
> + Method(_SUN) {
> + Add (SUN1, 7, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S8) { // Slot 8
> + Name (_ADR, 0x00080000)
> + Method (_EJ0,1) {
> + Store(0x100, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 8, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S9) { // Slot 9
> + Name (_ADR, 0x00090000)
> + Method (_EJ0,1) {
> + Store(0x200, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 9, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S10) { // Slot 10
> + Name (_ADR, 0x000A0000)
> + Method (_EJ0,1) {
> + Store(0x400, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 10, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S11) { // Slot 11
> + Name (_ADR, 0x000B0000)
> + Method (_EJ0,1) {
> + Store(0x800, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 11, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S12) { // Slot 12
> + Name (_ADR, 0x000C0000)
> + Method (_EJ0,1) {
> + Store(0x1000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 12, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S13) { // Slot 13
> + Name (_ADR, 0x000D0000)
> + Method (_EJ0,1) {
> + Store(0x2000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 13, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S14) { // Slot 14
> + Name (_ADR, 0x000E0000)
> + Method (_EJ0,1) {
> + Store(0x4000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 14, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S15) { // Slot 15
> + Name (_ADR, 0x000F0000)
> + Method (_EJ0,1) {
> + Store(0x8000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 15, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S16) { // Slot 16
> + Name (_ADR, 0x00100000)
> + Method (_EJ0,1) {
> + Store(0x10000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 16, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S17) { // Slot 17
> + Name (_ADR, 0x00110000)
> + Method (_EJ0,1) {
> + Store(0x20000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 17, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S18) { // Slot 18
> + Name (_ADR, 0x00120000)
> + Method (_EJ0,1) {
> + Store(0x40000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 18, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S19) { // Slot 19
> + Name (_ADR, 0x00130000)
> + Method (_EJ0,1) {
> + Store(0x80000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 19, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S20) { // Slot 20
> + Name (_ADR, 0x00140000)
> + Method (_EJ0,1) {
> + Store(0x100000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 20, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S21) { // Slot 21
> + Name (_ADR, 0x00150000)
> + Method (_EJ0,1) {
> + Store(0x200000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 21, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S22) { // Slot 22
> + Name (_ADR, 0x00160000)
> + Method (_EJ0,1) {
> + Store(0x400000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 22, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S23) { // Slot 23
> + Name (_ADR, 0x00170000)
> + Method (_EJ0,1) {
> + Store(0x800000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 23, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S24) { // Slot 24
> + Name (_ADR, 0x00180000)
> + Method (_EJ0,1) {
> + Store(0x1000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 24, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S25) { // Slot 25
> + Name (_ADR, 0x00190000)
> + Method (_EJ0,1) {
> + Store(0x2000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 25, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S26) { // Slot 26
> + Name (_ADR, 0x001A0000)
> + Method (_EJ0,1) {
> + Store(0x4000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 26, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S27) { // Slot 27
> + Name (_ADR, 0x001B0000)
> + Method (_EJ0,1) {
> + Store(0x8000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 27, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S28) { // Slot 28
> + Name (_ADR, 0x001C0000)
> + Method (_EJ0,1) {
> + Store(0x10000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 28, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S29) { // Slot 29
> + Name (_ADR, 0x001D0000)
> + Method (_EJ0,1) {
> + Store(0x20000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 29, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S30) { // Slot 30
> + Name (_ADR, 0x001E0000)
> + Method (_EJ0,1) {
> + Store(0x40000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 30, Local0)
> + Return (Local0)
> + }
> + }
> +
> + Device (S31) { // Slot 31
> + Name (_ADR, 0x001F0000)
> + Method (_EJ0,1) {
> + Store(0x80000000, BEJ)
> + Return (0x0)
> + }
> + Method(_SUN) {
> + Add (SUN1, 31, Local0)
> + Return (Local0)
> + }
> + }
> Index: kvm-userspace.pci2/bios/rombios32.c
> ===================================================================
> --- kvm-userspace.pci2.orig/bios/rombios32.c
> +++ kvm-userspace.pci2/bios/rombios32.c
> @@ -652,6 +652,30 @@ static void bios_lock_shadow_ram(void)
> pci_config_writeb(d, 0x59, v);
> }
>
> +static int nr_bridges = 1;
> +static int current_bridge = 0;
> +
> +static void pci_bios_count_p2p(PCIDevice *d)
> +{
> + uint16_t vendor_id, device_id;
> +
> + vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
> + device_id = pci_config_readw(d, PCI_DEVICE_ID);
> + if (vendor_id == 0x8086 && device_id == 0x244e)
> + nr_bridges++;
> +}
> +
> +int fls(int i)
> +{
> + int bit;
> +
> + for (bit=31; bit >= 0; bit--)
> + if (i & (1 << bit))
> + return bit+1;
> +
> + return 0;
> +}
> +
> static void pci_bios_init_bridges(PCIDevice *d)
> {
> uint16_t vendor_id, device_id;
> @@ -681,6 +705,27 @@ static void pci_bios_init_bridges(PCIDev
> } else if (vendor_id == 0x8086 && device_id == 0x1237) {
> /* i440 PCI bridge */
> bios_shadow_init(d);
> + } else if (vendor_id == 0x8086 && device_id == 0x244e) {
> + int len, base;
> +
> + len = (0xfebfffff - 0xf0000000) / nr_bridges;
> + if (len & (len-1))
> + len = 1 << fls(len);
> +
> + /* memory IO */
> + base = (0xf0000000+len) + (current_bridge*len);
> + base >>= 16;
> + pci_config_writew(d, 0x20, base);
> + pci_config_writew(d, 0x22, base);
> +
> + /* port IO */
> + len = 0x1000;
> + base = 0x2000 + (current_bridge*len);
> + base >>= 8;
> + pci_config_writeb(d, 0x1c, base);
> + pci_config_writeb(d, 0x1d, base);
> +
> + current_bridge++;
> }
> }
>
> @@ -775,6 +820,8 @@ static void pci_bios_init_device(PCIDevi
> pci_set_io_region_addr(d, 0, 0x80800000);
> }
> break;
> + case 0x0604:
> + break;
> default:
> default_map:
> /* default memory mappings */
> @@ -859,6 +906,8 @@ void pci_bios_init(void)
> if (pci_bios_bigmem_addr < 0x90000000)
> pci_bios_bigmem_addr = 0x90000000;
>
> + pci_for_each_device(pci_bios_count_p2p);
> +
> pci_for_each_device(pci_bios_init_bridges);
>
> pci_for_each_device(pci_bios_init_device);
> Index: kvm-userspace.pci2/qemu/hw/acpi.c
> ===================================================================
> --- kvm-userspace.pci2.orig/qemu/hw/acpi.c
> +++ kvm-userspace.pci2/qemu/hw/acpi.c
> @@ -557,10 +557,11 @@ struct gpe_regs {
> struct pci_status {
> uint32_t up;
> uint32_t down;
> + unsigned long base;
> };
>
> static struct gpe_regs gpe;
> -static struct pci_status pci0_status;
> +static struct pci_status pci_bus_status[4];
>
> static uint32_t gpe_readb(void *opaque, uint32_t addr)
> {
> @@ -630,16 +631,19 @@ static void gpe_writeb(void *opaque, uin
>
> static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
> {
> - uint32_t val = 0;
> struct pci_status *g = opaque;
> - switch (addr) {
> - case PCI_BASE:
> + uint32_t val, offset;
> +
> + offset = addr - g->base;
> + switch (offset) {
> + case 0:
> val = g->up;
> break;
> - case PCI_BASE + 4:
> + case 4:
> val = g->down;
> break;
> default:
> + val = 0;
> break;
> }
>
> @@ -652,11 +656,13 @@ static uint32_t pcihotplug_read(voi...
[truncated message content] |
