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[kvm-ia64-devel] [PATCH][14]add processor virtulization support.
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From: Zhang, X. <xia...@in...> - 2008-01-31 10:34:10
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From: Zhang Xiantao <xia...@in...>
Date: Tue, 29 Jan 2008 14:34:03 +0800
Subject: [PATCH] kvm/ia64: add processor virtulization support.
vcpu.c provides processor virtualization logic.
Signed-off-by: Anthony Xu <ant...@in...>
Signed-off-by: Xiantao Zhang <xia...@in...>
---
arch/ia64/kvm/vcpu.c | 2158
++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 2158 insertions(+), 0 deletions(-)
create mode 100644 arch/ia64/kvm/vcpu.c
diff --git a/arch/ia64/kvm/vcpu.c b/arch/ia64/kvm/vcpu.c
new file mode 100644
index 0000000..91a6f94
--- /dev/null
+++ b/arch/ia64/kvm/vcpu.c
@@ -0,0 +1,2158 @@
+/*
+ * kvm_vcpu.c: handling all virtual cpu related thing.
+ * Copyright (c) 2005, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but
WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Shaofan Li (Susue Li) <sus...@in...>
+ * Yaozu Dong (Eddie Dong) (Edd...@in...)
+ * Xuefei Xu (Anthony Xu) (Ant...@in...)
+ * Xiantao Zhang <xia...@in...>
+ */
+
+#include <linux/kvm_host.h>
+
+#include <asm/types.h>
+#include <asm/processor.h>
+#include <asm/ia64regs.h>
+#include <asm/gcc_intrin.h>
+#include <asm/kregs.h>
+#include <asm/pgtable.h>
+
+
+#include "asm-offsets.h"
+#include "vcpu.h"
+
+/*
+ * Special notes:
+ * - Index by it/dt/rt sequence
+ * - Only existing mode transitions are allowed in this table
+ * - RSE is placed at lazy mode when emulating guest partial mode
+ * - If gva happens to be rr0 and rr4, only allowed case is identity
+ * mapping (gva=3Dgpa), or panic! (How?)
+ */
+int mm_switch_table[8][8] =3D {
+ /* 2004/09/12(Kevin): Allow switch to self */
+ /*
+ * (it,dt,rt): (0,0,0) -> (1,1,1)
+ * This kind of transition usually occurs in the very early
+ * stage of Linux boot up procedure. Another case is in efi
+ * and pal calls. (see "arch/ia64/kernel/head.S")
+ *
+ * (it,dt,rt): (0,0,0) -> (0,1,1)
+ * This kind of transition is found when OSYa exits efi boot
+ * service. Due to gva =3D gpa in this case (Same region),
+ * data access can be satisfied though itlb entry for physical
+ * emulation is hit.
+ */
+ {SW_SELF, 0, 0, SW_NOP, 0, 0, 0, SW_P2V},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ /*
+ * (it,dt,rt): (0,1,1) -> (1,1,1)
+ * This kind of transition is found in OSYa.
+ *
+ * (it,dt,rt): (0,1,1) -> (0,0,0)
+ * This kind of transition is found in OSYa
+ */
+ {SW_NOP, 0, 0, SW_SELF, 0, 0, 0, SW_P2V},
+ /* (1,0,0)->(1,1,1) */
+ {0, 0, 0, 0, 0, 0, 0, SW_P2V},
+ /*
+ * (it,dt,rt): (1,0,1) -> (1,1,1)
+ * This kind of transition usually occurs when Linux returns
+ * from the low level TLB miss handlers.
+ * (see "arch/ia64/kernel/ivt.S")
+ */
+ {0, 0, 0, 0, 0, SW_SELF, 0, SW_P2V},
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ /*
+ * (it,dt,rt): (1,1,1) -> (1,0,1)
+ * This kind of transition usually occurs in Linux low level
+ * TLB miss handler. (see "arch/ia64/kernel/ivt.S")
+ *
+ * (it,dt,rt): (1,1,1) -> (0,0,0)
+ * This kind of transition usually occurs in pal and efi calls,
+ * which requires running in physical mode.
+ * (see "arch/ia64/kernel/head.S")
+ * (1,1,1)->(1,0,0)
+ */
+
+ {SW_V2P, 0, 0, 0, SW_V2P, SW_V2P, 0, SW_SELF},
+};
+
+void physical_mode_init(VCPU *vcpu)
+{
+ vcpu->arch.mode_flags =3D GUEST_IN_PHY;
+}
+
+extern void kvm_switch_rr6(unsigned long, void *, void *, void *);
+
+
+void switch_to_physical_rid(VCPU *vcpu)
+{
+ unsigned long psr;
+
+ /* Save original virtual mode rr[0] and rr[4] */
+ psr =3D ia64_clear_ic();
+ ia64_set_rr(VRN0<<VRN_SHIFT, vcpu->arch.metaphysical_rr0);
+ ia64_srlz_d();
+ ia64_set_rr(VRN4<<VRN_SHIFT, vcpu->arch.metaphysical_rr4);
+ ia64_srlz_d();
+
+ ia64_set_psr(psr);
+ ia64_srlz_i();
+ return;
+}
+
+
+void switch_to_virtual_rid(VCPU *vcpu)
+{
+ unsigned long psr;
+
+ psr =3D ia64_clear_ic();
+ ia64_set_rr(VRN0 << VRN_SHIFT,
vcpu->arch.metaphysical_saved_rr0);
+ ia64_srlz_d();
+ ia64_set_rr(VRN4 << VRN_SHIFT,
vcpu->arch.metaphysical_saved_rr4);
+ ia64_srlz_d();
+ ia64_set_psr(psr);
+ ia64_srlz_i();
+ return;
+}
+
+static int mm_switch_action(ia64_psr opsr, ia64_psr npsr)
+{
+ return mm_switch_table[MODE_IND(opsr)][MODE_IND(npsr)];
+}
+
+void switch_mm_mode(VCPU *vcpu, ia64_psr old_psr, ia64_psr new_psr)
+{
+ int act;
+ act =3D mm_switch_action(old_psr, new_psr);
+ switch (act) {
+ case SW_V2P:
+ /*printk("V -> P mode transition: (0x%lx -> 0x%lx)\n",
+ old_psr.val, new_psr.val);*/
+ switch_to_physical_rid(vcpu);
+ /*
+ * Set rse to enforced lazy, to prevent active rse
+ *save/restor when guest physical mode.
+ */
+ vcpu->arch.mode_flags |=3D GUEST_IN_PHY;
+ break;
+ case SW_P2V:
+ switch_to_virtual_rid(vcpu);
+ /*
+ * recover old mode which is saved when entering
+ * guest physical mode
+ */
+ vcpu->arch.mode_flags &=3D ~GUEST_IN_PHY;
+ break;
+ case SW_SELF:
+ break;
+ case SW_NOP:
+ break;
+ default:
+ /* Sanity check */
+ break;
+ }
+ return;
+}
+
+
+
+/*
+ * In physical mode, insert tc/tr for region 0 and 4 uses
+ * RID[0] and RID[4] which is for physical mode emulation.
+ * However what those inserted tc/tr wants is rid for
+ * virtual mode. So original virtual rid needs to be restored
+ * before insert.
+ *
+ * Operations which required such switch include:
+ * - insertions (itc.*, itr.*)
+ * - purges (ptc.* and ptr.*)
+ * - tpa
+ * - tak
+ * - thash?, ttag?
+ * All above needs actual virtual rid for destination entry.
+ */
+
+void check_mm_mode_switch(VCPU *vcpu, ia64_psr old_psr, ia64_psr
new_psr)
+{
+
+ if ((old_psr.dt !=3D new_psr.dt)
+ || (old_psr.it !=3D new_psr.it)
+ || (old_psr.rt !=3D new_psr.rt))
+ switch_mm_mode(vcpu, old_psr, new_psr);
+
+ return;
+}
+
+
+/*
+ * In physical mode, insert tc/tr for region 0 and 4 uses
+ * RID[0] and RID[4] which is for physical mode emulation.
+ * However what those inserted tc/tr wants is rid for
+ * virtual mode. So original virtual rid needs to be restored
+ * before insert.
+ *
+ * Operations which required such switch include:
+ * - insertions (itc.*, itr.*)
+ * - purges (ptc.* and ptr.*)
+ * - tpa
+ * - tak
+ * - thash?, ttag?
+ * All above needs actual virtual rid for destination entry.
+ */
+
+void prepare_if_physical_mode(VCPU *vcpu)
+{
+ if (is_physical_mode(vcpu)) {
+ vcpu->arch.mode_flags |=3D GUEST_PHY_EMUL;
+ switch_to_virtual_rid(vcpu);
+ }
+ return;
+}
+
+/* Recover always follows prepare */
+void recover_if_physical_mode(VCPU *vcpu)
+{
+ if (is_physical_mode(vcpu))
+ switch_to_physical_rid(vcpu);
+ vcpu->arch.mode_flags &=3D ~GUEST_PHY_EMUL;
+ return;
+}
+
+#define RPT(x) ((u16) &((struct kvm_pt_regs *)0)->x)
+
+static u16 gr_info[32] =3D {
+ 0, /* r0 is read-only : WE SHOULD NEVER GET THIS */
+ RPT(r1), RPT(r2), RPT(r3),
+ RPT(r4), RPT(r5), RPT(r6), RPT(r7),
+ RPT(r8), RPT(r9), RPT(r10), RPT(r11),
+ RPT(r12), RPT(r13), RPT(r14), RPT(r15),
+ RPT(r16), RPT(r17), RPT(r18), RPT(r19),
+ RPT(r20), RPT(r21), RPT(r22), RPT(r23),
+ RPT(r24), RPT(r25), RPT(r26), RPT(r27),
+ RPT(r28), RPT(r29), RPT(r30), RPT(r31)
+};
+
+/*
+ * Return the (rotated) index for floating point register
+ * be in the REGNUM (REGNUM must range from 32-127,
+ * result is in the range from 0-95.
+ */
+static inline unsigned long fph_index(struct kvm_pt_regs *regs,
+ long regnum)
+{
+ unsigned long rrb_fr =3D (regs->cr_ifs >> 25) & 0x7f;
+ return rotate_reg(96, rrb_fr, (regnum -
IA64_FIRST_ROTATING_FR));
+}
+
+
+/*
+ * The inverse of the above: given bspstore and the number of
+ * registers, calculate ar.bsp.
+ */
+static inline unsigned long *kvm_rse_skip_regs(unsigned long *addr,
+ long num_regs)
+{
+ long delta =3D ia64_rse_slot_num(addr) + num_regs;
+ int i =3D 0;
+
+ if (num_regs < 0)
+ delta -=3D 0x3e;
+ if (delta < 0) {
+ while (delta <=3D -0x3f) {
+ i--;
+ delta +=3D 0x3f;
+ }
+ } else {
+ while (delta >=3D 0x3f) {
+ i++;
+ delta -=3D 0x3f;
+ }
+ }
+
+ return addr + num_regs + i;
+}
+
+static void get_rse_reg (struct kvm_pt_regs *regs, unsigned long r1,
+ unsigned long *val, int *nat)
+{
+ unsigned long *bsp, *addr, *rnat_addr, *bspstore;
+ unsigned long *kbs =3D (void *) current_vcpu + VMM_RBS_OFFSET;
+ unsigned long nat_mask;
+ unsigned long old_rsc, new_rsc;
+ long sof =3D (regs->cr_ifs) & 0x7f;
+ long sor =3D (((regs->cr_ifs >> 14) & 0xf) << 3);
+ long rrb_gr =3D (regs->cr_ifs >> 18) & 0x7f;
+ long ridx =3D r1 - 32;
+
+ if (ridx < sor)
+ ridx =3D rotate_reg(sor, rrb_gr, ridx);
+
+ old_rsc =3D ia64_get_rsc();
+ new_rsc =3D old_rsc&(~(0x3));
+ ia64_set_rsc(new_rsc);
+
+ bspstore =3D (unsigned long *)ia64_get_bspstore();
+ bsp =3D kbs + (regs->loadrs >> 19);
+
+ addr =3D kvm_rse_skip_regs(bsp, -sof + ridx);
+ nat_mask =3D 1UL << ia64_rse_slot_num(addr);
+ rnat_addr =3D ia64_rse_rnat_addr(addr);
+
+ if (addr >=3D bspstore) {
+ ia64_flushrs();
+ ia64_mf();
+ bspstore =3D (unsigned long *)ia64_get_bspstore();
+ }
+ *val =3D *addr;
+ if (nat) {
+ if (bspstore < rnat_addr) {
+ *nat =3D (int)!!(ia64_get_rnat() & nat_mask);
+ } else {
+ *nat =3D (int)!!((*rnat_addr) & nat_mask);
+ }
+ ia64_set_rsc(old_rsc);
+ }
+}
+
+void set_rse_reg(struct kvm_pt_regs *regs, unsigned long r1,
+ unsigned long val, unsigned long nat)
+{
+ unsigned long *bsp, *bspstore, *addr, *rnat_addr;
+ unsigned long *kbs =3D (void *) current_vcpu + VMM_RBS_OFFSET;
+ unsigned long nat_mask;
+ unsigned long old_rsc, new_rsc, psr;
+ unsigned long rnat;
+ long sof =3D (regs->cr_ifs) & 0x7f;
+ long sor =3D (((regs->cr_ifs >> 14) & 0xf) << 3);
+ long rrb_gr =3D (regs->cr_ifs >> 18) & 0x7f;
+ long ridx =3D r1 - 32;
+
+ if (ridx < sor)
+ ridx =3D rotate_reg(sor, rrb_gr, ridx);
+
+ old_rsc =3D ia64_get_rsc();
+ /* put RSC to lazy mode, and set loadrs 0 */
+ new_rsc =3D old_rsc & (~0x3fff0003);
+ ia64_set_rsc(new_rsc);
+ bsp =3D kbs + (regs->loadrs >> 19); /* 16 + 3 */
+
+ addr =3D kvm_rse_skip_regs(bsp, -sof + ridx);
+ nat_mask =3D 1UL << ia64_rse_slot_num(addr);
+ rnat_addr =3D ia64_rse_rnat_addr(addr);
+
+ local_irq_save(psr);
+ bspstore =3D (unsigned long *)ia64_get_bspstore();
+ if (addr >=3D bspstore) {
+
+ ia64_flushrs();
+ ia64_mf();
+ *addr =3D val;
+ bspstore =3D (unsigned long *)ia64_get_bspstore();
+ rnat =3D ia64_get_rnat();
+ if (bspstore < rnat_addr) {
+ rnat =3D rnat & (~nat_mask);
+ } else{
+ *rnat_addr =3D (*rnat_addr)&(~nat_mask);
+ }
+ ia64_mf();
+ ia64_loadrs();
+ ia64_set_rnat(rnat);
+ } else {
+ rnat =3D ia64_get_rnat();
+ *addr =3D val;
+ if (bspstore < rnat_addr) {
+ rnat =3D rnat&(~nat_mask);
+ } else {
+ *rnat_addr =3D (*rnat_addr) & (~nat_mask);
+ }
+ ia64_set_bspstore(bspstore);
+ ia64_set_rnat(rnat);
+ }
+ local_irq_restore(psr);
+ ia64_set_rsc(old_rsc);
+}
+
+void getreg(unsigned long regnum, unsigned long *val,
+ int *nat, struct kvm_pt_regs *regs)
+{
+ unsigned long addr, *unat;
+ if (regnum >=3D IA64_FIRST_STACKED_GR) {
+ get_rse_reg(regs, regnum, val, nat);
+ return;
+ }
+
+ /*
+ * Now look at registers in [0-31] range and init correct UNAT
+ */
+ addr =3D (unsigned long)regs;
+ unat =3D ®s->eml_unat;;
+
+ addr +=3D gr_info[regnum];
+
+ *val =3D *(unsigned long *)addr;
+ /*
+ * do it only when requested
+ */
+ if (nat)
+ *nat =3D (*unat >> ((addr >> 3) & 0x3f)) & 0x1UL;
+}
+
+void setreg(unsigned long regnum, unsigned long val,
+ int nat, struct kvm_pt_regs *regs)
+{
+ unsigned long addr;
+ unsigned long bitmask;
+ unsigned long *unat;
+
+ /*
+ * First takes care of stacked registers
+ */
+ if (regnum >=3D IA64_FIRST_STACKED_GR) {
+ set_rse_reg(regs, regnum, val, nat);
+ return;
+ }
+
+ /*
+ * Now look at registers in [0-31] range and init correct UNAT
+ */
+ addr =3D (unsigned long)regs;
+ unat =3D ®s->eml_unat;
+ /*
+ * add offset from base of struct
+ * and do it !
+ */
+ addr +=3D gr_info[regnum];
+
+ *(unsigned long *)addr =3D val;
+
+ /*
+ * We need to clear the corresponding UNAT bit to fully emulate
the load
+ * UNAT bit_pos =3D GR[r3]{8:3} form EAS-2.4
+ */
+ bitmask =3D 1UL << ((addr >> 3) & 0x3f);
+ if (nat) {
+ *unat |=3D bitmask;
+ } else {
+ *unat &=3D ~bitmask;
+ }
+}
+
+u64 vcpu_get_gr(VCPU *vcpu, unsigned long reg)
+{
+ REGS *regs =3D vcpu_regs(vcpu);
+ u64 val;
+
+ if (!reg)
+ return 0;
+ getreg(reg, &val, 0, regs);
+ return val;
+}
+
+void vcpu_set_gr(VCPU *vcpu, u64 reg, u64 value, int nat)
+{
+ REGS *regs =3D vcpu_regs(vcpu);
+ long sof =3D (regs->cr_ifs) & 0x7f;
+
+ if (!reg)
+ return;
+ if (reg >=3D sof + 32)
+ return;
+ setreg(reg, value, nat, regs); /* FIXME: handle NATs later*/
+}
+
+void getfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
+ struct kvm_pt_regs *regs)
+{
+ /* Take floating register rotation into consideration*/
+ if (regnum >=3D IA64_FIRST_ROTATING_FR)
+ regnum =3D IA64_FIRST_ROTATING_FR + fph_index(regs,
regnum);
+#define CASE_FIXED_FP(reg) \
+ case (reg) : \
+ ia64_stf_spill(fpval, reg); \
+ break
+
+ switch (regnum) {
+ CASE_FIXED_FP(0);
+ CASE_FIXED_FP(1);
+ CASE_FIXED_FP(2);
+ CASE_FIXED_FP(3);
+ CASE_FIXED_FP(4);
+ CASE_FIXED_FP(5);
+
+ CASE_FIXED_FP(6);
+ CASE_FIXED_FP(7);
+ CASE_FIXED_FP(8);
+ CASE_FIXED_FP(9);
+ CASE_FIXED_FP(10);
+ CASE_FIXED_FP(11);
+
+ CASE_FIXED_FP(12);
+ CASE_FIXED_FP(13);
+ CASE_FIXED_FP(14);
+ CASE_FIXED_FP(15);
+ CASE_FIXED_FP(16);
+ CASE_FIXED_FP(17);
+ CASE_FIXED_FP(18);
+ CASE_FIXED_FP(19);
+ CASE_FIXED_FP(20);
+ CASE_FIXED_FP(21);
+ CASE_FIXED_FP(22);
+ CASE_FIXED_FP(23);
+ CASE_FIXED_FP(24);
+ CASE_FIXED_FP(25);
+ CASE_FIXED_FP(26);
+ CASE_FIXED_FP(27);
+ CASE_FIXED_FP(28);
+ CASE_FIXED_FP(29);
+ CASE_FIXED_FP(30);
+ CASE_FIXED_FP(31);
+ CASE_FIXED_FP(32);
+ CASE_FIXED_FP(33);
+ CASE_FIXED_FP(34);
+ CASE_FIXED_FP(35);
+ CASE_FIXED_FP(36);
+ CASE_FIXED_FP(37);
+ CASE_FIXED_FP(38);
+ CASE_FIXED_FP(39);
+ CASE_FIXED_FP(40);
+ CASE_FIXED_FP(41);
+ CASE_FIXED_FP(42);
+ CASE_FIXED_FP(43);
+ CASE_FIXED_FP(44);
+ CASE_FIXED_FP(45);
+ CASE_FIXED_FP(46);
+ CASE_FIXED_FP(47);
+ CASE_FIXED_FP(48);
+ CASE_FIXED_FP(49);
+ CASE_FIXED_FP(50);
+ CASE_FIXED_FP(51);
+ CASE_FIXED_FP(52);
+ CASE_FIXED_FP(53);
+ CASE_FIXED_FP(54);
+ CASE_FIXED_FP(55);
+ CASE_FIXED_FP(56);
+ CASE_FIXED_FP(57);
+ CASE_FIXED_FP(58);
+ CASE_FIXED_FP(59);
+ CASE_FIXED_FP(60);
+ CASE_FIXED_FP(61);
+ CASE_FIXED_FP(62);
+ CASE_FIXED_FP(63);
+ CASE_FIXED_FP(64);
+ CASE_FIXED_FP(65);
+ CASE_FIXED_FP(66);
+ CASE_FIXED_FP(67);
+ CASE_FIXED_FP(68);
+ CASE_FIXED_FP(69);
+ CASE_FIXED_FP(70);
+ CASE_FIXED_FP(71);
+ CASE_FIXED_FP(72);
+ CASE_FIXED_FP(73);
+ CASE_FIXED_FP(74);
+ CASE_FIXED_FP(75);
+ CASE_FIXED_FP(76);
+ CASE_FIXED_FP(77);
+ CASE_FIXED_FP(78);
+ CASE_FIXED_FP(79);
+ CASE_FIXED_FP(80);
+ CASE_FIXED_FP(81);
+ CASE_FIXED_FP(82);
+ CASE_FIXED_FP(83);
+ CASE_FIXED_FP(84);
+ CASE_FIXED_FP(85);
+ CASE_FIXED_FP(86);
+ CASE_FIXED_FP(87);
+ CASE_FIXED_FP(88);
+ CASE_FIXED_FP(89);
+ CASE_FIXED_FP(90);
+ CASE_FIXED_FP(91);
+ CASE_FIXED_FP(92);
+ CASE_FIXED_FP(93);
+ CASE_FIXED_FP(94);
+ CASE_FIXED_FP(95);
+ CASE_FIXED_FP(96);
+ CASE_FIXED_FP(97);
+ CASE_FIXED_FP(98);
+ CASE_FIXED_FP(99);
+ CASE_FIXED_FP(100);
+ CASE_FIXED_FP(101);
+ CASE_FIXED_FP(102);
+ CASE_FIXED_FP(103);
+ CASE_FIXED_FP(104);
+ CASE_FIXED_FP(105);
+ CASE_FIXED_FP(106);
+ CASE_FIXED_FP(107);
+ CASE_FIXED_FP(108);
+ CASE_FIXED_FP(109);
+ CASE_FIXED_FP(110);
+ CASE_FIXED_FP(111);
+ CASE_FIXED_FP(112);
+ CASE_FIXED_FP(113);
+ CASE_FIXED_FP(114);
+ CASE_FIXED_FP(115);
+ CASE_FIXED_FP(116);
+ CASE_FIXED_FP(117);
+ CASE_FIXED_FP(118);
+ CASE_FIXED_FP(119);
+ CASE_FIXED_FP(120);
+ CASE_FIXED_FP(121);
+ CASE_FIXED_FP(122);
+ CASE_FIXED_FP(123);
+ CASE_FIXED_FP(124);
+ CASE_FIXED_FP(125);
+ CASE_FIXED_FP(126);
+ CASE_FIXED_FP(127);
+ }
+#undef CASE_FIXED_FP
+}
+
+void setfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
+ struct kvm_pt_regs *regs)
+{
+ /* Take floating register rotation into consideration*/
+ if (regnum >=3D IA64_FIRST_ROTATING_FR)
+ regnum =3D IA64_FIRST_ROTATING_FR + fph_index(regs,
regnum);
+
+#define CASE_FIXED_FP(reg) \
+ case (reg) : \
+ ia64_ldf_fill(reg, fpval); \
+ break
+
+ switch (regnum) {
+ CASE_FIXED_FP(2);
+ CASE_FIXED_FP(3);
+ CASE_FIXED_FP(4);
+ CASE_FIXED_FP(5);
+
+ CASE_FIXED_FP(6);
+ CASE_FIXED_FP(7);
+ CASE_FIXED_FP(8);
+ CASE_FIXED_FP(9);
+ CASE_FIXED_FP(10);
+ CASE_FIXED_FP(11);
+
+ CASE_FIXED_FP(12);
+ CASE_FIXED_FP(13);
+ CASE_FIXED_FP(14);
+ CASE_FIXED_FP(15);
+ CASE_FIXED_FP(16);
+ CASE_FIXED_FP(17);
+ CASE_FIXED_FP(18);
+ CASE_FIXED_FP(19);
+ CASE_FIXED_FP(20);
+ CASE_FIXED_FP(21);
+ CASE_FIXED_FP(22);
+ CASE_FIXED_FP(23);
+ CASE_FIXED_FP(24);
+ CASE_FIXED_FP(25);
+ CASE_FIXED_FP(26);
+ CASE_FIXED_FP(27);
+ CASE_FIXED_FP(28);
+ CASE_FIXED_FP(29);
+ CASE_FIXED_FP(30);
+ CASE_FIXED_FP(31);
+ CASE_FIXED_FP(32);
+ CASE_FIXED_FP(33);
+ CASE_FIXED_FP(34);
+ CASE_FIXED_FP(35);
+ CASE_FIXED_FP(36);
+ CASE_FIXED_FP(37);
+ CASE_FIXED_FP(38);
+ CASE_FIXED_FP(39);
+ CASE_FIXED_FP(40);
+ CASE_FIXED_FP(41);
+ CASE_FIXED_FP(42);
+ CASE_FIXED_FP(43);
+ CASE_FIXED_FP(44);
+ CASE_FIXED_FP(45);
+ CASE_FIXED_FP(46);
+ CASE_FIXED_FP(47);
+ CASE_FIXED_FP(48);
+ CASE_FIXED_FP(49);
+ CASE_FIXED_FP(50);
+ CASE_FIXED_FP(51);
+ CASE_FIXED_FP(52);
+ CASE_FIXED_FP(53);
+ CASE_FIXED_FP(54);
+ CASE_FIXED_FP(55);
+ CASE_FIXED_FP(56);
+ CASE_FIXED_FP(57);
+ CASE_FIXED_FP(58);
+ CASE_FIXED_FP(59);
+ CASE_FIXED_FP(60);
+ CASE_FIXED_FP(61);
+ CASE_FIXED_FP(62);
+ CASE_FIXED_FP(63);
+ CASE_FIXED_FP(64);
+ CASE_FIXED_FP(65);
+ CASE_FIXED_FP(66);
+ CASE_FIXED_FP(67);
+ CASE_FIXED_FP(68);
+ CASE_FIXED_FP(69);
+ CASE_FIXED_FP(70);
+ CASE_FIXED_FP(71);
+ CASE_FIXED_FP(72);
+ CASE_FIXED_FP(73);
+ CASE_FIXED_FP(74);
+ CASE_FIXED_FP(75);
+ CASE_FIXED_FP(76);
+ CASE_FIXED_FP(77);
+ CASE_FIXED_FP(78);
+ CASE_FIXED_FP(79);
+ CASE_FIXED_FP(80);
+ CASE_FIXED_FP(81);
+ CASE_FIXED_FP(82);
+ CASE_FIXED_FP(83);
+ CASE_FIXED_FP(84);
+ CASE_FIXED_FP(85);
+ CASE_FIXED_FP(86);
+ CASE_FIXED_FP(87);
+ CASE_FIXED_FP(88);
+ CASE_FIXED_FP(89);
+ CASE_FIXED_FP(90);
+ CASE_FIXED_FP(91);
+ CASE_FIXED_FP(92);
+ CASE_FIXED_FP(93);
+ CASE_FIXED_FP(94);
+ CASE_FIXED_FP(95);
+ CASE_FIXED_FP(96);
+ CASE_FIXED_FP(97);
+ CASE_FIXED_FP(98);
+ CASE_FIXED_FP(99);
+ CASE_FIXED_FP(100);
+ CASE_FIXED_FP(101);
+ CASE_FIXED_FP(102);
+ CASE_FIXED_FP(103);
+ CASE_FIXED_FP(104);
+ CASE_FIXED_FP(105);
+ CASE_FIXED_FP(106);
+ CASE_FIXED_FP(107);
+ CASE_FIXED_FP(108);
+ CASE_FIXED_FP(109);
+ CASE_FIXED_FP(110);
+ CASE_FIXED_FP(111);
+ CASE_FIXED_FP(112);
+ CASE_FIXED_FP(113);
+ CASE_FIXED_FP(114);
+ CASE_FIXED_FP(115);
+ CASE_FIXED_FP(116);
+ CASE_FIXED_FP(117);
+ CASE_FIXED_FP(118);
+ CASE_FIXED_FP(119);
+ CASE_FIXED_FP(120);
+ CASE_FIXED_FP(121);
+ CASE_FIXED_FP(122);
+ CASE_FIXED_FP(123);
+ CASE_FIXED_FP(124);
+ CASE_FIXED_FP(125);
+ CASE_FIXED_FP(126);
+ CASE_FIXED_FP(127);
+ }
+}
+
+void vcpu_get_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg
*val)
+{
+ REGS *regs =3D vcpu_regs(vcpu);
+
+ getfpreg(reg, val, regs); /* FIXME: handle NATs later*/
+}
+
+void vcpu_set_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg
*val)
+{
+ REGS *regs =3D vcpu_regs(vcpu);
+
+ if (reg > 1)
+ setfpreg(reg, val, regs); /* FIXME: handle NATs
later*/
+}
+
+
+/**********************************************************************
**
+ * lsapic timer
+
***********************************************************************/
+u64 vcpu_get_itc(VCPU *vcpu)
+{
+ unsigned long guest_itc;
+ guest_itc =3D VMX(vcpu, itc_offset) + ia64_get_itc();
+
+ if (guest_itc >=3D VMX(vcpu, last_itc)) {
+ VMX(vcpu, last_itc) =3D guest_itc;
+ return guest_itc;
+ } else
+ return VMX(vcpu, last_itc);
+}
+
+static inline void vcpu_set_itm(VCPU *vcpu, u64 val);
+static void vcpu_set_itc(VCPU *vcpu, u64 val)
+{
+ VCPU *v;
+ int i;
+ long itc_offset =3D val - ia64_get_itc();
+ unsigned long vitv =3D VCPU(vcpu, itv);
+
+ if (vcpu->vcpu_id =3D=3D 0) {
+ for (i =3D 0; i < MAX_VCPU_NUM; i++) {
+ v =3D (VCPU *)((char *)vcpu + VCPU_SIZE * i);
+ VMX(v, itc_offset) =3D itc_offset;
+ VMX(v, last_itc) =3D 0;
+ }
+ }
+ VMX(vcpu, last_itc) =3D 0;
+ if (VCPU(vcpu, itm) <=3D val) {
+ VMX(vcpu, itc_check) =3D 0;
+ vcpu_unpend_interrupt(vcpu, vitv);
+ } else {
+ VMX(vcpu, itc_check) =3D 1;
+ vcpu_set_itm(vcpu, VCPU(vcpu, itm));
+ }
+
+}
+
+static inline u64 vcpu_get_itm(VCPU *vcpu)
+{
+ return ((u64)VCPU(vcpu, itm));
+}
+
+static inline void vcpu_set_itm(VCPU *vcpu, u64 val)
+{
+ unsigned long vitv =3D VCPU(vcpu, itv);
+ VCPU(vcpu, itm) =3D val;
+
+ if (val > vcpu_get_itc(vcpu)) {
+ VMX(vcpu, itc_check) =3D 1;
+ vcpu_unpend_interrupt(vcpu, vitv);
+ VMX(vcpu, timer_pending) =3D 0;
+ } else
+ VMX(vcpu, itc_check) =3D 0;
+}
+
+#define ITV_VECTOR(itv) (itv&0xff)
+#define ITV_IRQ_MASK(itv) (itv&(1<<16))
+
+static inline void vcpu_set_itv(VCPU *vcpu, u64 val)
+{
+ VCPU(vcpu, itv) =3D val;
+ if (!ITV_IRQ_MASK(val) && vcpu->arch.timer_pending) {
+ vcpu_pend_interrupt(vcpu, ITV_VECTOR(val));
+ vcpu->arch.timer_pending =3D 0;
+ }
+}
+
+static inline void vcpu_set_eoi(VCPU *vcpu, u64 val)
+{
+ int vec;
+
+ vec =3D highest_inservice_irq(vcpu);
+ if (vec =3D=3D NULL_VECTOR)
+ return;
+ VMX(vcpu, insvc[vec >> 6]) &=3D ~(1UL << (vec & 63));
+ VCPU(vcpu, eoi) =3D 0;
+ vcpu->arch.irq_new_pending =3D 1;
+
+}
+
+/* See Table 5-8 in SDM vol2 for the definition */
+int irq_masked(VCPU *vcpu, int h_pending, int h_inservice)
+{
+ ia64_tpr vtpr;
+
+ vtpr.val =3D VCPU(vcpu, tpr);
+
+ if (h_inservice =3D=3D NMI_VECTOR)
+ return IRQ_MASKED_BY_INSVC;
+
+ if (h_pending =3D=3D NMI_VECTOR) {
+ /* Non Maskable Interrupt */
+ return IRQ_NO_MASKED;
+ }
+
+ if (h_inservice =3D=3D ExtINT_VECTOR)
+ return IRQ_MASKED_BY_INSVC;
+
+ if (h_pending =3D=3D ExtINT_VECTOR) {
+ if (vtpr.mmi) {
+ /* mask all external IRQ */
+ return IRQ_MASKED_BY_VTPR;
+ } else
+ return IRQ_NO_MASKED;
+ }
+
+ if (is_higher_irq(h_pending, h_inservice)) {
+ if (is_higher_class(h_pending, vtpr.mic + (vtpr.mmi <<
4)))
+ return IRQ_NO_MASKED;
+ else
+ return IRQ_MASKED_BY_VTPR;
+ } else {
+ return IRQ_MASKED_BY_INSVC;
+ }
+}
+
+void vcpu_pend_interrupt(VCPU *vcpu, u8 vec)
+{
+ long spsr;
+ int ret;
+
+ local_irq_save(spsr);
+ ret =3D test_and_set_bit(vec, &VCPU(vcpu, irr[0]));
+ local_irq_restore(spsr);
+
+ vcpu->arch.irq_new_pending =3D 1;
+}
+
+void vcpu_unpend_interrupt(VCPU *vcpu, u8 vec)
+{
+ long spsr;
+ int ret;
+
+ local_irq_save(spsr);
+ ret =3D test_and_clear_bit(vec, &VCPU(vcpu, irr[0]));
+ local_irq_restore(spsr);
+ if (ret) {
+ vcpu->arch.irq_new_pending =3D 1;
+ wmb();
+ }
+}
+
+void update_vhpi(VCPU *vcpu, int vec)
+{
+ u64 vhpi;
+
+ if (vec =3D=3D NULL_VECTOR)
+ vhpi =3D 0;
+ else if (vec =3D=3D NMI_VECTOR)
+ vhpi =3D 32;
+ else if (vec =3D=3D ExtINT_VECTOR)
+ vhpi =3D 16;
+ else
+ vhpi =3D vec >> 4;
+
+ VCPU(vcpu, vhpi) =3D vhpi;
+ if (VCPU(vcpu, vac).a_int)
+ ia64_call_vsa(PAL_VPS_SET_PENDING_INTERRUPT,
+ (u64)vcpu->arch.vpd, 0, 0, 0, 0, 0, 0);
+}
+
+u64 vcpu_get_ivr(VCPU *vcpu)
+{
+ int vec, h_inservice, mask;
+
+ vec =3D highest_pending_irq(vcpu);
+ h_inservice =3D highest_inservice_irq(vcpu);
+ mask =3D irq_masked(vcpu, vec, h_inservice);
+ if (vec =3D=3D NULL_VECTOR || mask =3D=3D IRQ_MASKED_BY_INSVC) {
+ if (VCPU(vcpu, vhpi))
+ update_vhpi(vcpu, NULL_VECTOR);
+ return IA64_SPURIOUS_INT_VECTOR;
+ }
+ if (mask =3D=3D IRQ_MASKED_BY_VTPR) {
+ update_vhpi(vcpu, vec);
+ return IA64_SPURIOUS_INT_VECTOR;
+ }
+ VMX(vcpu, insvc[vec >> 6]) |=3D (1UL << (vec & 63));
+ vcpu_unpend_interrupt(vcpu, vec);
+ return (u64)vec;
+}
+
+/**********************************************************************
****
+ Privileged operation emulation routines
+
************************************************************************
**/
+u64 vcpu_thash(VCPU *vcpu, u64 vadr)
+{
+ ia64_pta vpta;
+ ia64_rr vrr;
+ u64 pval;
+ u64 vhpt_offset;
+
+ vpta.val =3D vcpu_get_pta(vcpu);
+ vrr.val =3D vcpu_get_rr(vcpu, vadr);
+ vhpt_offset =3D ((vadr >> vrr.ps) << 3) & ((1UL << (vpta.size)) -
1);
+ if (vpta.vf) {
+ pval =3D ia64_call_vsa(PAL_VPS_THASH, vadr, vrr.val,
+ vpta.val, 0, 0, 0, 0);
+ } else {
+ pval =3D (vadr & VRN_MASK) | vhpt_offset |
+ (vpta.val << 3 >> (vpta.size + 3) <<
(vpta.size));
+ }
+ return pval;
+}
+
+u64 vcpu_ttag(VCPU *vcpu, u64 vadr)
+{
+ ia64_rr vrr;
+ ia64_pta vpta;
+ u64 pval;
+
+ vpta.val =3D vcpu_get_pta(vcpu);
+ vrr.val =3D vcpu_get_rr(vcpu, vadr);
+ if (vpta.vf) {
+ pval =3D ia64_call_vsa(PAL_VPS_TTAG, vadr, vrr.val,
+ 0, 0, 0, 0, 0);
+ } else
+ pval =3D 1;
+
+ return pval;
+}
+
+u64 vcpu_tak(VCPU *vcpu, u64 vadr)
+{
+ thash_data_t *data;
+ ia64_pta vpta;
+ u64 key;
+
+ vpta.val =3D vcpu_get_pta(vcpu);
+ if (vpta.vf =3D=3D 0) {
+ key =3D 1;
+ return key;
+ }
+ data =3D vtlb_lookup(vcpu, vadr, D_TLB);
+ if (!data || !data->p) {
+ key =3D 1;
+ } else{
+ key =3D data->key;
+ }
+
+ return key;
+}
+
+
+
+void kvm_thash(VCPU *vcpu, INST64 inst)
+{
+ unsigned long thash, vadr;
+
+ vadr =3D vcpu_get_gr(vcpu, inst.M46.r3);
+ thash =3D vcpu_thash(vcpu, vadr);
+ vcpu_set_gr(vcpu, inst.M46.r1, thash, 0);
+}
+
+
+void kvm_ttag(VCPU *vcpu, INST64 inst)
+{
+ unsigned long tag, vadr;
+
+ vadr =3D vcpu_get_gr(vcpu, inst.M46.r3);
+ tag =3D vcpu_ttag(vcpu, vadr);
+ vcpu_set_gr(vcpu, inst.M46.r1, tag, 0);
+}
+
+int vcpu_tpa(VCPU *vcpu, u64 vadr, u64 *padr)
+{
+ thash_data_t *data;
+ ia64_isr visr, pt_isr;
+ REGS *regs;
+ ia64_psr vpsr;
+
+ regs =3D vcpu_regs(vcpu);
+ pt_isr.val =3D VMX(vcpu, cr_isr);
+ visr.val =3D 0;
+ visr.ei =3D pt_isr.ei;
+ visr.ir =3D pt_isr.ir;
+ vpsr.val =3D VCPU(vcpu, vpsr);
+ visr.na =3D 1;
+
+ data =3D vhpt_lookup(vadr);
+ if (data) {
+ if (data->p =3D=3D 0) {
+ vcpu_set_isr(vcpu, visr.val);
+ data_page_not_present(vcpu, vadr);
+ return IA64_FAULT;
+ } else if (data->ma =3D=3D VA_MATTR_NATPAGE) {
+ vcpu_set_isr(vcpu, visr.val);
+ dnat_page_consumption(vcpu, vadr);
+ return IA64_FAULT;
+ } else {
+ *padr =3D (data->gpaddr >> data->ps << data->ps) |
+ (vadr & (PSIZE(data->ps) - 1));
+ return IA64_NO_FAULT;
+ }
+ }
+
+ data =3D vtlb_lookup(vcpu, vadr, D_TLB);
+ if (data) {
+ if (data->p =3D=3D 0) {
+ vcpu_set_isr(vcpu, visr.val);
+ data_page_not_present(vcpu, vadr);
+ return IA64_FAULT;
+ } else if (data->ma =3D=3D VA_MATTR_NATPAGE) {
+ vcpu_set_isr(vcpu, visr.val);
+ dnat_page_consumption(vcpu, vadr);
+ return IA64_FAULT;
+ } else{
+ *padr =3D ((data->ppn >> (data->ps - 12)) <<
data->ps)
+ | (vadr & (PSIZE(data->ps) - 1));
+ return IA64_NO_FAULT;
+ }
+ }
+ if (!vhpt_enabled(vcpu, vadr, NA_REF)) {
+ if (vpsr.ic) {
+ vcpu_set_isr(vcpu, visr.val);
+ alt_dtlb(vcpu, vadr);
+ return IA64_FAULT;
+ } else {
+ nested_dtlb(vcpu);
+ return IA64_FAULT;
+ }
+ } else {
+ if (vpsr.ic) {
+ vcpu_set_isr(vcpu, visr.val);
+ dvhpt_fault(vcpu, vadr);
+ return IA64_FAULT;
+ } else{
+ nested_dtlb(vcpu);
+ return IA64_FAULT;
+ }
+ }
+
+ return IA64_NO_FAULT;
+}
+
+
+int kvm_tpa(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r1, r3;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M46.r3);
+
+ if (vcpu_tpa(vcpu, r3, &r1))
+ return IA64_FAULT;
+
+ vcpu_set_gr(vcpu, inst.M46.r1, r1, 0);
+ return(IA64_NO_FAULT);
+}
+
+void kvm_tak(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r1, r3;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M46.r3);
+ r1 =3D vcpu_tak(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M46.r1, r1, 0);
+}
+
+
+/************************************
+ * Insert/Purge translation register/cache
+ ************************************/
+void vcpu_itc_i(VCPU *vcpu, u64 pte, u64 itir, u64 ifa)
+{
+ thash_purge_and_insert(vcpu, pte, itir, ifa, I_TLB);
+}
+
+void vcpu_itc_d(VCPU *vcpu, u64 pte, u64 itir, u64 ifa)
+{
+ thash_purge_and_insert(vcpu, pte, itir, ifa, D_TLB);
+}
+
+void vcpu_itr_i(VCPU *vcpu, u64 slot, u64 pte, u64 itir, u64 ifa)
+{
+ u64 ps, va, rid;
+ thash_data_t *p_itr;
+
+ ps =3D itir_ps(itir);
+ va =3D PAGEALIGN(ifa, ps);
+ pte &=3D ~PAGE_FLAGS_RV_MASK;
+ rid =3D vcpu_get_rr(vcpu, ifa);
+ rid =3D rid & RR_RID_MASK;
+ p_itr =3D (thash_data_t *)&vcpu->arch.itrs[slot];
+ vcpu_set_tr(p_itr, pte, itir, va, rid);
+ vcpu_quick_region_set(VMX(vcpu, itr_regions), va);
+}
+
+
+void vcpu_itr_d(VCPU *vcpu, u64 slot, u64 pte, u64 itir, u64 ifa)
+{
+ u64 gpfn;
+ u64 ps, va, rid;
+ thash_data_t *p_dtr;
+
+ ps =3D itir_ps(itir);
+ va =3D PAGEALIGN(ifa, ps);
+ pte &=3D ~PAGE_FLAGS_RV_MASK;
+
+ /* This is a bad workaround
+ In Linux, region 7 use 16M pagesize and is identity mapped.
+ VHPT page size is 16K in XEN. If purge VHPT while guest
insert 16M,
+ it will iteratively purge VHPT 1024 times, which makes
XEN/IPF very
+ slow. XEN doesn't purge VHPT
+ */
+ if (ps !=3D _PAGE_SIZE_16M)
+ thash_purge_entries(vcpu, va, ps);
+ gpfn =3D (pte & _PAGE_PPN_MASK) >> PAGE_SHIFT;
+ if (__gpfn_is_io(gpfn))
+ pte |=3D VTLB_PTE_IO;
+ rid =3D vcpu_get_rr(vcpu, va);
+ rid =3D rid & RR_RID_MASK;
+ p_dtr =3D (thash_data_t *)&vcpu->arch.dtrs[slot];
+ vcpu_set_tr((thash_data_t *)&vcpu->arch.dtrs[slot], pte, itir,
va, rid);
+ vcpu_quick_region_set(VMX(vcpu, dtr_regions), va);
+}
+
+void vcpu_ptr_d(VCPU *vcpu, u64 ifa, u64 ps)
+{
+ int index;
+ u64 va;
+
+ va =3D PAGEALIGN(ifa, ps);
+ while ((index =3D vtr_find_overlap(vcpu, va, ps, D_TLB)) >=3D 0)
+ vcpu->arch.dtrs[index].page_flags =3D 0;
+
+ thash_purge_entries(vcpu, va, ps);
+}
+
+void vcpu_ptr_i(VCPU *vcpu, u64 ifa, u64 ps)
+{
+ int index;
+ u64 va;
+
+ va =3D PAGEALIGN(ifa, ps);
+ while ((index =3D vtr_find_overlap(vcpu, va, ps, I_TLB)) >=3D 0)
+ vcpu->arch.itrs[index].page_flags =3D 0;
+
+ thash_purge_entries(vcpu, va, ps);
+}
+
+void vcpu_ptc_l(VCPU *vcpu, u64 va, u64 ps)
+{
+ va =3D PAGEALIGN(va, ps);
+ thash_purge_entries(vcpu, va, ps);
+}
+
+void vcpu_ptc_e(VCPU *vcpu, u64 va)
+{
+ thash_purge_all(vcpu);
+}
+
+void vcpu_ptc_ga(VCPU *vcpu, u64 va, u64 ps)
+{
+ struct exit_ctl_data *p =3D &vcpu->arch.exit_data;
+ long psr;
+ local_irq_save(psr);
+ p->exit_reason =3D EXIT_REASON_PTC_G;
+
+ p->u.ptc_g_data.rr =3D vcpu_get_rr(vcpu, va);
+ p->u.ptc_g_data.vaddr =3D va;
+ p->u.ptc_g_data.ps =3D ps;
+ vmm_transition(vcpu);
+ /* Do Local Purge Here*/
+ vcpu_ptc_l(vcpu, va, ps);
+ local_irq_restore(psr);
+}
+
+
+void vcpu_ptc_g(VCPU *vcpu, u64 va, u64 ps)
+{
+ vcpu_ptc_ga(vcpu, va, ps);
+}
+
+void kvm_ptc_e(VCPU *vcpu, INST64 inst)
+{
+ unsigned long ifa;
+
+ ifa =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ vcpu_ptc_e(vcpu, ifa);
+}
+
+void kvm_ptc_g(VCPU *vcpu, INST64 inst)
+{
+ unsigned long ifa, itir;
+
+ ifa =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ itir =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_ptc_g(vcpu, ifa, itir_ps(itir));
+}
+
+void kvm_ptc_ga(VCPU *vcpu, INST64 inst)
+{
+ unsigned long ifa, itir;
+
+ ifa =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ itir =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_ptc_ga(vcpu, ifa, itir_ps(itir));
+}
+
+void kvm_ptc_l(VCPU *vcpu, INST64 inst)
+{
+ unsigned long ifa, itir;
+
+ ifa =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ itir =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_ptc_l(vcpu, ifa, itir_ps(itir));
+}
+
+void kvm_ptr_d(VCPU *vcpu, INST64 inst)
+{
+ unsigned long ifa, itir;
+
+ ifa =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ itir =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_ptr_d(vcpu, ifa, itir_ps(itir));
+}
+
+void kvm_ptr_i(VCPU *vcpu, INST64 inst)
+{
+ unsigned long ifa, itir;
+
+ ifa =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ itir =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_ptr_i(vcpu, ifa, itir_ps(itir));
+}
+
+void kvm_itr_d(VCPU *vcpu, INST64 inst)
+{
+ unsigned long itir, ifa, pte, slot;
+
+ slot =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ pte =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ itir =3D vcpu_get_itir(vcpu);
+ ifa =3D vcpu_get_ifa(vcpu);
+ vcpu_itr_d(vcpu, slot, pte, itir, ifa);
+}
+
+
+
+void kvm_itr_i(VCPU *vcpu, INST64 inst)
+{
+ unsigned long itir, ifa, pte, slot;
+
+ slot =3D vcpu_get_gr(vcpu, inst.M45.r3);
+ pte =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ itir =3D vcpu_get_itir(vcpu);
+ ifa =3D vcpu_get_ifa(vcpu);
+ vcpu_itr_i(vcpu, slot, pte, itir, ifa);
+}
+
+void kvm_itc_d(VCPU *vcpu, INST64 inst)
+{
+ unsigned long itir, ifa, pte;
+
+ itir =3D vcpu_get_itir(vcpu);
+ ifa =3D vcpu_get_ifa(vcpu);
+ pte =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_itc_d(vcpu, pte, itir, ifa);
+}
+
+void kvm_itc_i(VCPU *vcpu, INST64 inst)
+{
+ unsigned long itir, ifa, pte;
+
+ itir =3D vcpu_get_itir(vcpu);
+ ifa =3D vcpu_get_ifa(vcpu);
+ pte =3D vcpu_get_gr(vcpu, inst.M45.r2);
+ vcpu_itc_i(vcpu, pte, itir, ifa);
+}
+
+/*************************************
+ * Moves to semi-privileged registers
+ *************************************/
+
+void kvm_mov_to_ar_imm(VCPU *vcpu, INST64 inst)
+{
+ unsigned long imm;
+
+ if (inst.M30.s) {
+ imm =3D -inst.M30.imm;
+ } else {
+ imm =3D inst.M30.imm;
+ }
+
+ vcpu_set_itc(vcpu, imm);
+}
+
+void kvm_mov_to_ar_reg(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r2;
+
+ r2 =3D vcpu_get_gr(vcpu, inst.M29.r2);
+ vcpu_set_itc(vcpu, r2);
+}
+
+
+void kvm_mov_from_ar_reg(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r1;
+
+ r1 =3D vcpu_get_itc(vcpu);
+ vcpu_set_gr(vcpu, inst.M31.r1, r1, 0);
+}
+/**********************************************************************
****
+ VCPU protection key register access routines
+
************************************************************************
**/
+
+unsigned long vcpu_get_pkr(VCPU *vcpu, unsigned long reg)
+{
+ return ((unsigned long)ia64_get_pkr(reg));
+}
+
+void vcpu_set_pkr(VCPU *vcpu, unsigned long reg, unsigned long val)
+{
+ ia64_set_pkr(reg, val);
+}
+
+
+unsigned long vcpu_get_itir_on_fault(VCPU *vcpu, unsigned long ifa)
+{
+ ia64_rr rr, rr1;
+
+ rr.val =3D vcpu_get_rr(vcpu, ifa);
+ rr1.val =3D 0;
+ rr1.ps =3D rr.ps;
+ rr1.rid =3D rr.rid;
+ return (rr1.val);
+}
+
+
+
+/********************************
+ * Moves to privileged registers
+ ********************************/
+unsigned long vcpu_set_rr(VCPU *vcpu, unsigned long reg, unsigned long
val)
+{
+ ia64_rr oldrr, newrr;
+ unsigned long rrval;
+ struct exit_ctl_data *p =3D &vcpu->arch.exit_data;
+ unsigned long psr;
+
+ oldrr.val =3D vcpu_get_rr(vcpu, reg);
+ newrr.val =3D val;
+ vcpu->arch.vrr[reg >> VRN_SHIFT] =3D val;
+
+ switch ((unsigned long)(reg >> VRN_SHIFT)) {
+ case VRN6:
+ vcpu->arch.vmm_rr =3D vrrtomrr(val);
+ local_irq_save(psr);
+ p->exit_reason =3D EXIT_REASON_SWITCH_RR6;
+ vmm_transition(vcpu);
+ local_irq_restore(psr);
+ break;
+ case VRN4:
+ rrval =3D vrrtomrr(val);
+ vcpu->arch.metaphysical_saved_rr4 =3D rrval;
+ if (!is_physical_mode(vcpu))
+ ia64_set_rr(reg, rrval);
+ break;
+ case VRN0:
+ rrval =3D vrrtomrr(val);
+ vcpu->arch.metaphysical_saved_rr0 =3D rrval;
+ if (!is_physical_mode(vcpu))
+ ia64_set_rr(reg, rrval);
+ break;
+ default:
+ ia64_set_rr(reg, vrrtomrr(val));
+ break;
+ }
+
+ return (IA64_NO_FAULT);
+}
+
+
+
+void kvm_mov_to_rr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r2;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M42.r3);
+ r2 =3D vcpu_get_gr(vcpu, inst.M42.r2);
+ vcpu_set_rr(vcpu, r3, r2);
+}
+
+void kvm_mov_to_dbr(VCPU *vcpu, INST64 inst)
+{
+}
+
+void kvm_mov_to_ibr(VCPU *vcpu, INST64 inst)
+{
+}
+
+void kvm_mov_to_pmc(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r2;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M42.r3);
+ r2 =3D vcpu_get_gr(vcpu, inst.M42.r2);
+ vcpu_set_pmc(vcpu, r3, r2);
+}
+
+void kvm_mov_to_pmd(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r2;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M42.r3);
+ r2 =3D vcpu_get_gr(vcpu, inst.M42.r2);
+ vcpu_set_pmd(vcpu, r3, r2);
+}
+
+void kvm_mov_to_pkr(VCPU *vcpu, INST64 inst)
+{
+ u64 r3, r2;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M42.r3);
+ r2 =3D vcpu_get_gr(vcpu, inst.M42.r2);
+ vcpu_set_pkr(vcpu, r3, r2);
+}
+
+
+
+void kvm_mov_from_rr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r1;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M43.r3);
+ r1 =3D vcpu_get_rr(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M43.r1, r1, 0);
+}
+
+void kvm_mov_from_pkr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r1;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M43.r3);
+ r1 =3D vcpu_get_pkr(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M43.r1, r1, 0);
+}
+
+void kvm_mov_from_dbr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r1;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M43.r3);
+ r1 =3D vcpu_get_dbr(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M43.r1, r1, 0);
+}
+
+void kvm_mov_from_ibr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r1;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M43.r3);
+ r1 =3D vcpu_get_ibr(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M43.r1, r1, 0);
+}
+
+void kvm_mov_from_pmc(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r1;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M43.r3);
+ r1 =3D vcpu_get_pmc(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M43.r1, r1, 0);
+}
+
+
+unsigned long vcpu_get_cpuid(VCPU *vcpu, unsigned long reg)
+{
+ /* FIXME: This could get called as a result of a rsvd-reg fault
*/
+ if (reg > (ia64_get_cpuid(3) & 0xff))
+ return 0;
+ else
+ return ia64_get_cpuid(reg);
+}
+
+void kvm_mov_from_cpuid(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r3, r1;
+
+ r3 =3D vcpu_get_gr(vcpu, inst.M43.r3);
+ r1 =3D vcpu_get_cpuid(vcpu, r3);
+ vcpu_set_gr(vcpu, inst.M43.r1, r1, 0);
+}
+
+void vcpu_set_tpr(VCPU *vcpu, unsigned long val)
+{
+ VCPU(vcpu, tpr) =3D val;
+ vcpu->arch.irq_check =3D 1;
+}
+
+unsigned long kvm_mov_to_cr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long r2;
+
+ r2 =3D vcpu_get_gr(vcpu, inst.M32.r2);
+ VCPU(vcpu, vcr[inst.M32.cr3]) =3D r2;
+
+ switch (inst.M32.cr3) {
+ case 0:
+ vcpu_set_dcr(vcpu, r2);
+ break;
+ case 1:
+ vcpu_set_itm(vcpu, r2);
+ break;
+ case 66:
+ vcpu_set_tpr(vcpu, r2);
+ break;
+ case 67:
+ vcpu_set_eoi(vcpu, r2);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+
+unsigned long kvm_mov_from_cr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long tgt =3D inst.M33.r1;
+ unsigned long val;
+
+ switch (inst.M33.cr3) {
+ case 65:
+ val =3D vcpu_get_ivr(vcpu);
+ vcpu_set_gr(vcpu, tgt, val, 0);
+ break;
+
+ case 67:
+ vcpu_set_gr(vcpu, tgt, 0L, 0);
+ break;
+ default:
+ val =3D VCPU(vcpu, vcr[inst.M33.cr3]);
+ vcpu_set_gr(vcpu, tgt, val, 0);
+ break;
+ }
+
+ return 0;
+}
+
+
+
+void vcpu_set_psr(VCPU *vcpu, unsigned long val)
+{
+
+ unsigned long mask;
+ REGS *regs;
+ ia64_psr old_psr, new_psr;
+
+ old_psr =3D (ia64_psr)VCPU(vcpu, vpsr);
+
+ regs =3D vcpu_regs(vcpu);
+ /* We only support guest as:
+ * vpsr.pk =3D 0
+ * vpsr.is =3D 0
+ * Otherwise panic
+ */
+ if (val & (IA64_PSR_PK | IA64_PSR_IS | IA64_PSR_VM))
+ panic_vm(vcpu);
+
+ /*
+ * For those IA64_PSR bits: id/da/dd/ss/ed/ia
+ * Since these bits will become 0, after success execution of
each
+ * instruction, we will change set them to mIA64_PSR
+ */
+ VCPU(vcpu, vpsr) =3D val
+ & (~(IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD |
+ IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA));
+
+ if (!old_psr.i && (val & IA64_PSR_I)) {
+ /* vpsr.i 0->1 */
+ vcpu->arch.irq_check =3D 1;
+ }
+ new_psr.val =3D VCPU(vcpu, vpsr);
+
+ /*
+ * All vIA64_PSR bits shall go to mPSR (v->tf->tf_special.psr)
+ * , except for the following bits:
+ * ic/i/dt/si/rt/mc/it/bn/vm
+ */
+ mask =3D IA64_PSR_IC + IA64_PSR_I + IA64_PSR_DT + IA64_PSR_SI +
+ IA64_PSR_RT + IA64_PSR_MC + IA64_PSR_IT + IA64_PSR_BN +
+ IA64_PSR_VM;
+
+ regs->cr_ipsr =3D (regs->cr_ipsr & mask) | (val & (~mask));
+
+ check_mm_mode_switch(vcpu, old_psr, new_psr);
+
+ return ;
+}
+
+unsigned long vcpu_cover(VCPU *vcpu)
+{
+ ia64_psr vpsr;
+
+ REGS *regs =3D vcpu_regs(vcpu);
+ vpsr =3D (ia64_psr)VCPU(vcpu, vpsr);
+
+ if (!vpsr.ic)
+ VCPU(vcpu, ifs) =3D regs->cr_ifs;
+ regs->cr_ifs =3D IA64_IFS_V;
+ return (IA64_NO_FAULT);
+}
+
+
+
+/**********************************************************************
****
+ VCPU banked general register access routines
+
************************************************************************
**/
+#define vcpu_bsw0_unat(i, b0unat, b1unat, runat, VMM_PT_REGS_R16_SLOT)
\
+ do {
\
+ __asm__ __volatile__ (
\
+ ";;extr.u %0 =3D %3,%6,16;;\n"
\
+ "dep %1 =3D %0, %1, 0, 16;;\n"
\
+ "st8 [%4] =3D %1\n"
\
+ "extr.u %0 =3D %2, 16, 16;;\n"
\
+ "dep %3 =3D %0, %3, %6, 16;;\n"
\
+ "st8 [%5] =3D %3\n"
\
+ ::"r"(i), "r"(*b1unat), "r"(*b0unat),
\
+ "r"(*runat), "r"(b1unat), "r"(runat),
\
+ "i"(VMM_PT_REGS_R16_SLOT) : "memory");
\
+ } while (0)
+
+void vcpu_bsw0(VCPU *vcpu)
+{
+ unsigned long i;
+
+ REGS *regs =3D vcpu_regs(vcpu);
+ unsigned long *r =3D ®s->r16;
+ unsigned long *b0 =3D &VCPU(vcpu, vbgr[0]);
+ unsigned long *b1 =3D &VCPU(vcpu, vgr[0]);
+ unsigned long *runat =3D ®s->eml_unat;
+ unsigned long *b0unat =3D &VCPU(vcpu, vbnat);
+ unsigned long *b1unat =3D &VCPU(vcpu, vnat);
+
+
+ if (VCPU(vcpu, vpsr) & IA64_PSR_BN) {
+ for (i =3D 0; i < 16; i++) {
+ *b1++ =3D *r;
+ *r++ =3D *b0++;
+ }
+ vcpu_bsw0_unat(i, b0unat, b1unat, runat,
+ VMM_PT_REGS_R16_SLOT);
+ VCPU(vcpu, vpsr) &=3D ~IA64_PSR_BN;
+ }
+}
+
+#define vcpu_bsw1_unat(i, b0unat, b1unat, runat, VMM_PT_REGS_R16_SLOT)
\
+ do {
\
+ __asm__ __volatile__ (";;extr.u %0 =3D %3, %6, 16;;\n"
\
+ "dep %1 =3D %0, %1, 16, 16;;\n"
\
+ "st8 [%4] =3D %1\n"
\
+ "extr.u %0 =3D %2, 0, 16;;\n"
\
+ "dep %3 =3D %0, %3, %6, 16;;\n"
\
+ "st8 [%5] =3D %3\n"
\
+ ::"r"(i), "r"(*b0unat), "r"(*b1unat),
\
+ "r"(*runat), "r"(b0unat), "r"(runat),
\
+ "i"(VMM_PT_REGS_R16_SLOT) : "memory");
\
+ } while (0)
+
+void vcpu_bsw1(VCPU *vcpu)
+{
+ /* TODO: Only allowed for current vcpu */
+ unsigned long i;
+ REGS *regs =3D vcpu_regs(vcpu);
+ unsigned long *r =3D ®s->r16;
+ unsigned long *b0 =3D &VCPU(vcpu, vbgr[0]);
+ unsigned long *b1 =3D &VCPU(vcpu, vgr[0]);
+ unsigned long *runat =3D ®s->eml_unat;
+ unsigned long *b0unat =3D &VCPU(vcpu, vbnat);
+ unsigned long *b1unat =3D &VCPU(vcpu, vnat);
+
+ if (!(VCPU(vcpu, vpsr) & IA64_PSR_BN)) {
+ for (i =3D 0; i < 16; i++) {
+ *b0++ =3D *r;
+ *r++ =3D *b1++;
+ }
+ vcpu_bsw1_unat(i, b0unat, b1unat, runat,
+ VMM_PT_REGS_R16_SLOT);
+ VCPU(vcpu, vpsr) |=3D IA64_PSR_BN;
+ }
+}
+
+
+
+
+void vcpu_rfi(VCPU *vcpu)
+{
+ /* TODO: Only allowed for current vcpu */
+ unsigned long ifs, psr;
+ REGS *regs =3D vcpu_regs(vcpu);
+
+ psr =3D VCPU(vcpu, ipsr);
+ if (psr & IA64_PSR_BN)
+ vcpu_bsw1(vcpu);
+ else
+ vcpu_bsw0(vcpu);
+ vcpu_set_psr(vcpu, psr);
+ ifs =3D VCPU(vcpu, ifs);
+ if (ifs >> 63)
+ regs->cr_ifs =3D ifs;
+ regs->cr_iip =3D VCPU(vcpu, iip);
+}
+
+
+/*
+ VPSR can't keep track of below bits of guest PSR
+ This function gets guest PSR
+ */
+
+unsigned long vcpu_get_psr(VCPU *vcpu)
+{
+ unsigned long mask;
+ REGS *regs =3D vcpu_regs(vcpu);
+
+ mask =3D IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL |
+ IA64_PSR_MFH | IA64_PSR_CPL | IA64_PSR_RI;
+ return (VCPU(vcpu, vpsr) & ~mask) | (regs->cr_ipsr & mask);
+}
+
+void kvm_rsm(VCPU *vcpu, INST64 inst)
+{
+ unsigned long vpsr;
+ unsigned long imm24 =3D (inst.M44.i<<23) | (inst.M44.i2<<21)
+ | inst.M44.imm;
+
+ vpsr =3D vcpu_get_psr(vcpu);
+ vpsr &=3D (~imm24);
+ vcpu_set_psr(vcpu, vpsr);
+}
+
+void kvm_ssm(VCPU *vcpu, INST64 inst)
+{
+ unsigned long vpsr;
+ unsigned long imm24 =3D (inst.M44.i << 23) | (inst.M44.i2 << 21)
+ | inst.M44.imm;
+
+ vpsr =3D vcpu_get_psr(vcpu);
+ vpsr |=3D imm24;
+ vcpu_set_psr(vcpu, vpsr);
+}
+
+void vcpu_set_psr_l(VCPU *vcpu, unsigned long val)
+{
+ val =3D (val & MASK(0, 32)) | (vcpu_get_psr(vcpu) & MASK(32, 32));
+ vcpu_set_psr(vcpu, val);
+}
+
+void kvm_mov_to_psr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long val;
+
+ val =3D vcpu_get_gr(vcpu, inst.M35.r2);
+ vcpu_set_psr_l(vcpu, val);
+}
+
+void kvm_mov_from_psr(VCPU *vcpu, INST64 inst)
+{
+ unsigned long val;
+
+ val =3D vcpu_get_psr(vcpu);
+ val =3D (val & MASK(0, 32)) | (val & MASK(35, 2));
+ vcpu_set_gr(vcpu, inst.M33.r1, val, 0);
+}
+
+void vcpu_increment_iip(VCPU *vcpu)
+{
+ REGS *regs =3D vcpu_regs(vcpu);
+ ia64_psr *ipsr =3D (ia64_psr *)®s->cr_ipsr;
+ if (ipsr->ri =3D=3D 2) {
+ ipsr->ri =3D 0;
+ regs->cr_iip +=3D 16;
+ } else
+ ipsr->ri++;
+}
+
+void vcpu_decrement_iip(VCPU *vcpu)
+{
+ REGS *regs =3D vcpu_regs(vcpu);
+ ia64_psr *ipsr =3D (ia64_psr *)®s->cr_ipsr;
+
+ if (ipsr->ri =3D=3D 0) {
+ ipsr->ri =3D 2;
+ regs->cr_iip -=3D 16;
+ } else
+ ipsr->ri--;
+}
+
+/** Emulate a privileged operation.
+ *
+ *
+ * @param vcpu virtual cpu
+ * @cause the reason cause virtualization fault
+ * @opcode the instruction code which cause virtualization fault
+ */
+
+void kvm_emulate(VCPU *vcpu, REGS *regs)
+{
+ unsigned long status, cause, opcode ;
+ INST64 inst;
+
+ status =3D IA64_NO_FAULT;
+ cause =3D VMX(vcpu, cause);
+ opcode =3D VMX(vcpu, opcode);
+ inst.inst =3D opcode;
+ /*
+ * Switch to actual virtual rid in rr0 and rr4,
+ * which is required by some tlb related instructions.
+ */
+ prepare_if_physical_mode(vcpu);
+
+ switch (cause) {
+ case EVENT_RSM:
+ kvm_rsm(vcpu, inst);
+ break;
+ case EVENT_SSM:
+ kvm_ssm(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_PSR:
+ kvm_mov_to_psr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_PSR:
+ kvm_mov_from_psr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_CR:
+ kvm_mov_from_cr(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_CR:
+ kvm_mov_to_cr(vcpu, inst);
+ break;
+ case EVENT_BSW_0:
+ vcpu_bsw0(vcpu);
+ break;
+ case EVENT_BSW_1:
+ vcpu_bsw1(vcpu);
+ break;
+ case EVENT_COVER:
+ vcpu_cover(vcpu);
+ break;
+ case EVENT_RFI:
+ vcpu_rfi(vcpu);
+ break;
+ case EVENT_ITR_D:
+ kvm_itr_d(vcpu, inst);
+ break;
+ case EVENT_ITR_I:
+ kvm_itr_i(vcpu, inst);
+ break;
+ case EVENT_PTR_D:
+ kvm_ptr_d(vcpu, inst);
+ break;
+ case EVENT_PTR_I:
+ kvm_ptr_i(vcpu, inst);
+ break;
+ case EVENT_ITC_D:
+ kvm_itc_d(vcpu, inst);
+ break;
+ case EVENT_ITC_I:
+ kvm_itc_i(vcpu, inst);
+ break;
+ case EVENT_PTC_L:
+ kvm_ptc_l(vcpu, inst);
+ break;
+ case EVENT_PTC_G:
+ kvm_ptc_g(vcpu, inst);
+ break;
+ case EVENT_PTC_GA:
+ kvm_ptc_ga(vcpu, inst);
+ break;
+ case EVENT_PTC_E:
+ kvm_ptc_e(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_RR:
+ kvm_mov_to_rr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_RR:
+ kvm_mov_from_rr(vcpu, inst);
+ break;
+ case EVENT_THASH:
+ kvm_thash(vcpu, inst);
+ break;
+ case EVENT_TTAG:
+ kvm_ttag(vcpu, inst);
+ break;
+ case EVENT_TPA:
+ status =3D kvm_tpa(vcpu, inst);
+ break;
+ case EVENT_TAK:
+ kvm_tak(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_AR_IMM:
+ kvm_mov_to_ar_imm(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_AR:
+ kvm_mov_to_ar_reg(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_AR:
+ kvm_mov_from_ar_reg(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_DBR:
+ kvm_mov_to_dbr(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_IBR:
+ kvm_mov_to_ibr(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_PMC:
+ kvm_mov_to_pmc(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_PMD:
+ kvm_mov_to_pmd(vcpu, inst);
+ break;
+ case EVENT_MOV_TO_PKR:
+ kvm_mov_to_pkr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_DBR:
+ kvm_mov_from_dbr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_IBR:
+ kvm_mov_from_ibr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_PMC:
+ kvm_mov_from_pmc(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_PKR:
+ kvm_mov_from_pkr(vcpu, inst);
+ break;
+ case EVENT_MOV_FROM_CPUID:
+ kvm_mov_from_cpuid(vcpu, inst);
+ break;
+ case EVENT_VMSW:
+ status =3D IA64_FAULT;
+ break;
+ default:
+ break;
+ };
+ /*Assume all status is NO_FAULT ?*/
+ if (status =3D=3D IA64_NO_FAULT && cause !=3D EVENT_RFI)
+ vcpu_increment_iip(vcpu);
+
+ recover_if_physical_mode(vcpu);
+}
+
+void init_vcpu(VCPU *vcpu)
+{
+ int i;
+ VCPU *v;
+ long itc_offset;
+
+ vcpu->arch.mode_flags =3D GUEST_IN_PHY;
+ VMX(vcpu, vrr[0]) =3D 0x38;
+ VMX(vcpu, vrr[1]) =3D 0x38;
+ VMX(vcpu, vrr[2]) =3D 0x38;
+ VMX(vcpu, vrr[3]) =3D 0x38;
+ VMX(vcpu, vrr[4]) =3D 0x38;
+ VMX(vcpu, vrr[5]) =3D 0x38;
+ VMX(vcpu, vrr[6]) =3D 0x38;
+ VMX(vcpu, vrr[7]) =3D 0x38;
+ VCPU(vcpu, vpsr) =3D IA64_PSR_BN;
+ VCPU(vcpu, dcr) =3D 0;
+ /* pta.size must not be 0. The minimum is 15 (32k) */
+ VCPU(vcpu, pta) =3D 15 << 2;
+ if (vcpu->vcpu_id =3D=3D 0) {
+ itc_offset =3D 0UL - ia64_get_itc();
+ for (i =3D 0; i < MAX_VCPU_NUM; i++) {
+ v =3D (VCPU *)((char *)vcpu + VCPU_SIZE * i);
+ VMX(v, itc_offset) =3D itc_offset;
+ VMX(v, last_itc) =3D 0;
+ }
+ }
+ VCPU(vcpu, itv) =3D 0x10000;
+ VCPU(vcpu, itm) =3D 0;
+ VMX(vcpu, last_itc) =3D 0;
+
+ VCPU(vcpu, lid) =3D VCPU_LID(vcpu);
+ VCPU(vcpu, ivr) =3D 0;
+ VCPU(vcpu, tpr) =3D 0x10000;
+ VCPU(vcpu, eoi) =3D 0;
+ VCPU(vcpu, irr[0]) =3D 0;
+ VCPU(vcpu, irr[1]) =3D 0;
+ VCPU(vcpu, irr[2]) =3D 0;
+ VCPU(vcpu, irr[3]) =3D 0;
+ VCPU(vcpu, pmv) =3D 0x10000;
+ VCPU(vcpu, cmcv) =3D 0x10000;
+ VCPU(vcpu, lrr0) =3D 0x10000; /* default reset value? */
+ VCPU(vcpu, lrr1) =3D 0x10000; /* default reset value? */
+ update_vhpi(vcpu, NULL_VECTOR);
+ VLSAPIC_XTP(vcpu) =3D 0x80; /* disabled */
+
+ for (i =3D 0; i < 4; i++)
+ VLSAPIC_INSVC(vcpu, i) =3D 0;
+}
+
+void kvm_init_all_rr(VCPU *vcpu)
+{
+ unsigned long psr;
+
+ local_irq_save(psr);
+
+ /* WARNING: not allow co-exist of both virtual mode and physical
+ * mode in same region
+ */
+
+ vcpu->arch.metaphysical_saved_rr0 =3D vrrtomrr(VMX(vcpu,
vrr[VRN0]));
+ vcpu->arch.metaphysical_saved_rr4 =3D vrrtomrr(VMX(vcpu,
vrr[VRN4]));
+
+ if (is_physical_mode(vcpu)) {
+ if (vcpu->arch.mode_flags & GUEST_PHY_EMUL)
+ panic_vm(vcpu);
+
+ ia64_set_rr((VRN0 << VRN_SHIFT),
vcpu->arch.metaphysical_rr0);
+ ia64_dv_serialize_data();
+ ia64_set_rr((VRN4 << VRN_SHIFT),
vcpu->arch.metaphysical_rr4);
+ ia64_dv_serialize_data();
+ } else {
+ ia64_set_rr((VRN0 << VRN_SHIFT),
+ vcpu->arch.metaphysical_saved_rr0);
+ ia64_dv_serialize_data();
+ ia64_set_rr((VRN4 << VRN_SHIFT),
+ vcpu->arch.metaphysical_saved_rr4);
+ ia64_dv_serialize_data();
+ }
+ ia64_set_rr((VRN1 << VRN_SHIFT),
+ vrrtomrr(VMX(vcpu, vrr[VRN1])));
+ ia64_dv_serialize_data();
+ ia64_set_rr((VRN2 << VRN_SHIFT),
+ vrrtomrr(VMX(vcpu, vrr[VRN2])));
+ ia64_dv_serialize_data();
+ ia64_set_rr((VRN3 << VRN_SHIFT),
+ vrrtomrr(VMX(vcpu, vrr[VRN3])));
+ ia64_dv_serialize_data();
+ ia64_set_rr((VRN5 << VRN_SHIFT),
+ vrrtomrr(VMX(vcpu, vrr[VRN5])));
+ ia64_dv_serialize_data();
+ ia64_set_rr((VRN7 << VRN_SHIFT),
+ vrrtomrr(VMX(vcpu, vrr[VRN7])));
+ ia64_dv_serialize_data();
+ ia64_srlz_d();
+ ia64_set_psr(psr);
+ ia64_srlz_i();
+}
+
+int vmm_entry(void)
+{
+ VCPU *v;
+ v =3D current_vcpu;
+
+ ia64_call_vsa(PAL_VPS_RESTORE, (unsigned long)v->arch.vpd,
+ 0, 0, 0, 0, 0, 0);
+ kvm_init_vtlb(v);
+ kvm_init_vhpt(v);
+ init_vcpu(v);
+ kvm_init_all_rr(v);
+ vmm_reset_entry();
+
+ return 0;
+}
+
+void panic_vm(VCPU *v)
+{
+ struct exit_ctl_data *p =3D &v->arch.exit_data;
+
+ p->exit_reason =3D EXIT_REASON_VM_PANIC;
+ vmm_transition(v);
+ /*Never to return*/
+ while (1);
+}
+
+
--=20
1.5.1
|
