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From: Avi K. <av...@qu...> - 2008-05-02 09:38:38
|
Jerone Young wrote: > This patch removes static x86 entries and makes things work for multiple archs. > > Applied, thanks, -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain. |
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:49:18
|
Interrupt polarity should have no functional effect, since qemu tracks logical
IRQ state, not the electrical state of physical lines.
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
--- a/qemu/hw/ppc4xx_devs.c
+++ b/qemu/hw/ppc4xx_devs.c
@@ -377,10 +377,7 @@ static void ppcuic_set_irq (void *opaque
if (irq_num < 0 || irq_num > 31)
return;
sr = uic->uicsr;
- if (!(uic->uicpr & mask)) {
- /* Negatively asserted IRQ */
- level = level == 0 ? 1 : 0;
- }
+
/* Update status register */
if (uic->uictr & mask) {
/* Edge sensitive interrupt */
@@ -479,7 +476,6 @@ static void dcr_write_uic (void *opaque,
break;
case DCR_UICPR:
uic->uicpr = val;
- ppcuic_trigger_irq(uic);
break;
case DCR_UICTR:
uic->uictr = val;
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:44:13
|
On Wednesday 30 April 2008 15:16:09 Avi Kivity wrote: > > hack = $(call _hack,$T/$(strip $1)) > > + > > +ifneq '$(filter $(ARCH_DIR), x86)' '' > > +HACK_FILES = kvm_main.c \ > > + mmu.c \ > > + vmx.c \ > > + svm.c \ > > + x86.c \ > > + irq.h > > +endif > > > > > > hack-files-x86 = ... > hack-files-ppc = ... > > hack-files = $(hack-files-$(ARCH_DIR)) Agreed; this is exactly what I had suggested previously. -- Hollis Blanchard IBM Linux Technology Center |
|
From: Jerone Y. <jy...@us...> - 2008-04-30 21:16:55
|
On Wed, 2008-04-30 at 16:14 -0500, Hollis Blanchard wrote:
> On Wednesday 30 April 2008 15:53:47 Jerone Young wrote:
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> > configure | 2 +-
> >
> >
> > This fixes compilation for cross compilers as many do not create a
> ${cross_prefix}cc link. But the do a ${cross_prefix}gcc. This is what the
> kernel does so this will work for everyone. This breaks some who do not have
> a cc link (cross tools does not create), when I put a patch to remove libkvm
> dependence on test config.mak.
The explanation came out awful :-) . But yes the issue is that by
default cross tools does not create a ${cross_prefix}cc symlink. So you
have to say gcc.
> >
> > Signed-off-by: Jerone Young <jy...@us...>
> >
> > diff --git a/configure b/configure
> > --- a/configure
> > +++ b/configure
> > @@ -2,7 +2,7 @@
> >
> > prefix=/usr/local
> > kerneldir=/lib/modules/$(uname -r)/build
> > -cc=cc
> > +cc=gcc
> > ld=ld
> > objcopy=objcopy
> > want_module=1
>
> To clarify: there is no such thing as "${cross_prefix}cc", so the configure
> script is currently broken for cross-compiling.
>
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:14:47
|
On Wednesday 30 April 2008 15:53:47 Jerone Young wrote:
> 1 file changed, 1 insertion(+), 1 deletion(-)
> configure | 2 +-
>
>
> This fixes compilation for cross compilers as many do not create a
${cross_prefix}cc link. But the do a ${cross_prefix}gcc. This is what the
kernel does so this will work for everyone. This breaks some who do not have
a cc link (cross tools does not create), when I put a patch to remove libkvm
dependence on test config.mak.
>
> Signed-off-by: Jerone Young <jy...@us...>
>
> diff --git a/configure b/configure
> --- a/configure
> +++ b/configure
> @@ -2,7 +2,7 @@
>
> prefix=/usr/local
> kerneldir=/lib/modules/$(uname -r)/build
> -cc=cc
> +cc=gcc
> ld=ld
> objcopy=objcopy
> want_module=1
To clarify: there is no such thing as "${cross_prefix}cc", so the configure
script is currently broken for cross-compiling.
--
Hollis Blanchard
IBM Linux Technology Center
|
|
From: Jerone Y. <jy...@us...> - 2008-04-30 21:11:55
|
1 file changed, 23 insertions(+), 13 deletions(-)
kernel/Makefile | 36 +++++++++++++++++++++++-------------
This patch removes static x86 entries and makes things work for multiple archs.
Signed-off-by: Jerone Young <jy...@us...>
diff --git a/kernel/Makefile b/kernel/Makefile
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -1,4 +1,7 @@ include ../config.mak
include ../config.mak
+
+ARCH_DIR=$(if $(filter $(ARCH),x86_64 i386),x86,$(ARCH))
+ARCH_CONFIG=$(shell echo $(ARCH_DIR)|tr '[:lower:]' '[:upper:]')
KVERREL = $(patsubst /lib/modules/%/build,%,$(KERNELDIR))
@@ -18,10 +21,19 @@ _hack = mv $1 $1.orig && \
| sed '/\#include/! s/\blapic\b/l_apic/g' > $1 && rm $1.orig
unifdef = mv $1 $1.orig && \
- unifdef -DCONFIG_X86 $1.orig > $1; \
+ unifdef -DCONFIG_$(ARCH_CONFIG) $1.orig > $1; \
[ $$? -le 1 ] && rm $1.orig
hack = $(call _hack,$T/$(strip $1))
+
+hack-files-x86 = kvm_main.c \
+ mmu.c \
+ vmx.c \
+ svm.c \
+ x86.c \
+ irq.h
+
+hack-files = $(hack-files-$(ARCH_DIR))
all::
# include header priority 1) $LINUX 2) $KERNELDIR 3) include-compat
@@ -49,21 +61,19 @@ header-sync:
rm -rf $T
rm -f include/asm
- ln -sf asm-x86 include/asm
- ln -sf asm-x86 include-compat/asm
+ ln -sf asm-$(ARCH_DIR) include/asm
+ ln -sf asm-$(ARCH_DIR) include-compat/asm
source-sync:
rm -rf $T
rsync --exclude='*.mod.c' -R \
- "$(LINUX)"/arch/x86/kvm/./*.[ch] \
- "$(LINUX)"/virt/kvm/./*.[ch] \
- $T/
- $(call hack, kvm_main.c)
- $(call hack, mmu.c)
- $(call hack, vmx.c)
- $(call hack, svm.c)
- $(call hack, x86.c)
- $(call hack, irq.h)
+ "$(LINUX)"/arch/$(ARCH_DIR)/kvm/./*.[ch] \
+ "$(LINUX)"/virt/kvm/./*.[ch] \
+ $T/
+
+ for i in $(hack-files); \
+ do $(call hack, $$i); done
+
for i in $$(find $T -type f -printf '%P '); \
do cmp -s $$i $T/$$i || cp $T/$$i $$i; done
rm -rf $T
@@ -72,7 +82,7 @@ install:
mkdir -p $(DESTDIR)/$(INSTALLDIR)
cp *.ko $(DESTDIR)/$(INSTALLDIR)
for i in $(ORIGMODDIR)/drivers/kvm/*.ko \
- $(ORIGMODDIR)/arch/x86/kvm/*.ko; do \
+ $(ORIGMODDIR)/arch/$(ARCH_DIR)/kvm/*.ko; do \
if [ -f "$$i" ]; then mv "$$i" "$$i.orig"; fi; \
done
/sbin/depmod -a
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:05:40
|
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/libkvm/libkvm-powerpc.c b/libkvm/libkvm-powerpc.c
--- a/libkvm/libkvm-powerpc.c
+++ b/libkvm/libkvm-powerpc.c
@@ -25,6 +25,7 @@
#include "kvm-powerpc.h"
#include <errno.h>
#include <stdio.h>
+#include <inttypes.h>
int handle_dcr(struct kvm_run *run, kvm_context_t kvm, int vcpu)
{
@@ -70,12 +71,16 @@ void kvm_show_regs(kvm_context_t kvm, in
return;
fprintf(stderr,"guest vcpu #%d\n", vcpu);
- fprintf(stderr,"pc: %08x msr: %08x\n", regs.pc, regs.msr);
- fprintf(stderr,"lr: %08x ctr: %08x\n", regs.lr, regs.ctr);
- fprintf(stderr,"srr0: %08x srr1: %08x\n", regs.srr0, regs.srr1);
+ fprintf(stderr,"pc: %016"PRIx64" msr: %016"PRIx64"\n",
+ regs.pc, regs.msr);
+ fprintf(stderr,"lr: %016"PRIx64" ctr: %016"PRIx64"\n",
+ regs.lr, regs.ctr);
+ fprintf(stderr,"srr0: %016"PRIx64" srr1: %016"PRIx64"\n",
+ regs.srr0, regs.srr1);
for (i=0; i<32; i+=4)
{
- fprintf(stderr, "gpr%02d: %08x %08x %08x %08x\n", i,
+ fprintf(stderr, "gpr%02d: %016"PRIx64" %016"PRIx64" %016"PRIx64
+ " %016"PRIx64"\n", i,
regs.gpr[i],
regs.gpr[i+1],
regs.gpr[i+2],
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:04:32
|
Avi, please apply these patches to the kvm-userspace repository. I've submitted the device emulation patches (UIC and PCI) to qemu-devel, but have received no response. Thinking ahead to qemu integration, many of these should be folded into a single "Bamboo board" patch, but e.g. the device emulation patches are logically separate. Do you track qemu patches for upstream integration like you do for the kernel? Do you want me to keep these split-out patches locally? Unsplitting them later would be a pain... -Hollis |
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/hw/ppc4xx.h b/qemu/hw/ppc4xx.h
--- a/qemu/hw/ppc4xx.h
+++ b/qemu/hw/ppc4xx.h
@@ -2,6 +2,9 @@
* QEMU PowerPC 4xx emulation shared definitions
*
* Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Copyright 2008 IBM Corp.
+ * Authors: Hollis Blanchard <ho...@us...>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -46,4 +49,41 @@ qemu_irq *ppcuic_init (CPUState *env, qe
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
+
+struct pci_master_map {
+ uint32_t la;
+ uint32_t ma;
+ uint32_t pcila;
+ uint32_t pciha;
+};
+
+struct pci_target_map {
+ uint32_t ms;
+ uint32_t la;
+ uint32_t bar;
+};
+
+#define PPC44x_PCI_NR_PMMS 3
+#define PPC44x_PCI_NR_PTMS 2
+
+struct ppc4xx_pci_t {
+ target_phys_addr_t config_space;
+ target_phys_addr_t registers;
+ struct pci_master_map pmm[PPC44x_PCI_NR_PMMS];
+ struct pci_target_map ptm[PPC44x_PCI_NR_PTMS];
+
+ unsigned int pmm_offset_flags;
+ qemu_irq *pic;
+
+ uint32_t pcic0_cfgaddr;
+ PCIBus *bus;
+};
+typedef struct ppc4xx_pci_t ppc4xx_pci_t;
+
+ppc4xx_pci_t *ppc4xx_pci_init(CPUState *env, qemu_irq *pic,
+ target_phys_addr_t config_space,
+ target_phys_addr_t int_ack,
+ target_phys_addr_t special_cycle,
+ target_phys_addr_t registers);
+
#endif /* !defined(PPC_4XX_H) */
diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
--- a/qemu/hw/ppc4xx_devs.c
+++ b/qemu/hw/ppc4xx_devs.c
@@ -2,6 +2,9 @@
* QEMU PowerPC 4xx embedded processors shared devices emulation
*
* Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Copyright 2008 IBM Corp.
+ * Authors: Hollis Blanchard <ho...@us...>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -25,6 +28,8 @@
#include "ppc.h"
#include "ppc4xx.h"
#include "sysemu.h"
+#include "pci.h"
+#include "bswap.h"
extern int loglevel;
extern FILE *logfile;
@@ -535,3 +540,369 @@ qemu_irq *ppcuic_init (CPUState *env, qe
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
+
+
+
+
+#define PCIC0_CFGADDR 0x0
+#define PCIC0_CFGDATA 0x4
+
+#define PCIL0_PMM0LA 0x0
+#define PCIL0_PMM0MA 0x4
+#define PCIL0_PMM0PCILA 0x8
+#define PCIL0_PMM0PCIHA 0xc
+#define PCIL0_PMM1LA 0x10
+#define PCIL0_PMM1MA 0x14
+#define PCIL0_PMM1PCILA 0x18
+#define PCIL0_PMM1PCIHA 0x1c
+#define PCIL0_PMM2LA 0x20
+#define PCIL0_PMM2MA 0x24
+#define PCIL0_PMM2PCILA 0x28
+#define PCIL0_PMM2PCIHA 0x2c
+#define PCIL0_PTM1MS 0x30
+#define PCIL0_PTM1LA 0x34
+#define PCIL0_PTM2MS 0x38
+#define PCIL0_PTM2LA 0x3c
+#define PCI_REG_SIZE 0x40
+
+#define PPC44x_PCI_MA_MASK 0xfffff000
+#define PPC44x_PCI_MA_ENABLE 0x1
+
+
+static uint32_t pci4xx_cfgaddr_read4(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ return cpu_to_le32(ppc4xx_pci->pcic0_cfgaddr);
+}
+
+static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
+ &pci4xx_cfgaddr_read4,
+ &pci4xx_cfgaddr_read4,
+ &pci4xx_cfgaddr_read4,
+};
+
+static void pci4xx_cfgaddr_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+
+ value = le32_to_cpu(value);
+
+ ppc4xx_pci->pcic0_cfgaddr = value & ~0x3;
+}
+
+static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
+ &pci4xx_cfgaddr_write4,
+ &pci4xx_cfgaddr_write4,
+ &pci4xx_cfgaddr_write4,
+};
+
+static uint32_t pci4xx_cfgdata_read1(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+ uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
+ uint32_t value;
+
+ if (!(cfgaddr & (1<<31)))
+ return 0xffffffff;
+
+ value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 1);
+
+ return value;
+}
+
+static uint32_t pci4xx_cfgdata_read2(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+ uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
+ uint32_t value;
+
+ if (!(cfgaddr & (1<<31)))
+ return 0xffffffff;
+
+ value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 2);
+
+ return cpu_to_le16(value);
+}
+
+static uint32_t pci4xx_cfgdata_read4(void *opaque, target_phys_addr_t addr)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+ uint32_t cfgaddr = ppc4xx_pci->pcic0_cfgaddr;
+ uint32_t value;
+
+ if (!(cfgaddr & (1<<31)))
+ return 0xffffffff;
+
+ value = pci_data_read(ppc4xx_pci->bus, cfgaddr | offset, 4);
+
+ return cpu_to_le32(value);
+}
+
+static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
+ &pci4xx_cfgdata_read1,
+ &pci4xx_cfgdata_read2,
+ &pci4xx_cfgdata_read4,
+};
+
+static void pci4xx_cfgdata_write1(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+
+ pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
+ value, 1);
+}
+
+static void pci4xx_cfgdata_write2(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+
+ value = le16_to_cpu(value);
+
+ pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
+ value, 2);
+}
+
+static void pci4xx_cfgdata_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ ppc4xx_pci_t *ppc4xx_pci = opaque;
+ int offset = addr & 0x3;
+
+ value = le32_to_cpu(value);
+
+ pci_data_write(ppc4xx_pci->bus, ppc4xx_pci->pcic0_cfgaddr | offset,
+ value, 4);
+}
+
+static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
+ &pci4xx_cfgdata_write1,
+ &pci4xx_cfgdata_write2,
+ &pci4xx_cfgdata_write4,
+};
+
+static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ struct ppc4xx_pci_t *pci = opaque;
+ unsigned long offset = addr - pci->registers;
+
+ value = le32_to_cpu(value);
+
+ switch (offset) {
+ case PCIL0_PMM0LA:
+ pci->pmm[0].la = value;
+ break;
+ case PCIL0_PMM1LA:
+ pci->pmm[0].la = value;
+ break;
+ case PCIL0_PMM2LA:
+ pci->pmm[0].la = value;
+ break;
+ default:
+ //printf(" unhandled PCI internal register 0x%lx\n", offset);
+ break;
+ }
+}
+
+static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
+{
+ struct ppc4xx_pci_t *pci = opaque;
+ unsigned long offset = addr - pci->registers;
+ uint32_t value;
+
+ switch (offset) {
+ case PCIL0_PMM0LA:
+ value = pci->pmm[0].la;
+ break;
+ case PCIL0_PMM0MA:
+ value = pci->pmm[0].ma;
+ break;
+ case PCIL0_PMM0PCIHA:
+ value = pci->pmm[0].pciha;
+ break;
+ case PCIL0_PMM0PCILA:
+ value = pci->pmm[0].pcila;
+ break;
+
+ case PCIL0_PMM1LA:
+ value = pci->pmm[1].la;
+ break;
+ case PCIL0_PMM1MA:
+ value = pci->pmm[1].ma;
+ break;
+ case PCIL0_PMM1PCIHA:
+ value = pci->pmm[1].pciha;
+ break;
+ case PCIL0_PMM1PCILA:
+ value = pci->pmm[1].pcila;
+ break;
+
+ case PCIL0_PMM2LA:
+ value = pci->pmm[2].la;
+ break;
+ case PCIL0_PMM2MA:
+ value = pci->pmm[2].ma;
+ break;
+ case PCIL0_PMM2PCIHA:
+ value = pci->pmm[2].pciha;
+ break;
+ case PCIL0_PMM2PCILA:
+ value = pci->pmm[2].pcila;
+ break;
+
+ case PCIL0_PTM1MS:
+ value = pci->ptm[0].ms;
+ break;
+ case PCIL0_PTM1LA:
+ value = pci->ptm[0].la;
+ break;
+ case PCIL0_PTM2MS:
+ value = pci->ptm[1].ms;
+ break;
+ case PCIL0_PTM2LA:
+ value = pci->ptm[1].la;
+ break;
+
+ default:
+ //printf(" read from invalid PCI internal register 0x%lx\n", offset);
+ value = 0;
+ }
+
+ value = cpu_to_le32(value);
+
+ return value;
+}
+
+static CPUReadMemoryFunc *pci_reg_read[] = {
+ &pci_reg_read4,
+ &pci_reg_read4,
+ &pci_reg_read4,
+};
+
+static CPUWriteMemoryFunc *pci_reg_write[] = {
+ &pci_reg_write4,
+ &pci_reg_write4,
+ &pci_reg_write4,
+};
+
+static uint32_t pci_int_ack_read4(void *opaque, target_phys_addr_t addr)
+{
+ printf("%s\n", __func__);
+ return 0;
+}
+
+static CPUReadMemoryFunc *pci_int_ack_read[] = {
+ &pci_int_ack_read4,
+ &pci_int_ack_read4,
+ &pci_int_ack_read4,
+};
+
+static void pci_special_write4(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+ printf("%s\n", __func__);
+}
+
+static CPUWriteMemoryFunc *pci_special_write[] = {
+ &pci_special_write4,
+ &pci_special_write4,
+ &pci_special_write4,
+};
+
+static int bamboo_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+{
+ int slot = pci_dev->devfn >> 3;
+
+#if 0
+ printf("### %s: devfn %x irq %d -> %d\n", __func__,
+ pci_dev->devfn, irq_num, slot+1);
+#endif
+
+ /* All pins from each slot are tied to a single board IRQ (2-5) */
+ return slot + 1;
+}
+
+static void bamboo_pci_set_irq(qemu_irq *pic, int irq_num, int level)
+{
+#if 0
+ printf("### %s: PCI irq %d, UIC irq %d\n", __func__, irq_num, 30 - irq_num);
+#endif
+
+ /* Board IRQs 2-5 are connected to UIC IRQs 28-25 */
+ qemu_set_irq(pic[30-irq_num], level);
+}
+
+/* XXX Needs some abstracting for boards other than Bamboo. */
+ppc4xx_pci_t *ppc4xx_pci_init(CPUState *env, qemu_irq *pic,
+ target_phys_addr_t config_space,
+ target_phys_addr_t int_ack,
+ target_phys_addr_t special_cycle,
+ target_phys_addr_t registers)
+{
+ ppc4xx_pci_t *pci;
+ PCIDevice *d;
+ int index;
+
+ pci = qemu_mallocz(sizeof(ppc4xx_pci_t));
+ if (!pci)
+ return NULL;
+
+ pci->config_space = config_space;
+ pci->registers = registers;
+ pci->pic = pic;
+
+ pci->bus = pci_register_bus(bamboo_pci_set_irq, bamboo_pci_map_irq,
+ pic, 0, 4);
+ d = pci_register_device(pci->bus, "host bridge", sizeof(PCIDevice),
+ 0, NULL, NULL);
+ d->config[0x00] = 0x14; // vendor_id
+ d->config[0x01] = 0x10;
+ d->config[0x02] = 0x7f; // device_id
+ d->config[0x03] = 0x02;
+ d->config[0x0a] = 0x80; // class_sub = other bridge type
+ d->config[0x0b] = 0x06; // class_base = PCI_bridge
+
+ /* CFGADDR */
+ index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
+ pci4xx_cfgaddr_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(config_space, 4, index);
+
+ /* CFGDATA */
+ index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
+ pci4xx_cfgdata_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(config_space + 4, 4, index);
+
+ /* "Special cycle" and interrupt acknowledge */
+ index = cpu_register_io_memory(0, pci_int_ack_read,
+ pci_special_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(int_ack, 4, index);
+
+ /* Internal registers */
+ index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, pci);
+ if (index < 0)
+ goto free;
+ cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
+
+ /* XXX register_savevm() */
+
+ return pci;
+
+free:
+ printf("%s error\n", __func__);
+ qemu_free(pci);
+ return NULL;
+}
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
This is especially useful when debugging the UIC emulation.
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/hw/ppc405_uc.c b/qemu/hw/ppc405_uc.c
--- a/qemu/hw/ppc405_uc.c
+++ b/qemu/hw/ppc405_uc.c
@@ -2587,13 +2587,13 @@ CPUState *ppc405cr_init (target_phys_add
ppc405_dma_init(env, dma_irqs);
/* Serial ports */
if (serial_hds[0] != NULL) {
- ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
+ ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
}
if (serial_hds[1] != NULL) {
- ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
+ ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
}
/* IIC controller */
- ppc405_i2c_init(env, mmio, 0x500, pic[29]);
+ ppc405_i2c_init(env, mmio, 0x500, pic[2]);
/* GPIO */
ppc405_gpio_init(env, mmio, 0x700);
/* CPU control */
@@ -2930,49 +2930,50 @@ CPUState *ppc405ep_init (target_phys_add
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
+ /* XXX 405EP has no ECC interrupt */
+ ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
offset = 0;
for (i = 0; i < 2; i++)
offset += ram_sizes[i];
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
- dma_irqs[0] = pic[26];
- dma_irqs[1] = pic[25];
- dma_irqs[2] = pic[24];
- dma_irqs[3] = pic[23];
+ dma_irqs[0] = pic[5];
+ dma_irqs[1] = pic[6];
+ dma_irqs[2] = pic[7];
+ dma_irqs[3] = pic[8];
ppc405_dma_init(env, dma_irqs);
/* IIC controller */
- ppc405_i2c_init(env, mmio, 0x500, pic[29]);
+ ppc405_i2c_init(env, mmio, 0x500, pic[2]);
/* GPIO */
ppc405_gpio_init(env, mmio, 0x700);
/* Serial ports */
if (serial_hds[0] != NULL) {
- ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
+ ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
}
if (serial_hds[1] != NULL) {
- ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
+ ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
}
/* OCM */
ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
offset += 4096;
/* GPT */
- gpt_irqs[0] = pic[12];
- gpt_irqs[1] = pic[11];
- gpt_irqs[2] = pic[10];
- gpt_irqs[3] = pic[9];
- gpt_irqs[4] = pic[8];
+ gpt_irqs[0] = pic[19];
+ gpt_irqs[1] = pic[20];
+ gpt_irqs[2] = pic[21];
+ gpt_irqs[3] = pic[22];
+ gpt_irqs[4] = pic[23];
ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
/* PCI */
- /* Uses pic[28], pic[15], pic[13] */
+ /* Uses pic[3], pic[16], pic[18] */
/* MAL */
- mal_irqs[0] = pic[20];
- mal_irqs[1] = pic[19];
- mal_irqs[2] = pic[18];
- mal_irqs[3] = pic[17];
+ mal_irqs[0] = pic[11];
+ mal_irqs[1] = pic[12];
+ mal_irqs[2] = pic[13];
+ mal_irqs[3] = pic[14];
ppc405_mal_init(env, mal_irqs);
/* Ethernet */
- /* Uses pic[22], pic[16], pic[14] */
+ /* Uses pic[9], pic[15], pic[17] */
/* CPU control */
ppc405ep_cpc_init(env, clk_setup, sysclk);
*offsetp = offset;
diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
--- a/qemu/hw/ppc4xx_devs.c
+++ b/qemu/hw/ppc4xx_devs.c
@@ -365,7 +365,7 @@ static void ppcuic_set_irq (void *opaque
uint32_t mask, sr;
uic = opaque;
- mask = 1 << irq_num;
+ mask = 1 << (31-irq_num);
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/hw/ppc440.c b/qemu/hw/ppc440.c
--- a/qemu/hw/ppc440.c
+++ b/qemu/hw/ppc440.c
@@ -8,17 +8,32 @@
*
*/
+
+#include "hw.h"
+#include "hw/isa.h"
#include "ppc440.h"
+
+#define PPC440EP_PCI_CONFIG 0xeec00000
+#define PPC440EP_PCI_INTACK 0xeed00000
+#define PPC440EP_PCI_SPECIAL 0xeed00000
+#define PPC440EP_PCI_REGS 0xef400000
+#define PPC440EP_PCI_IO 0xe8000000
+#define PPC440EP_PCI_IOLEN 0x10000
+#define PPC440EP_PCI_MEM 0xa0000000
+#define PPC440EP_PCI_MEMLEN 0x20000000
+
void ppc440ep_init(CPUState *env,
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
qemu_irq **picp,
+ ppc4xx_pci_t **pcip,
int do_init)
{
ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
ram_addr_t offset;
+ ppc4xx_pci_t *pci;
int i;
ppc_dcr_init(env, NULL, NULL);
@@ -45,6 +60,18 @@ void ppc440ep_init(CPUState *env,
for (i = 0; i < 2; i++)
offset += ram_sizes[i];
+ /* PCI */
+ pci = ppc4xx_pci_init(env, pic,
+ PPC440EP_PCI_CONFIG,
+ PPC440EP_PCI_INTACK,
+ PPC440EP_PCI_SPECIAL,
+ PPC440EP_PCI_REGS);
+ if (!pci)
+ printf("couldn't create PCI controller!\n");
+ *pcip = pci;
+
+ isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
+
/* serial ports on page 126 of 440EP user manual */
if (serial_hds[0]) {
printf("Initializing first serial port\n");
diff --git a/qemu/hw/ppc440.h b/qemu/hw/ppc440.h
--- a/qemu/hw/ppc440.h
+++ b/qemu/hw/ppc440.h
@@ -24,6 +24,7 @@ void ppc440ep_init(CPUState *env,
target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
qemu_irq **picp,
+ ppc4xx_pci_t **pcip,
int do_init);
#endif
diff --git a/qemu/hw/ppc440_bamboo.c b/qemu/hw/ppc440_bamboo.c
--- a/qemu/hw/ppc440_bamboo.c
+++ b/qemu/hw/ppc440_bamboo.c
@@ -9,6 +9,11 @@
*/
#include "config.h"
+#include "qemu-common.h"
+#include "net.h"
+#include "hw.h"
+#include "pci.h"
+#include "sysemu.h"
#include "ppc440.h"
#include "qemu-kvm.h"
#include "device_tree.h"
@@ -26,7 +31,9 @@ void bamboo_init(ram_addr_t ram_size, in
{
char *buf=NULL;
target_phys_addr_t ram_bases[4], ram_sizes[4];
+ NICInfo *nd;
qemu_irq *pic;
+ ppc4xx_pci_t *pci;
CPUState *env;
target_ulong ep=0;
target_ulong la=0;
@@ -77,7 +84,7 @@ void bamboo_init(ram_addr_t ram_size, in
/* call init */
printf("Calling function ppc440_init\n");
- ppc440ep_init(env, ram_bases, ram_sizes, &pic,1);
+ ppc440ep_init(env, ram_bases, ram_sizes, &pic, &pci, 1);
printf("Done calling ppc440_init\n");
/* Register mem */
@@ -168,6 +175,25 @@ void bamboo_init(ram_addr_t ram_size, in
env->nip = ep;
}
+ if (pci) {
+ int unit_id = 0;
+
+ /* Add virtio block devices. */
+ while ((i = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
+ virtio_blk_init(pci->bus, 0x1AF4, 0x1001,
+ drives_table[i].bdrv);
+ unit_id++;
+ }
+
+ /* Register network interfaces. */
+ for (i = 0; i < nb_nics; i++) {
+ nd = &nd_table[i];
+ if (!nd->model)
+ nd->model = "virtio";
+ pci_nic_init(pci->bus, nd, -1);
+ }
+ }
+
printf("%s: DONE\n", __func__);
}
diff --git a/qemu/pc-bios/bamboo.dtb b/qemu/pc-bios/bamboo.dtb
index e02fa8e0bf23b992b04fe87dfce37d4cc08777a6..81f971c64745aaf79152e1ed6f09e5d36137e461
GIT binary patch
literal 3163
zc$~FX&1)Su5TA8kuu~k{DW#-IN?&kGdU%UBiJkbAJX(q`Js48Rp@ddXEAJE8uWI)>
zwjtosYcBZ*LLirr{sTD`(@UYJT>Tfcm&DLh3nf(2O1raqn-2;Rh}CaqH1nI$>f_nT
zm(Ky_zXgDGfcKut@8`0gl6~pr^Iwhtyhl>L57W&v-(#}(%y<UjMPsAzyzFO5Lg`>c
zl2MiclArI8tN8;n-y<<61uL-bsuSzF87rAb^GVUc&4V^KFt)>>ZMz|57B48?o7o*E
zHoqLKt_ELiwry`Xac+L{`|(YLBk%6c5aB)9`v~82@B@H-?C)oUReNg2v$Fq|l9F$;
zR{TSg=ZvjI!jeqv);4P1h9jFtdBBP4qv!IpWI{~x(x+KkiY$(qK(+c%tsNgFg9)d;
ztPRV-pvFeEKM=ovQN8A52*u~XgvD!xb6RX;ZxPySe`vm%a}f$_yI}cAnc+7TdjZ#q
z=F@Yf>{WB;@!UKfS^Z~ru9Ts=7!=iL)ydP=y=(udVIS#k&i?h|Hzr?_G=BOhXOf`k
z1_x_V?&h(C^9U1S_2;ZFDMOwNn)0KMgA3MAme=+8)cTP!<j0_>Ms6+K{c3UF)S_<t
zraNQHO>vqve(L%i`)Bw>`D7zH#Z$@<PlKWwx%GSBS-01%BaV&v9fxM$dIb}l#6z}q
zB?vADfsLp4Zl%Nd!TGefcx7!Zz_J@h-|OFIu8HeiGP0TnJU&3!y9VB`7=MjwW_f~B
z$3sB>4(7f3zj^mMc=uk<yIJp7@%B1+*Y^d#L@Ux)gP`pTHl%Lq|KP3j&Y-A9PChDq
z_}~rvW&oXGHJ|l&!DsGm_{?HHEFsk2OE|Asg@%=~SO4~gQu+F_*dnyKk1kk#THg?~
zFlrz;98W6TK3}PfP6OTCnn)d9e|NvR_l31p{bOj(YR%AB&g^k*97A&k-!fyxLEo7#
z4zxlS^~Ezi?z!Wmp&k#-+;w$+%^1fIoo^qShm~!A+JRSdIj5H83+Qh94d*3QI)J}j
z6Qz@K?<YeYw_fF6DVDl)XDi+5F5Q_**YDDORO!%tJI)H0)_kPiyT2mqz9KJ!m5xIY
z%{{S9!cefH@F|Pq0+tKD$ILj%LKXwfl3c!zMlpks3O^@;r6p8e1M|HIA=~DZeOK=0
z3<QgS#u>fsZwdCpgr#&BN}jNhe0(Ai_bH)c=Epo`z6uNBl*HP!)D@6in%9(ugi@7A
z!pd<Lf^;(38RTP<hLU>M6AV<Ea=(RaN6%Nhmyw|^f*@%mpUkzmfNd_y35m5iod{J9
ozsMO2Q4mw5T=0a*7oxiAT}OUGa@mX9ZIR(!lwmeee#$ZY2cfvR=Kufz
diff --git a/qemu/pc-bios/bamboo.dts b/qemu/pc-bios/bamboo.dts
--- a/qemu/pc-bios/bamboo.dts
+++ b/qemu/pc-bios/bamboo.dts
@@ -187,6 +187,45 @@
};
+ PCI0: pci@ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
+ primary;
+ reg = <0 eec00000 8 /* Config space access */
+ 0 eed00000 4 /* IACK */
+ 0 eed00000 4 /* Special cycle */
+ 0 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 a0000000 0 a0000000 0 20000000
+ 01000000 0 00000000 0 e8000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* Bamboo has all 4 IRQ pins tied together per slot */
+ interrupt-map-mask = <f800 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 0 &UIC0 1c 8
+
+ /* IDSEL 2 */
+ 1000 0 0 0 &UIC0 1b 8
+
+ /* IDSEL 3 */
+ 1800 0 0 0 &UIC0 1a 8
+
+ /* IDSEL 4 */
+ 2000 0 0 0 &UIC0 19 8
+ >;
+ };
+
};
chosen {
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
/home/hollisb/source/kvm-userspace-ppc.hg/qemu/target-ppc/helper_regs.h: In function `hreg_store_msr': /home/hollisb/source/kvm-userspace-ppc.hg/qemu/target-ppc/helper_regs.h:102: warning: implicit declaration of function `tlb_flush' Signed-off-by: Hollis Blanchard <ho...@us...> diff --git a/qemu/qemu-kvm-powerpc.c b/qemu/qemu-kvm-powerpc.c --- a/qemu/qemu-kvm-powerpc.c +++ b/qemu/qemu-kvm-powerpc.c @@ -19,6 +19,7 @@ #include "hw/hw.h" #include "sysemu.h" #include "cpu.h" +#include "exec-all.h" #include "helper_regs.h" #include "qemu-kvm.h" |
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/hw/ppc440.c b/qemu/hw/ppc440.c
--- a/qemu/hw/ppc440.c
+++ b/qemu/hw/ppc440.c
@@ -39,6 +39,7 @@ void ppc440ep_init(CPUState *env,
/* SDRAM controller */
printf("trying to setup sdram controller\n");
+ /* XXX 440EP's ECC interrupts are on UIC1 */
ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
offset = 0;
for (i = 0; i < 2; i++)
@@ -47,10 +48,10 @@ void ppc440ep_init(CPUState *env,
/* serial ports on page 126 of 440EP user manual */
if (serial_hds[0]) {
printf("Initializing first serial port\n");
- ppc405_serial_init(env, mmio,0x300, pic[31], serial_hds[0]);
+ ppc405_serial_init(env, mmio,0x300, pic[0], serial_hds[0]);
}
if (serial_hds[1]) {
printf("Initializing 2nd serial port\n");
- ppc405_serial_init(env, mmio,0x400, pic[30], serial_hds[1]);
+ ppc405_serial_init(env, mmio,0x400, pic[1], serial_hds[1]);
}
}
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
In addition to env->interrupt_request, PowerPC qemu tracks device interrupts in
env->irq_input_state. As long as irq_input_state is set, interrupt_request will
not be updated. Since we clear CPU_INTERRUPT_HARD, and it's never re-enabled,
we end up delivering only one interrupt.
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/qemu-kvm-powerpc.c b/qemu/qemu-kvm-powerpc.c
--- a/qemu/qemu-kvm-powerpc.c
+++ b/qemu/qemu-kvm-powerpc.c
@@ -168,11 +168,11 @@ int kvm_arch_try_push_interrupts(void *o
int r;
unsigned irq;
+ /* PowerPC Qemu tracks the various core input pins (interrupt, critical
+ * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
if (env->ready_for_interrupt_injection &&
- (env->interrupt_request & CPU_INTERRUPT_HARD))
+ (env->irq_input_state & (1<<PPC40x_INPUT_INT)))
{
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
-
/* For now KVM disregards the 'irq' argument. However, in the
* future KVM could cache it in-kernel to avoid a heavyweight exit
* when reading the UIC.
@@ -184,7 +184,10 @@ int kvm_arch_try_push_interrupts(void *o
printf("cpu %d fail inject %x\n", env->cpu_index, irq);
}
- return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
+ /* We don't know if there are more interrupts pending after this. However,
+ * the guest will return to userspace in the course of handling this one
+ * anyways, so we will get a chance to deliver the rest. */
+ return 0;
}
void kvm_arch_update_regs_for_sipi(CPUState *env)
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:55
|
This fixes the following race condition:
1. target handles an interrupt and begins to EOI
2. device raises an interrupt, setting UIC SR
3. target finishes EOI by clearing SR bit
On hardware, a device with a level-triggered interrupt would instantly
re-assert SR after step 3, so we need to do the same.
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
--- a/qemu/hw/ppc4xx_devs.c
+++ b/qemu/hw/ppc4xx_devs.c
@@ -278,6 +278,7 @@ struct ppcuic_t {
struct ppcuic_t {
uint32_t dcr_base;
int use_vectors;
+ uint32_t level; /* Remembers the state of level-triggered interrupts. */
uint32_t uicsr; /* Status register */
uint32_t uicer; /* Enable register */
uint32_t uiccr; /* Critical register */
@@ -385,10 +386,13 @@ static void ppcuic_set_irq (void *opaque
uic->uicsr |= mask;
} else {
/* Level sensitive interrupt */
- if (level == 1)
+ if (level == 1) {
uic->uicsr |= mask;
- else
+ uic->level |= mask;
+ } else {
uic->uicsr &= ~mask;
+ uic->level &= ~mask;
+ }
}
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
@@ -460,6 +464,7 @@ static void dcr_write_uic (void *opaque,
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
+ uic->uicsr |= uic->level;
ppcuic_trigger_irq(uic);
break;
case DCR_UICSRS:
|
|
From: Hollis B. <ho...@us...> - 2008-04-30 21:03:44
|
This patch adds a print to notify of failed reads and rights.
Signed-off-by: Jerone Young <jy...@us...>
Signed-off-by: Hollis Blanchard <ho...@us...>
diff --git a/qemu/qemu-kvm-powerpc.c b/qemu/qemu-kvm-powerpc.c
--- a/qemu/qemu-kvm-powerpc.c
+++ b/qemu/qemu-kvm-powerpc.c
@@ -199,13 +199,17 @@ int handle_powerpc_dcr_read(int vcpu, ui
int handle_powerpc_dcr_read(int vcpu, uint32_t dcrn, uint32_t *data)
{
CPUState *env = cpu_single_env;
- ppc_dcr_read(env->dcr_env, dcrn, data);
+ if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
+ fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
+
return 0; /* XXX ignore failed DCR ops */
}
int handle_powerpc_dcr_write(int vcpu, uint32_t dcrn, uint32_t data)
{
CPUState *env = cpu_single_env;
- ppc_dcr_write(env->dcr_env, dcrn, data);
+ if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
+ fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
+
return 0; /* XXX ignore failed DCR ops */
}
|
|
From: Jerone Y. <jy...@us...> - 2008-04-30 20:57:26
|
1 file changed, 1 insertion(+), 1 deletion(-)
configure | 2 +-
This fixes compilation for cross compilers as many do not create a ${cross_prefix}cc link. But the do a ${cross_prefix}gcc. This is what the kernel does so this will work for everyone. This breaks some who do not have a cc link (cross tools does not create), when I put a patch to remove libkvm dependence on test config.mak.
Signed-off-by: Jerone Young <jy...@us...>
diff --git a/configure b/configure
--- a/configure
+++ b/configure
@@ -2,7 +2,7 @@
prefix=/usr/local
kerneldir=/lib/modules/$(uname -r)/build
-cc=cc
+cc=gcc
ld=ld
objcopy=objcopy
want_module=1
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From: Avi K. <av...@qu...> - 2008-04-30 20:23:12
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Jerone Young wrote:
> 1 file changed, 1 deletion(-)
> qemu/hw/ppc440_bamboo.c | 1 -
>
>
> In 2.6.26 wait is now enabled by default. With this the /hypervisor node will not be need to be idetified to enable the guest to go into wait state while idle.
>
> Signed-off-by: Jerone Young <jy...@us...>
>
> diff --git a/qemu/hw/ppc440_bamboo.c b/qemu/hw/ppc440_bamboo.c
> --- a/qemu/hw/ppc440_bamboo.c
> +++ b/qemu/hw/ppc440_bamboo.c
> @@ -163,7 +163,6 @@ void bamboo_init(ram_addr_t ram_size, in
> dt_cell(fdt, "/chosen", "linux,initrd-end",
> (initrd_base + initrd_size));
> dt_string(fdt, "/chosen", "bootargs", (char *)kernel_cmdline);
> - dt_node(fdt, "/", "hypervisor");
> #endif
>
> if (kvm_enabled()) {
>
I don't have this bit in my tree.
--
Any sufficiently difficult bug is indistinguishable from a feature.
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From: Avi K. <av...@qu...> - 2008-04-30 20:18:04
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Jerone Young wrote: > This patch removes static x86 entries and makes things work for multiple archs. > > Signed-off-by: Jerone Young <jy...@us...> > > diff --git a/kernel/Makefile b/kernel/Makefile > --- a/kernel/Makefile > +++ b/kernel/Makefile > @@ -1,5 +1,10 @@ include ../config.mak > include ../config.mak > > +ARCH_DIR=$(ARCH) > +ifneq '$(filter $(ARCH_DIR), x86_64 i386)' '' > + ARCH_DIR=x86 > +endif > + > Let's be consistent with functions and directives: ARCH_DIR=$(if $(filter $(ARCH),x86_64 i386),x86,$(ARCH)) > KVERREL = $(patsubst /lib/modules/%/build,%,$(KERNELDIR)) > > DESTDIR= > @@ -18,10 +23,19 @@ _hack = mv $1 $1.orig && \ > | sed '/\#include/! s/\blapic\b/l_apic/g' > $1 && rm $1.orig > > unifdef = mv $1 $1.orig && \ > - unifdef -DCONFIG_X86 $1.orig > $1; \ > + unifdef -DCONFIG_$(shell echo $(ARCH_DIR)|tr '[:lower:]' '[:upper:]') $1.orig > $1; \ > [ $$? -le 1 ] && rm $1.orig > My eyes hurt. A new variable please (and assign with := to avoid the shell being called too often). > > hack = $(call _hack,$T/$(strip $1)) > + > +ifneq '$(filter $(ARCH_DIR), x86)' '' > +HACK_FILES = kvm_main.c \ > + mmu.c \ > + vmx.c \ > + svm.c \ > + x86.c \ > + irq.h > +endif > > hack-files-x86 = ... hack-files-ppc = ... hack-files = $(hack-files-$(ARCH_DIR)) (yeah, someone else is now gauging their eyes out) -- Any sufficiently difficult bug is indistinguishable from a feature. |
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From: Avi K. <av...@qu...> - 2008-04-30 13:39:55
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Hollis Blanchard wrote: > Acked-by: Hollis Blanchard <ho...@us...> > > Avi, please apply for 2.6.26. > > Sure thing. Thanks. -- Any sufficiently difficult bug is indistinguishable from a feature. |
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From: Avi K. <av...@qu...> - 2008-04-30 13:02:11
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In about a week, the various kvm lists will move to vger.kenel.org. This will improve responsiveness, and reduce spam and advertising. Please subscribe to the lists you are interested in as soon as possible. You can subscribe by sending an email to maj...@vg..., with the following lines in the body: subscribe kvm subscribe kvm-commits subscribe kvm-ia64 subscribe kvm-ppc Of course, omit lines for the lists you are not interested in. Majordomo will then send further instructions. Thanks to the vger admins for hosting the kvm lists. -- Any sufficiently difficult bug is indistinguishable from a feature. |
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From: Avi K. <av...@qu...> - 2008-04-30 12:57:11
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David Miller wrote: > I've created (and tested) all of these lists. > > Thanks. I about a week I'll make the sourceforge lists read-only. -- Any sufficiently difficult bug is indistinguishable from a feature. |
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From: David M. <da...@da...> - 2008-04-30 03:14:48
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From: Avi Kivity <av...@qu...> Date: Wed, 30 Apr 2008 00:46:13 +0300 > I sent an email a couple of days ago to pos...@vg...: > > > Hi, please create the following lists for kvm: > > > > kvm (x86 and general discussion) > > kvm-ppc (powerpc, managed by Hollis Blanchard) > > kvm-ia64 (ia64) > > kvm-commits (read-only, tracks commits to kvm git HEAD) > > > > Thanks. I've created (and tested) all of these lists. |
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From: Avi K. <av...@qu...> - 2008-04-29 21:47:43
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David Miller wrote: > Should I create the list(s) now? If so, please let me know the > names they should have. > I sent an email a couple of days ago to pos...@vg...: > Hi, please create the following lists for kvm: > > kvm (x86 and general discussion) > kvm-ppc (powerpc, managed by Hollis Blanchard) > kvm-ia64 (ia64) > kvm-commits (read-only, tracks commits to kvm git HEAD) > > Thanks. Thanks. -- Any sufficiently difficult bug is indistinguishable from a feature. |
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From: Hollis B. <ho...@us...> - 2008-04-29 21:18:28
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Acked-by: Hollis Blanchard <ho...@us...> Avi, please apply for 2.6.26. -- Hollis Blanchard IBM Linux Technology Center |
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