From: santiago g. <san...@gm...> - 2009-09-16 08:58:07
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I't looks to me that logic update rate (then gpsim processors) is actually 1e6, then 1 MHz.. is this correct? What is the actual behaivor of logic update rates? i think the qtimer is at 1KHz, but the loops inside every call aren't sinchonized... i mean: logic updates are done 1e6 times/Sec, but not at 1us steps... isn't it?, not sure about this. Looks to me that logic updates are done 1000 times/ms, but may be that all 1000 updates could be done in the firsts 100 us, for example. Is this right? What is the upper limit to logic updatre rate?, tried with 5e6 with a pic simulation and looks unstable. I don't know if this is a bug or what: When i add a clock input to the circuit at 1Hz i have a 0.25 Hz signal... is this a problem of the clock input component, or the timming, or is my PC? Do you also have 0.25 Hz? The extrange thing for me is that at 5e6 i still have a 0.25 Hz signal in the clock input, but if i run the pic then it goes faster but irregular... |
From: Zoltan P. <zol...@gm...> - 2009-09-16 10:49:45
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Yes. the logic update is done as you've written. What do you mean by unstable? Ktechlab crashes or just outputs garbage? Also I don't understand how to reproduce the problem. Set the logic update timer to 5e6 and then? Maybe Alan knows: how is the time in simulation managed? We should provide the some ways to know what is the current time in the simulation, and how much time has passed since the last step (for reactive elements). 2009/9/16 santiago gonzalez <san...@gm...> > I't looks to me that logic update rate (then gpsim processors) is actually > 1e6, then 1 MHz.. is this correct? > > What is the actual behaivor of logic update rates? > i think the qtimer is at 1KHz, but the loops inside every call aren't > sinchonized... i mean: logic updates are done 1e6 times/Sec, but not at 1us > steps... isn't it?, not sure about this. > > Looks to me that logic updates are done 1000 times/ms, but may be that all > 1000 updates could be done in the firsts 100 us, for example. Is this right? > > What is the upper limit to logic updatre rate?, tried with 5e6 with a pic > simulation and looks unstable. > > I don't know if this is a bug or what: > When i add a clock input to the circuit at 1Hz i have a 0.25 Hz signal... > is this a problem of the clock input component, or the timming, or is my PC? > Do you also have 0.25 Hz? > > The extrange thing for me is that at 5e6 i still have a 0.25 Hz signal in > the clock input, but if i run the pic then it goes faster but irregular... > > > > > ------------------------------------------------------------------------------ > Come build with us! The BlackBerry® Developer Conference in SF, CA > is the only developer event you need to attend this year. Jumpstart your > developing skills, take BlackBerry mobile applications to market and stay > ahead of the curve. Join us from November 9-12, 2009. Register now! > http://p.sf.net/sfu/devconf > _______________________________________________ > Ktechlab-devel mailing list > Kte...@li... > https://lists.sourceforge.net/lists/listinfo/ktechlab-devel > > |
From: santiago g. <san...@gm...> - 2009-09-16 13:58:38
|
2009/9/16 Zoltan Padrah <zol...@gm...> > Yes. the logic update is done as you've written. > > What do you mean by unstable? Ktechlab crashes or just outputs garbage? > Unstable perhaps is not the proper word... i mean irregular periods, i tried with a simple toggle led pic program at 1 Hz. Logic update at 5e6 is 5 Mhz; Then a pic program at 20 MHz (5MHz instruction cicle) should go real-time. Running simulation i have a 1Hz blinking led in ktl, but sometimes go faster, sometimes slower; anyway is a good aproach, it can run a pic at 20 MHz real-time, not very accurate, but it can. I added an input clock singal component to the circuit... it goes at 0.25 Hz, even when is configured at 1 Hz, no matter if i use update logic 1e6 or 5e6, it goes at 0.25 Hz. But when i run the pic the clock singal go faster... here you can see a mini-video: http://arcachofo.users.sourceforge.net/miweb/ktl1 I just try to understand how this work. And i'm not sure about why the input signal does not go at 1 Hz, if it's a problem in the component or a problem in my ktl build. > Also I don't understand how to reproduce the problem. Set the logic update > timer to 5e6 and then? > I think you can't reproduce the problem bcos with the actual gpsimprocessor pic simulations goes very slow. I didn't want to send you a path and send another in some days with some other changes; if you want i send you the actual changes i have made, but i think you should wait a time for some other changes and testing to include it in official release (if accepted). > > Maybe Alan knows: how is the time in simulation managed? We should provide > the some ways to know what is the current time in the simulation, and how > much time has passed since the last step (for reactive elements). > > I think this could be a good thing. I need some time to undertand the gpsim interface (if i finally can..), but i think is possible to do a first aproach to real-time simulating pics in the easy way: -The gpsimprossesors should be updated at 5e6, may be inside logic update: a 5x loop (to not update all the logic at 5e6) . Every gpsimprocessor should have a counter and update depending on it's clock speed. This way only 4, 8, 12, 16, 20 MHz speeds will be accurate, but this is just a first aproach. -An editable propertie should be added to the pic component: clock MHz (no idea about how to do this) this integer value is used to set the counter value in simulator.cpp (if someday is possible to use gpsim in real-time mode this value could be used) 2009/9/16 santiago gonzalez <san...@gm...> > >> I't looks to me that logic update rate (then gpsim processors) is actually >> 1e6, then 1 MHz.. is this correct? >> >> What is the actual behaivor of logic update rates? >> i think the qtimer is at 1KHz, but the loops inside every call aren't >> sinchonized... i mean: logic updates are done 1e6 times/Sec, but not at 1us >> steps... isn't it?, not sure about this. >> >> Looks to me that logic updates are done 1000 times/ms, but may be that all >> 1000 updates could be done in the firsts 100 us, for example. Is this right? >> >> What is the upper limit to logic updatre rate?, tried with 5e6 with a pic >> simulation and looks unstable. >> >> I don't know if this is a bug or what: >> When i add a clock input to the circuit at 1Hz i have a 0.25 Hz signal... >> is this a problem of the clock input component, or the timming, or is my PC? >> Do you also have 0.25 Hz? >> >> The extrange thing for me is that at 5e6 i still have a 0.25 Hz signal in >> the clock input, but if i run the pic then it goes faster but irregular... >> >> >> >> >> ------------------------------------------------------------------------------ >> Come build with us! The BlackBerry® Developer Conference in SF, CA >> is the only developer event you need to attend this year. Jumpstart your >> developing skills, take BlackBerry mobile applications to market and stay >> ahead of the curve. Join us from November 9-12, 2009. Register >> now! >> http://p.sf.net/sfu/devconf >> _______________________________________________ >> Ktechlab-devel mailing list >> Kte...@li... >> https://lists.sourceforge.net/lists/listinfo/ktechlab-devel >> >> > > > ------------------------------------------------------------------------------ > Come build with us! The BlackBerry® Developer Conference in SF, CA > is the only developer event you need to attend this year. Jumpstart your > developing skills, take BlackBerry mobile applications to market and stay > ahead of the curve. Join us from November 9-12, 2009. Register now! > http://p.sf.net/sfu/devconf > _______________________________________________ > Ktechlab-devel mailing list > Kte...@li... > https://lists.sourceforge.net/lists/listinfo/ktechlab-devel > > |
From: Alan G. <ag...@sp...> - 2009-09-16 15:44:09
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> Maybe Alan knows: how is the time in simulation managed? Not really... The code was a real mess. The current preferred method is Simulator::time(). This will read the current linear element clock for you. There is kindof a problem though because if a subcircuit has analog elements it will always operate on the linear clock even if it also has logic elements in it. -- I think. I've been trying to plow through the code in logic.h. my biggest headaches right now: LogicOut::logicPinList LogicOut::m_pNextChanged, and LogicIn::m_pNextLogic. There is a lot of messed up crap going on that needs to be re-designed. over the past few days I did clear out much of the easy stuff, but the HARD stuff remains. =\ -- New president: Here we go again... Chemistry.com: A total rip-off. Powers are not rights. |