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[Krobot-commits] [SCM] krobot branch, master, updated. dd7c5daac4fc87ee81874bfca82f20efde0a8f92
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From: Nicolas D. <Ba...@us...> - 2011-04-04 22:06:12
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- Log -----------------------------------------------------------------
commit dd7c5daac4fc87ee81874bfca82f20efde0a8f92
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Tue Apr 5 00:05:29 2011 +0200
[krobot_message] Implement the Battery monitoring messages.
commit 7c91035c86358a5eafefe5df31fe77313cee59e8
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Tue Apr 5 00:03:52 2011 +0200
[USB_CAN] Add the battery monitoring logic to the USB CAN converter
This patch enables battery monitoring on the USB-CAN converter.
Corrseponding CAN packets are sent to the PC and to the CAN bus.
commit 949acd815853f6f4a495c9a9f229635e726e7444
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Tue Apr 5 00:00:44 2011 +0200
[USB_CAN] Group the converter logic in one directory.
commit f7da3fccd16605b78cebeabb28ab0562fc3b96c8
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Mon Apr 4 23:57:16 2011 +0200
[USB_CAN] Upgrade BeRTOS
-----------------------------------------------------------------------
Changes:
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_adc.h b/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_adc.h
index df2587b..62ee6ed 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_adc.h
+++ b/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_adc.h
@@ -109,4 +109,41 @@
*/
#define CONFIG_ADC_STROBE 0
+
+/**
+ * Start up timer[s] = startup value / ADCClock [Hz]
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3_adc_sut"
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_SUT ADC_SUT512
+
+/**
+ * Analog Settling Time[s] = settling value / ADCClock[Hz]
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3_adc_stt"
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_STTLING ADC_AST17
+
+/**
+ * Tracking Time[s] = (TRACKTIM + 1) / ADCClock[Hz]
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_TRACKTIM 0
+
+/**
+ * Transfer Period[s] = (TRANSFER * 2 + 3) ADCClock[Hz]
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_TRANSFER 1
+
#endif /* CFG_ADC_H */
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_dac.h b/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_dac.h
new file mode 100644
index 0000000..1ae1e98
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_dac.h
@@ -0,0 +1,88 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ * All Rights Reserved.
+ * -->
+ *
+ * \brief Configuration file for DAC module.
+ *
+ *
+ * \author Daniele Basile <as...@de...>
+ */
+
+#ifndef CFG_DAC_H
+#define CFG_DAC_H
+
+/**
+ * Module logging level.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_level"
+ */
+#define DAC_LOG_LEVEL LOG_LVL_WARN
+
+/**
+ * Module logging format.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_format"
+ */
+#define DAC_LOG_FORMAT LOG_FMT_TERSE
+
+/**
+ * DAC Refresh Period = 1024*REFRESH/DACC Clock
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "sam3x"
+ * $WIZ$ min = 0
+ * $WIZ$ max = 65536
+ */
+#define CONFIG_DAC_REFRESH 16
+
+/**
+ * DAC Startup Time Selection.
+ * see datasheet table.
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "sam3x"
+ * $WIZ$ min = 0
+ * $WIZ$ max = 63
+ */
+#define CONFIG_DAC_STARTUP 0
+
+/**
+ * DAC Trigger Selection.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3x_dac_tc"
+ * $WIZ$ supports = "sam3x"
+ */
+#define CONFIG_DAC_TIMER DACC_TRGSEL_TIO_CH0
+
+#endif /* CFG_DAC_H */
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_lwip.h b/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_lwip.h
index b6b55f6..73acb91 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_lwip.h
+++ b/elec/boards/USB_CAN/Firmware/bertos/cfg/cfg_lwip.h
@@ -1206,6 +1206,13 @@
* $WIZ$ type = "boolean"
*/
#define LWIP_SOCKET 1
+#if LWIP_SOCKET
+ /*
+ * The sockets.c file requires this macro to be defined to really
+ * set errno on errors.
+ */
+ #define ERRNO
+#endif
/**
* Enable BSD-style sockets functions names.
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/adc_sam3.c b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/adc_sam3.c
new file mode 100644
index 0000000..303689f
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/adc_sam3.c
@@ -0,0 +1,157 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief ADC hardware-specific implementation
+ *
+ * \author Daniele Basile <as...@de...>
+ */
+
+
+#include "adc_sam3.h"
+
+#include "cfg/cfg_adc.h"
+
+#include <cfg/macros.h>
+#include <cfg/compiler.h>
+
+// Define log settings for cfg/log.h.
+#define LOG_LEVEL ADC_LOG_LEVEL
+#define LOG_FORMAT ADC_LOG_FORMAT
+#include <cfg/log.h>
+
+#include <drv/adc.h>
+#include <drv/irq_cm3.h>
+
+#include <cpu/irq.h>
+
+#include <mware/event.h>
+
+#include <io/cm3.h>
+
+
+/* We use event to signal the end of conversion */
+static Event data_ready;
+/* The last converted data */
+static uint32_t data;
+
+/**
+ * ADC ISR.
+ *
+ * The interrupt is connected to ready data, so when the
+ * adc ends the conversion we generate an event and then
+ * we return the converted value.
+ *
+ * \note to clear the Ready data bit and End of conversion
+ * bit we should read the Last Converted Data register, otherwise
+ * the ready data interrupt loop on this call.
+ */
+static DECLARE_ISR(adc_conversion_end_irq)
+{
+ data = 0;
+ if (ADC_ISR & BV(ADC_DRDY))
+ {
+ data = ADC_LDATA;
+ event_do(&data_ready);
+ }
+}
+
+/**
+ * Select mux channel \a ch.
+ */
+void adc_hw_select_ch(uint8_t ch)
+{
+ /* Disable all channels */
+ ADC_CHDR = ADC_CH_MASK;
+ /* Enable select channel */
+ ADC_CHER = BV(ch);
+}
+
+/**
+ * Start an ADC convertion.
+ */
+uint16_t adc_hw_read(void)
+{
+ ADC_CR = BV(ADC_START);
+ event_wait(&data_ready);
+ return(data);
+}
+
+/**
+ * Init ADC hardware.
+ */
+void adc_hw_init(void)
+{
+ /* Make sure that interrupt are enabled */
+ IRQ_ASSERT_ENABLED();
+
+ /* Initialize the dataready event */
+ event_initGeneric(&data_ready);
+
+ /* Clock ADC peripheral */
+ pmc_periphEnable(ADC_ID);
+
+ /* Reset adc controller */
+ ADC_CR = ADC_SWRST;
+
+ /*
+ * Set adc mode register:
+ * - Disable hardware trigger and enable software trigger.
+ * - Select normal mode.
+ */
+ ADC_MR = 0;
+
+ /* Set ADC_BITS bit convertion resolution. */
+ #if ADC_BITS == 12
+ ADC_MR &= ~BV(ADC_LOWRES);
+ #elif ADC_BITS == 10
+ ADC_MR |= BV(ADC_LOWRES);
+ #else
+ #error No select bit resolution is supported to this CPU
+ #endif
+
+ /* Setup ADC */
+ LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_CLOCK);
+ ADC_MR |= ((ADC_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
+ LOG_INFO("prescaler[%ld]\n", ADC_PRESCALER);
+ ADC_MR |= ((CONFIG_ADC_SUT << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
+ LOG_INFO("starup[%d]\n", CONFIG_ADC_SUT);
+ ADC_MR |= ((CONFIG_ADC_STTLING << ADC_SETTLING_SHIFT) & ADC_SETTLING_MASK);
+ LOG_INFO("sttime[%d]\n", CONFIG_ADC_STTLING);
+ ADC_MR |= ((CONFIG_ADC_TRACKTIM << ADC_TRACKTIM_SHIFT) & ADC_TRACKTIM_MASK);
+ LOG_INFO("tracking[%d]\n", CONFIG_ADC_TRACKTIM);
+ ADC_MR |= ((CONFIG_ADC_TRANSFER << ADC_TRANSFER_SHIFT) & ADC_TRANSFER_MASK);
+ LOG_INFO("tranfer[%d]\n", CONFIG_ADC_TRANSFER);
+
+ /* Register and enable irq for adc. */
+ sysirq_setHandler(INT_ADC, adc_conversion_end_irq);
+ ADC_IER = BV(ADC_DRDY);
+}
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/adc_sam3.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/adc_sam3.h
new file mode 100644
index 0000000..f46f940
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/adc_sam3.h
@@ -0,0 +1,64 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief ADC hardware-specific definition
+ *
+ * \author Daniele Basile <as...@de...>
+ */
+
+#ifndef DRV_ADC_SAM3_H
+#define DRV_ADC_SAM3_H
+
+#include <hw/hw_cpufreq.h>
+
+#include "cfg/cfg_adc.h"
+
+#include <cfg/compiler.h>
+
+/**
+ * ADC config define.
+ */
+#define ADC_MUX_MAXCH 16 //Max number of channel for ADC.
+#define ADC_BITS 12 //Bit resolution for ADC converter.
+
+/**
+ * Macro for computing correct value to write into ADC
+ * register.
+ */
+#define ADC_PRESCALER (DIV_ROUNDUP(CPU_FREQ, 2 * CONFIG_ADC_CLOCK) - 1)
+#define ADC_CLOCK (CPU_FREQ / ((ADC_PRESCALER + 1) * 2))
+
+void adc_hw_select_ch(uint8_t ch);
+uint16_t adc_hw_read(void);
+void adc_hw_init(void);
+
+#endif /* DRV_ADC_SAM3_H */
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_cm3.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_cm3.h
new file mode 100644
index 0000000..3cebff7
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_cm3.h
@@ -0,0 +1,46 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief Low-level DAC module for Cortex-m3.
+ *
+ * \author Daniele Basile <as...@de...>
+ *
+ */
+
+#include <cpu/detect.h>
+
+#if CPU_CM3_SAM3X
+ #include "adc_sam3.h"
+/*#elif Add other ARM families here */
+#else
+ #error Unknown CPU
+#endif
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_sam3.c b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_sam3.c
new file mode 100644
index 0000000..b10ff62
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_sam3.c
@@ -0,0 +1,238 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief DAC hardware-specific implementation
+ *
+ * \author Daniele Basile <as...@de...>
+ */
+
+#include "dac_sam3.h"
+
+#include "cfg/cfg_dac.h"
+
+#include <cfg/macros.h>
+#include <cfg/compiler.h>
+
+// Define log settings for cfg/log.h.
+#define LOG_LEVEL DAC_LOG_LEVEL
+#define LOG_FORMAT DAC_LOG_FORMAT
+#include <cfg/log.h>
+
+#include <drv/dac.h>
+#include <drv/irq_cm3.h>
+
+#include <cpu/types.h>
+
+#include <io/cm3.h>
+
+#include <string.h>
+
+struct DacHardware
+{
+ uint16_t channels;
+ uint32_t rate;
+ bool end;
+};
+
+struct DacHardware dac_hw;
+
+#if CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH0 /* Select Timer counter TIO Channel 0 */
+ #define DAC_TC_ID TC0_ID
+ #define DAC_TC_CCR TC0_CCR0
+ #define DAC_TC_IDR TC0_IDR0
+ #define DAC_TC_CMR TC0_CMR0
+ #define DAC_TC_SR TC0_SR0
+ #define DAC_TC_RA TC0_RA0
+ #define DAC_TC_RC TC0_RC0
+#elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH1 /* Select Timer counter TIO Channel 1 */
+ #define DAC_TC_ID TC1_ID
+ #define DAC_TC_CCR TC0_CCR1
+ #define DAC_TC_IDR TC0_IDR1
+ #define DAC_TC_CMR TC0_CMR1
+ #define DAC_TC_SR TC0_SR1
+ #define DAC_TC_RA TC0_RA1
+ #define DAC_TC_RC TC0_RC1
+#elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH2 /* Select Timer counter TIO Channel 2 */
+ #define DAC_TC_ID TC2_ID
+ #define DAC_TC_CCR TC0_CCR2
+ #define DAC_TC_IDR TC0_IDR2
+ #define DAC_TC_CMR TC0_CMR2
+ #define DAC_TC_SR TC0_SR2
+ #define DAC_TC_RA TC0_RA2
+ #define DAC_TC_RC TC0_RC2
+#elif CONFIG_DAC_TIMER == DACC_TRGSEL_PWM0 || CONFIG_DAC_TIMER == DACC_TRGSEL_PWM1
+ #error unimplemented pwm triger select.
+#endif
+
+INLINE void tc_setup(uint32_t freq, size_t n_sample)
+{
+ pmc_periphEnable(DAC_TC_ID);
+
+ /* Disable TC clock */
+ DAC_TC_CCR = TC_CCR_CLKDIS;
+ /* Disable interrupts */
+ DAC_TC_IDR = 0xFFFFFFFF;
+ /* Clear status register */
+ volatile uint32_t dummy = DAC_TC_SR;
+ (void)dummy;
+
+ /*
+ * Setup the timer counter:
+ * - select clock TCLK1 (MCK/2)
+ * - enable wave form mode
+ * - RA compare effect SET
+ * - RC compare effect CLEAR
+ * - UP mode with automatic trigger on RC Compare
+ */
+ DAC_TC_CMR = TC_TIMER_CLOCK1 | BV(TC_CMR_WAVE) | TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR | BV(TC_CMR_CPCTRG);
+
+ /*
+ * Compute the sample frequency
+ * the RC counter will update every MCK/2 (see above)
+ * so to convert one sample at the user freq we generate
+ * the trigger every TC_CLK / (numer_of_sample * user_freq)
+ * where TC_CLK = MCK / 2.
+ */
+ uint32_t rc = DIV_ROUND((CPU_FREQ / 2), n_sample * freq);
+ DAC_TC_RC = rc;
+ /* generate the square wave with duty = 50% */
+ DAC_TC_RA = DIV_ROUND(50 * rc, 100);
+
+ PIOB_PDR = BV(25);
+ PIO_PERIPH_SEL(PIOB_BASE, BV(25), PIO_PERIPH_B);
+}
+
+INLINE void tc_start(void)
+{
+ DAC_TC_CCR = BV(TC_CCR_CLKEN)| BV(TC_CCR_SWTRG);
+}
+
+INLINE void tc_stop(void)
+{
+ DAC_TC_CCR = BV(TC_CCR_CLKDIS);
+}
+
+static int sam3x_dac_write(struct Dac *dac, unsigned channel, uint16_t sample)
+{
+ (void)dac;
+
+ ASSERT(channel <= DAC_MAXCH);
+
+ DACC_MR |= (channel << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
+ DACC_CHER |= BV(channel);
+
+ DACC_CDR = sample ;
+
+ return 0;
+}
+
+static void sam3x_dac_setCh(struct Dac *dac, uint32_t mask)
+{
+ /* we have only the ch0 and ch1 */
+ ASSERT(mask < BV(3));
+ dac->hw->channels = mask;
+}
+
+static void sam3x_dac_setSampleRate(struct Dac *dac, uint32_t rate)
+{
+ (void)dac;
+
+ /* Eneble hw trigger */
+ DACC_MR |= BV(DACC_TRGEN) | (CONFIG_DAC_TIMER << DACC_TRGSEL_SHIFT);
+ dac->hw->rate = rate;
+}
+
+static void sam3x_dac_conversion(struct Dac *dac, void *buf, size_t len)
+{
+ if (dac->hw->channels & BV(DACC_CH0))
+ DACC_MR |= (DACC_CH0 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
+
+ if (dac->hw->channels & BV(DACC_CH1))
+ DACC_MR |= (DACC_CH1 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
+
+ DACC_CHER |= dac->hw->channels;
+
+ /* setup timer and start it */
+ tc_setup(dac->hw->rate, len);
+ tc_start();
+
+ /* Setup dma and start it */
+ DACC_TPR = (uint32_t)buf ;
+ DACC_TCR = len;
+ DACC_PTCR |= BV(DACC_PTCR_TXTEN);
+}
+
+static bool sam3x_dac_isFinished(struct Dac *dac)
+{
+ (void)dac;
+ return 0;
+}
+
+static void sam3x_dac_start(struct Dac *dac, void *buf, size_t len, size_t slice_len)
+{
+ (void)dac;
+ (void)buf;
+ (void)len;
+ (void)slice_len;
+}
+
+static void sam3x_dac_stop(struct Dac *dac)
+{
+ (void)dac;
+}
+
+
+void dac_init(struct Dac *dac)
+{
+
+ /* Fill the virtual table */
+ dac->ctx.write = sam3x_dac_write;
+ dac->ctx.setCh = sam3x_dac_setCh;
+ dac->ctx.setSampleRate = sam3x_dac_setSampleRate;
+ dac->ctx.conversion = sam3x_dac_conversion;
+ dac->ctx.isFinished = sam3x_dac_isFinished;
+ dac->ctx.start = sam3x_dac_start;
+ dac->ctx.stop = sam3x_dac_stop;
+ dac->ctx._type = DAC_SAM3X;
+ dac->hw = &dac_hw;
+
+ /* Clock DAC peripheral */
+ pmc_periphEnable(DACC_ID);
+
+ /* Reset hw */
+ DACC_CR |= BV(DACC_SWRST);
+ DACC_MR = 0;
+
+ /* Configure the dac */
+ DACC_MR |= (CONFIG_DAC_REFRESH << DACC_REFRESH_SHIFT) & DACC_REFRESH_MASK;
+ DACC_MR |= (CONFIG_DAC_STARTUP << DACC_STARTUP_SHIFT) & DACC_STARTUP_MASK;
+}
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_sam3.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_sam3.h
new file mode 100644
index 0000000..e5d68a2
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/dac_sam3.h
@@ -0,0 +1,51 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
+ *
+ * -->
+ *
+ * \brief DAC hardware-specific definition
+ *
+ * \author Daniele Basile <as...@de...>
+ */
+
+#ifndef DRV_DAC_SAM3_H
+#define DRV_DAC_SAM3_H
+
+#include <drv/dac.h>
+
+/**
+ * DAC config define.
+ */
+#define DAC_MAXCH 2 //Max number of channel for ADC.
+#define DAC_BITS 12 //Bit resolution for ADC converter.
+
+#define DAC_SAM3X MAKE_ID('S', 'D', '3', 'X')
+
+#endif /* DRV_DAC_SAM3_H */
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.c b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.c
index 889a5c1..0247f61 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.c
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.c
@@ -77,7 +77,7 @@
*
* TODO: make this paramater user-configurable from the Wizard.
*/
-const uint8_t mac_addr[] = { 0x00, 0x23, 0x54, 0x6a, 0x77, 0x55 };
+const uint8_t mac_addr[] = { 0x00, 0x45, 0x56, 0x78, 0x9a, 0xbc };
/* Silent Doxygen bug... */
#ifndef __doxygen__
@@ -109,12 +109,9 @@ static DECLARE_ISR(emac_irqHandler)
/* Read interrupt status and disable interrupts. */
uint32_t isr = EMAC_ISR;
- kprintf("irq: %x\n", isr);
-
/* Receiver interrupt */
if ((isr & EMAC_RX_INTS))
{
- kprintf("emac: rx %x\n", isr);
if (isr & BV(EMAC_RCOMP))
event_do(&recv_wait);
EMAC_RSR = EMAC_RX_INTS;
@@ -123,12 +120,7 @@ static DECLARE_ISR(emac_irqHandler)
if (isr & EMAC_TX_INTS)
{
if (isr & BV(EMAC_TCOMP))
- {
- kprintf("emac: tcomp\n");
event_do(&send_wait);
- }
- if (isr & BV(EMAC_RLEX))
- kprintf("emac: rlex\n");
EMAC_TSR = EMAC_TX_INTS;
}
//AIC_EOICR = 0;
@@ -141,11 +133,13 @@ static DECLARE_ISR(emac_irqHandler)
*
* \return Contents of the specified register.
*/
-static uint16_t phy_hw_read(reg8_t reg)
+static uint16_t phy_hw_read(uint8_t phy_addr, reg8_t reg)
{
// PHY read command.
- EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
- | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE;
+ EMAC_MAN = EMAC_SOF | EMAC_RW_READ
+ | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
+ | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
+ | EMAC_CODE;
// Wait until PHY logic completed.
while (!(EMAC_NSR & BV(EMAC_IDLE)))
@@ -155,46 +149,105 @@ static uint16_t phy_hw_read(reg8_t reg)
return (uint16_t)(EMAC_MAN & EMAC_DATA);
}
+#if 0
/*
* \brief Write value to PHY register.
*
* \param reg PHY register number.
* \param val Value to write.
*/
-static void phy_hw_write(reg8_t reg, uint16_t val)
+static void phy_hw_write(uint8_t phy_addr, reg8_t reg, uint16_t val)
{
// PHY write command.
- EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
- | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE | val;
+ EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE
+ | ((phy_addr << EMAC_PHYA_SHIFT) & EMAC_PHYA)
+ | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA)
+ | EMAC_CODE | val;
// Wait until PHY logic completed.
while (!(EMAC_NSR & BV(EMAC_IDLE)))
cpu_relax();
}
+#endif
-static int emac_reset(void)
+/*
+ * Check link speed and duplex as negotiated by the PHY
+ * and configure CPU EMAC accordingly.
+ * Requires active PHY maintenance mode.
+ */
+static void emac_autoNegotiation(void)
{
- uint16_t phy_cr;
+ uint16_t reg;
+ time_t start;
+
+ // Wait for auto-negotation to complete
+ start = timer_clock();
+ do {
+ reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_BMSR);
+ if (timer_clock() - start > 2000)
+ {
+ kprintf("eth error: auto-negotiation timeout\n");
+ return;
+ }
+ }
+ while (!(reg & NIC_PHY_BMSR_ANCOMPL));
+
+ reg = phy_hw_read(NIC_PHY_ADDR, NIC_PHY_ANLPAR);
+
+ if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_TX_HDX))
+ {
+ LOG_INFO("eth: 100BASE-TX\n");
+ EMAC_NCFGR |= BV(EMAC_SPD);
+ }
+ else
+ {
+ LOG_INFO("eth: 10BASE-T\n");
+ EMAC_NCFGR &= ~BV(EMAC_SPD);
+ }
+
+ if ((reg & NIC_PHY_ANLPAR_TX_FDX) || (reg & NIC_PHY_ANLPAR_10_FDX))
+ {
+ LOG_INFO("eth: full duplex\n");
+ EMAC_NCFGR |= BV(EMAC_FD);
+ }
+ else
+ {
+ LOG_INFO("eth: half duplex\n");
+ EMAC_NCFGR &= ~BV(EMAC_FD);
+ }
+}
+
+static int emac_reset(void)
+{
+#if CPU_ARM_AT91
// Enable devices
- //PMC_PCER = BV(PIOA_ID);
- //PMC_PCER = BV(PIOB_ID);
- //PMC_PCER = BV(EMAC_ID);
- // TOOD: Implement in sam7x
- pmc_periphEnable(PIOA_ID);
- pmc_periphEnable(PIOB_ID);
- pmc_periphEnable(EMAC_ID);
+ PMC_PCER = BV(PIOA_ID);
+ PMC_PCER = BV(PIOB_ID);
+ PMC_PCER = BV(EMAC_ID);
- // Disable TESTMODE
+ // Disable TESTMODE and RMII
PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
-#if CPU_ARM_AT91
- // Disable RMII
PIOB_PUDR = BV(PHY_COL_RMII_BIT);
// Disable PHY power down.
PIOB_PER = BV(PHY_PWRDN_BIT);
PIOB_OER = BV(PHY_PWRDN_BIT);
PIOB_CODR = BV(PHY_PWRDN_BIT);
+#else
+ pmc_periphEnable(PIOA_ID);
+ pmc_periphEnable(PIOB_ID);
+ pmc_periphEnable(PIOC_ID);
+ pmc_periphEnable(PIOD_ID);
+ pmc_periphEnable(EMAC_ID);
+
+ // Disable TESTMODE and RMII
+ PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
+
+ // Disable PHY power down.
+ PIOD_PER = BV(PHY_PWRDN_BIT);
+ PIOD_OER = BV(PHY_PWRDN_BIT);
+ PIOD_CODR = BV(PHY_PWRDN_BIT);
#endif
// Toggle external hardware reset pin.
@@ -209,48 +262,30 @@ static int emac_reset(void)
PIOB_ASR = PHY_MII_PINS;
PIOB_BSR = 0;
PIOB_PDR = PHY_MII_PINS;
+
// Enable receive and transmit clocks.
EMAC_USRIO = BV(EMAC_CLKEN);
#else
- PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS, PIO_PERIPH_A);
- PIOB_PDR = PHY_MII_PINS;
+ PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
+ PIOB_PDR = PHY_MII_PINS_PORTB;
+
+ PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
+ PIOC_PDR = PHY_MII_PINS_PORTC;
+
// Enable receive, transmit clocks and RMII mode.
EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
#endif
// Enable management port.
EMAC_NCR |= BV(EMAC_MPE);
- EMAC_NCFGR |= EMAC_CLK_HCLK_32;
+ EMAC_NCFGR |= EMAC_CLK_HCLK_64;
// Set local MAC address.
EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
(mac_addr[1] << 8) | mac_addr[0];
EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
- // Wait for PHY ready
- timer_delay(255);
-
- // Clear MII isolate.
- phy_hw_read(NIC_PHY_BMCR);
- phy_cr = phy_hw_read(NIC_PHY_BMCR);
-
- phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
- phy_hw_write(NIC_PHY_BMCR, phy_cr);
-
- phy_cr = phy_hw_read(NIC_PHY_BMCR);
-
- LOG_INFO("%s: PHY ID %#04x %#04x\n",
- __func__,
- phy_hw_read(NIC_PHY_ID1), phy_hw_read(NIC_PHY_ID2));
-
- // Wait for auto negotiation completed.
- phy_hw_read(NIC_PHY_BMSR);
- for (;;)
- {
- if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
- break;
- cpu_relax();
- }
+ emac_autoNegotiation();
// Disable management port.
EMAC_NCR &= ~BV(EMAC_MPE);
@@ -258,6 +293,7 @@ static int emac_reset(void)
return 0;
}
+
static int emac_start(void)
{
uint32_t addr;
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.h
index f733df9..a756ffc 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.h
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/drv/eth_sam3.h
@@ -42,9 +42,9 @@
// Settings and definition for DAVICOM 9161A
// \{
-#define NIC_PHY_ADDR 31
+#define NIC_PHY_ADDR 0
-//Registry definition
+// Register bits definition
#define NIC_PHY_BMCR 0x00 // Basic mode control register.
#define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
#define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
@@ -61,6 +61,11 @@
#define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
#define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
+#define NIC_PHY_ANLPAR_10_HDX BV(5) // 10BASE-T half duplex
+#define NIC_PHY_ANLPAR_10_FDX BV(6) // 10BASE-T full duplex
+#define NIC_PHY_ANLPAR_TX_HDX BV(7) // 100BASE-TX half duplex
+#define NIC_PHY_ANLPAR_TX_FDX BV(8) // 100BASE-TX full duplex
+
#define NIC_PHY_ID1 0x02 // PHY identifier register 1.
#define NIC_PHY_ID2 0x03 // PHY identifier register 2.
#define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
@@ -74,7 +79,6 @@
* See schematics for AT91SAM7X-EK evalution board.
*/
// All pins in port B
-#define PHY_TXCLK_ISOLATE_BIT 0
#define PHY_REFCLK_XT2_BIT 0
#define PHY_TXEN_BIT 1
#define PHY_TXD0_BIT 2
@@ -123,32 +127,36 @@
* See schematics for SAM3X-EK evalution board.
*/
// Port B
-#define PHY_TXCLK_ISOLATE_BIT 0
#define PHY_REFCLK_XT2_BIT 0
#define PHY_TXEN_BIT 1
#define PHY_TXD0_BIT 2
#define PHY_TXD1_BIT 3
-#define PHY_RXDV_TESTMODE_BIT 4
#define PHY_RXD0_AD0_BIT 5
#define PHY_RXD1_AD1_BIT 6
#define PHY_RXER_RXD4_RPTR_BIT 7
#define PHY_MDC_BIT 8
#define PHY_MDIO_BIT 9
+// Port C
+#define PHY_RXDV_TESTMODE_BIT 10
// Port A
#define PHY_MDINTR_BIT 5
+// Port D -- FIXME: Only on which revision?
+#define PHY_PWRDN_BIT 18
-#define PHY_MII_PINS \
+#define PHY_MII_PINS_PORTB \
BV(PHY_REFCLK_XT2_BIT) \
| BV(PHY_TXEN_BIT) \
| BV(PHY_TXD0_BIT) \
| BV(PHY_TXD1_BIT) \
- | BV(PHY_RXDV_TESTMODE_BIT) \
| BV(PHY_RXD0_AD0_BIT) \
| BV(PHY_RXD1_AD1_BIT) \
| BV(PHY_RXER_RXD4_RPTR_BIT) \
| BV(PHY_MDC_BIT) \
| BV(PHY_MDIO_BIT)
+#define PHY_MII_PINS_PORTC \
+ BV(PHY_RXDV_TESTMODE_BIT)
+
#endif /* CPU_ARM_AT91 */
// \}
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3N4.cdef b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3N4.cdef
index 47f4c70..e13cc3e 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3N4.cdef
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3N4.cdef
@@ -51,7 +51,7 @@ MK_FLASH_SCRIPT = PRG_SCRIPTS_DIR + "arm/flash-sam3.sh"
CPU_DEFAULT_FREQ = "48000000UL"
# Special CPU related tags.
-CPU_TAGS += ["sam3"]
+CPU_TAGS += ["sam3n"]
# Additional hw drivers.
MK_CPU_CSRC += DRV_DIR + "clock_sam3.c "
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3X8.cdef b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3X8.cdef
index dfd9a87..b64fb18 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3X8.cdef
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/info/SAM3X8.cdef
@@ -51,7 +51,7 @@ MK_FLASH_SCRIPT = PRG_SCRIPTS_DIR + "arm/flash-sam3.sh"
CPU_DEFAULT_FREQ = "84000000UL"
# Special CPU related tags.
-CPU_TAGS += ["sam3"]
+CPU_TAGS += [ "sam3", "sam3x" ]
# Additional hw drivers.
MK_CPU_CSRC += DRV_DIR + "clock_sam3.c "
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3.h
index 9437c61..59931f9 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3.h
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3.h
@@ -170,6 +170,8 @@
#include "sam3_emac.h"
#include "sam3_rstc.h"
#include "sam3_adc.h"
+#include "sam3_dacc.h"
+#include "sam3_tc.h"
/**
* U(S)ART I/O pins
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_adc.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_adc.h
index 2545f23..30bac49 100644
--- a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_adc.h
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_adc.h
@@ -34,6 +34,8 @@
*
* SAM3 Analog to Digital Converter.
*
+ * $WIZ$
+ *
*/
@@ -64,12 +66,12 @@
#define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0.
#define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1.
#define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2.
-#define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0.
-#define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1.
+#define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0.
+#define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1.
#define ADC_LOWRES 4 ///< Resolution 0: 12-bit, 1: 10-bit.
#define ADC_SLEEP 5 ///< Sleep mode.
-
+#define ADC_FREERUN 7 ///< Freerun.
/**
* Prescaler rate selection.
@@ -81,37 +83,59 @@
/**
* Start up timer.
*/
-#define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask.
-#define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
-
-#define ADC_SUT0 0 ///< 0 period of ADCClock.
-#define ADC_SUT8 1 ///< 8 period of ADCClock.
-#define ADC_SUT16 2 ///< 16 period of ADCClock.
-#define ADC_SUT24 3 ///< 24 period of ADCClock.
-#define ADC_SUT64 4 ///< 64 period of ADCClock.
-#define ADC_SUT80 5 ///< 80 period of ADCClock.
-#define ADC_SUT96 6 ///< 96 period of ADCClock.
-#define ADC_SUT112 7 ///< 112 period of ADCClock.
-#define ADC_SUT512 8 ///< 512 period of ADCClock.
-#define ADC_SUT576 9 ///< 576 period of ADCClock.
+#define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask.
+#define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
+
+/**
+ * Start up timer.
+ * $WIZ$ sam3_adc_sut = "ADC_SUT0","ADC_SUT8","ADC_SUT16","ADC_SUT24","ADC_SUT64","DC_SUT80","ADC_SUT96","ADC_SUT112","ADC_SUT512","ADC_SUT576","ADC_SUT640","ADC_SUT704","ADC_SUT768","ADC_SUT832","ADC_SUT896","ADC_SUT960"
+ * \{
+ */
+#define ADC_SUT0 0 ///< 0 period of ADCClock.
+#define ADC_SUT8 1 ///< 8 period of ADCClock.
+#define ADC_SUT16 2 ///< 16 period of ADCClock.
+#define ADC_SUT24 3 ///< 24 period of ADCClock.
+#define ADC_SUT64 4 ///< 64 period of ADCClock.
+#define ADC_SUT80 5 ///< 80 period of ADCClock.
+#define ADC_SUT96 6 ///< 96 period of ADCClock.
+#define ADC_SUT112 7 ///< 112 period of ADCClock.
+#define ADC_SUT512 8 ///< 512 period of ADCClock.
+#define ADC_SUT576 9 ///< 576 period of ADCClock.
#define ADC_SUT640 10 ///< 640 period of ADCClock.
#define ADC_SUT704 11 ///< 704 period of ADCClock.
#define ADC_SUT768 12 ///< 768 period of ADCClock.
#define ADC_SUT832 13 ///< 832 period of ADCClock.
#define ADC_SUT896 14 ///< 896 period of ADCClock.
#define ADC_SUT960 15 ///< 896 period of ADCClock.
+/** \} */
/**
- * Sample & hold time.
- */
-#define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask.
-#define ADC_SHTIME_SHIFT 20 ///< Sample & hold time shift.
-#define ADC_AST3 0 ///< 3 period of ADCClock
-#define ADC_AST5 1 ///< 5 period of ADCClock
-#define ADC_AST9 2 ///< 9 period of ADCClock
-#define ADC_AST17 3 ///< 17 period of ADCClock
+ * Analog Settling Time.
+ * $WIZ$ sam3_adc_stt = "ADC_AST3", "ADC_AST5", "ADC_AST9", "ADC_AST17"
+ */
+#define ADC_SETTLING_MASK 0x00300000 ///< Analog Settling Time mask.
+#define ADC_SETTLING_SHIFT 20 ///< Analog Settling Time shift.
+#define ADC_AST3 0 ///< 3 period of ADCClock
+#define ADC_AST5 1 ///< 5 period of ADCClock
+#define ADC_AST9 2 ///< 9 period of ADCClock
+#define ADC_AST17 3 ///< 17 period of ADCClock
+
+/**
+ * Tracking Time.
+ * Tracking Time = (TRACKTIM + 1) * ADCClock periods.
+ */
+#define ADC_TRACKTIM_MASK 0x0F000000 ///< Tracking Time mask.
+#define ADC_TRACKTIM_SHIFT 24 ///< Tracking Time shift.
+
+/**
+ * Transfer Period.
+ * Transfer Period = (TRANSFER * 2 + 3) ADCClock periods.
+ */
+#define ADC_TRANSFER_MASK 0x30000000 ///< Transfer Period mask.
+#define ADC_TRANSFER_SHIFT 28 ///< Transfer Period shift.
/* \} */
+
/**
* ADC channel enable register
*/
@@ -130,6 +154,14 @@
#define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
#define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address.
+
+/**
+ * ADC status register
+ */
+#define ADC_SR_OFF 0x0000001C ///< Status register offeset.
+#define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address.
+
+
#define ADC_CH_MASK 0x000000FF ///< Channel mask.
#define ADC_CH0 0 ///< Channel 0
#define ADC_CH1 1 ///< Channel 1
@@ -191,10 +223,32 @@
/**
* ADC last convert data register.
+ * \{
*/
#define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset.
#define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted RAW data register.
#define ADC_LDATA (ADC_LCDR & 0xFFF) ///< Last data converted register.
#define ADC_CHNB ((ADC_LCDR & 0xF000) >> 12) ///< Channel number.
+/* \} */
+
+
+/**
+ * ADC Channel data register.
+ * \{
+ */
+#define ADC_CDR_OFF 0x00000050 ///< Channel data register offeset.
+#define ADC_CDR (*((reg32_t *)(ADC_BASE + ADC_CDR_OFF))) ///< Channel data register.
+/* \} */
+
+
+/**
+ * ADC Analog Control register.
+ * \{
+ */
+#define ADC_ACR_OFF 0x00000094 ///< Analog control register offeset.
+#define ADC_ACR (*((reg32_t *)(ADC_BASE + ADC_ACR_OFF))) ///< Analog control register.
+#define ADC_TSON 4 ///< Temperature Sensor On.
+#define ADC_TEMPERATURE_CH 15 ///< Channel where is the internal sensor temperature
+/* \} */
#endif /* SAM3_ADC_H */
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_dacc.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_dacc.h
new file mode 100644
index 0000000..0848a3b
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_dacc.h
@@ -0,0 +1,225 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/
+ *
+ * -->
+ *
+ * \author Daniele Basile <as...@de...>
+ *
+ * SAM3 Digital to Analog to Converter.
+ *
+ * $WIZ$
+ */
+
+
+#ifndef SAM3_DACC_H
+#define SAM3_DACC_H
+
+/** DACC registers base. */
+#define DACC_BASE 0x400C8000
+
+/**
+ * DACC control register
+ * \{
+ */
+#define DACC_CR_OFF 0x00000000 ///< Control register offeset.
+#define DACC_CR (*((reg32_t*)(DACC_BASE + DACC_CR_OFF))) ///< Control register address.
+#define DACC_SWRST 0 ///< Software reset.
+/* \} */
+
+/**
+ * DACC mode register
+ * \{
+ */
+#define DACC_MR_OFF 0x00000004 ///< Mode register offeset.
+#define DACC_MR (*((reg32_t*) (DACC_BASE + DACC_MR_OFF))) ///< Mode register address.
+#define DACC_TRGEN 0 ///< Trigger enable.
+#define DACC_TRGSEL_MASK 0x14 ///< Trigger selection mask.
+#define DACC_TRGSEL_SHIFT 1 ///< Trigger selection shift.
+#define DACC_WORD 4 ///< Word transfer.
+#define DACC_SLEEP 5 ///< Sleep mode.Fast Wake up Mode
+#define DACC_FASTWKUP 6 ///< Fast Wake up Mode
+#define DACC_REFRESH_MASK 0xFF00 ///< Refresh Period mask
+#define DACC_REFRESH_SHIFT 8 ///< Refresh Period shift
+#define DACC_USER_SEL_MASK 0x30000 ///< User Channel Selection mask
+#define DACC_USER_SEL_SHIFT 16 ///< User Channel Selection shift
+#define DACC_TAG 20 ///< Tag selection mode
+#define DACC_MAXS 21 ///< Max speed mode
+#define DACC_STARTUP_MASK 0x3F000000 ///< Startup time selection
+#define DACC_STARTUP_SHIFT 24 ///< Startup time selsection shift
+
+
+/**
+ * Trigger selection.
+ * $WIZ$ sam3x_dac_tc = "DACC_TRGSEL_TIO_CH0", "DACC_TRGSEL_TIO_CH1", "DACC_TRGSEL_TIO_CH2", "DACC_TRGSEL_PWM0", "DACC_TRGSEL_PWM1"
+ * \{
+ */
+ #define DACC_TRGSEL_TIO_CH0 1
+ #define DACC_TRGSEL_TIO_CH1 2
+ #define DACC_TRGSEL_TIO_CH2 3
+ #define DACC_TRGSEL_PWM0 4
+ #define DACC_TRGSEL_PWM1 5
+/* \} */
+
+#define DACC_MR_STARTUP_0 0 ///< 0 periods of DACClock
+#define DACC_MR_STARTUP_8 1 ///< 8 periods of DACClock
+#define DACC_MR_STARTUP_16 2 ///< 16 periods of of DACClock
+#define DACC_MR_STARTUP_24 3 ///< 24 periods of of DACClock
+#define DACC_MR_STARTUP_64 4 ///< 64 periods of of DACClock
+#define DACC_MR_STARTUP_80 5 ///< 70 periods of of DACClock
+#define DACC_MR_STARTUP_96 6 ///< 96 periods of of DACClock
+#define DACC_MR_STARTUP_112 7 ///< 112 periods of of DACClock
+#define DACC_MR_STARTUP_512 8 ///< 512 periods of DACClock
+#define DACC_MR_STARTUP_576 9 ///< 576 periods of DACClock
+#define DACC_MR_STARTUP_640 10 ///< 640 periods of DACClock
+#define DACC_MR_STARTUP_704 11 ///< 704 periods of DACClock
+#define DACC_MR_STARTUP_768 12 ///< 768 periods of DACClock
+#define DACC_MR_STARTUP_832 13 ///< 832 periods of DACClock
+#define DACC_MR_STARTUP_896 14 ///< 896 periods of DACClock
+#define DACC_MR_STARTUP_960 15 ///< 960 periods of DACClock
+#define DACC_MR_STARTUP_1024 16 ///< 1024 periods of DACClock
+#define DACC_MR_STARTUP_1088 17 ///< 1088 periods of DACClock
+#define DACC_MR_STARTUP_1152 18 ///< 1152 periods of DACClock
+#define DACC_MR_STARTUP_1216 19 ///< 1216 periods of DACClock
+#define DACC_MR_STARTUP_1280 20 ///< 1280 periods of DACClock
+#define DACC_MR_STARTUP_1344 21 ///< 1344 periods of DACClock
+#define DACC_MR_STARTUP_1408 22 ///< 1408 periods of DACClock
+#define DACC_MR_STARTUP_1472 23 ///< 1472 periods of DACClock
+#define DACC_MR_STARTUP_1536 24 ///< 1536 periods of DACClock
+#define DACC_MR_STARTUP_1600 25 ///< 1600 periods of DACClock
+#define DACC_MR_STARTUP_1664 26 ///< 1664 periods of DACClock
+#define DACC_MR_STARTUP_1728 27 ///< 1728 periods of DACClock
+#define DACC_MR_STARTUP_1792 28 ///< 1792 periods of DACClock
+#define DACC_MR_STARTUP_1856 29 ///< 1856 periods of DACClock
+#define DACC_MR_STARTUP_1920 30 ///< 1920 periods of DACClock
+#define DACC_MR_STARTUP_1984 31 ///< 1984 periods of DACClock
+/* \} */
+
+/**
+ * DACC channel enable register
+ */
+#define DACC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
+#define DACC_CHER (*((reg32_t*) (DACC_BASE + DACC_CHER_OFF))) ///< Channel enable register address.
+
+/**
+ * DACC channel disable register
+ */
+#define DACC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
+#define DACC_CHDR (*((reg32_t*) (DACC_BASE + DACC_CHDR_OFF))) ///< Channel disable register address.
+
+/**
+ * DACC channel status register
+ */
+#define DACC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
+#define DACC_CHSR (*((reg32_t*) (DACC_BASE + DACC_CHSR_OFF))) ///< Channel status register address.
+
+#define DACC_CH0 0 ///< Channel 0.
+#define DACC_CH1 1 ///< Channel 1.
+/* \} */
+
+/**
+ * DACC Conversion data register
+ */
+#define DACC_CDR_OFF 0x00000020 ///< Conversion data register offeset.
+#define DACC_CDR (*((reg32_t*) (DACC_BASE + DACC_CDR_OFF))) ///< Conversion data register address.
+
+
+/**
+ * DACC Interrupt enable register
+ */
+#define DACC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
+#define DACC_IER (*((reg32_t*) (DACC_BASE + DACC_IER_OFF))) ///< Interrupt enable register address.
+
+/**
+ * DACC Interrupt disable register
+ */
+#define DACC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
+#define DACC_IDR (*((reg32_t*) (DACC_BASE + DACC_IDR_OFF))) ///< Interrupt disable register address.
+
+/**
+ * DACC Interrupt disable register
+ */
+#define DACC_IMR_OFF 0x0000002C ///< Interrupt disable register offeset.
+#define DACC_IMR (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF))) ///< Interrupt disable register address.
+
+/**
+ * DACC Interrupt status register
+ */
+#define DACC_ISR_OFF 0x00000030 ///< Interrupt disable status offeset.
+#define DACC_ISR (*((reg32_t*) (DACC_BASE + DACC_ISR_OFF))) ///< Interrupt status register address.
+
+#define DACC_TXRDY 0 ///< Transmit ready interrupt
+#define DACC_EOC 1 ///< End of conversion interrupt
+#define DACC_ENDTX 2 ///< End of transmit buffer interrupt
+#define DACC_TXBUFE 3 ///< Transmit buffer empty interrupt
+
+
+/**
+ * DMA controller for DACC
+ * DACC PDC register.
+ */
+#define DACC_RPR_OFF 0x100 ///< Receive Pointer Register.
+#define DACC_RPR (*((reg32_t*) (DACC_BASE + DACC_RPR_OFF))) ///< Receive Pointer Register.
+
+#define DACC_RCR_OFF 0x104 ///< Receive Counter Register.
+#define DACC_RCR (*((reg32_t*) (DACC_BASE + DACC_RCR_OFF))) ///< Receive Counter Register.
+
+#define DACC_TPR_OFF 0x108 ///< Transmit Pointer Register.
+#define DACC_TPR (*((reg32_t*) (DACC_BASE + DACC_TPR_OFF))) ///< Transmit Pointer Register.
+
+#define DACC_TCR_OFF 0x10C ///< Transmit Counter Register.
+#define DACC_TCR (*((reg32_t*) (DACC_BASE + DACC_TCR_OFF))) ///< Transmit Counter Register.
+
+#define DACC_RNPR_OFF 0x110 ///< Receive Next Pointer Register.
+#define DACC_RNPR (*((reg32_t*) (DACC_BASE + DACC_RNPR_OFF))) ///< Receive Next Pointer Register.
+
+#define DACC_RNCR_OFF 0x114 ///< Receive Next Counter Register.
+#define DACC_RNCR (*((reg32_t*) (DACC_BASE + DACC_RNCR_OFF))) ///< Receive Next Counter Register.
+
+#define DACC_TNPR_OFF 0x118 ///< Transmit Next Pointer Register.
+#define DACC_TNPR (*((reg32_t*) (DACC_BASE + DACC_TNPR_OFF))) ///< Transmit Next Pointer Register.
+
+#define DACC_TNCR_OFF 0x11C ///< Transmit Next Counter Register.
+#define DACC_TNCR (*((reg32_t*) (DACC_BASE + DACC_TNCR_OFF))) ///< Transmit Next Counter Register.
+
+#define DACC_PTCR_OFF 0x120 ///< Transfer Control Register.
+#define DACC_PTCR (*((reg32_t*) (DACC_BASE + DACC_PTCR_OFF))) ///< Transfer Control Register.
+
+#define DACC_PTSR_OFF 0x124 ///< Transfer Status Register.
+#define DACC_PTSR (*((reg32_t*) (DACC_BASE + DACC_PTSR_OFF))) ///< Transfer Status Register.
+
+
+#define DACC_PTCR_RXTEN 0 ///< DACC_PTCR Receiver Transfer Enable.
+#define DACC_PTCR_RXTDIS 1 ///< DACC_PTCR Receiver Transfer Disable.
+#define DACC_PTCR_TXTEN 8 ///< DACC_PTCR Transmitter Transfer Enable.
+#define DACC_PTCR_TXTDIS 9 ///< DACC_PTCR Transmitter Transfer Disable.
+#define DACC_PTSR_RXTEN 0 ///< DACC_PTSR Receiver Transfer Enable.
+#define DACC_PTSR_TXTEN 8 ///< DACC_PTSR Transmitter Transfer Enable.
+
+#endif /* SAM3_DACC_H */
diff --git a/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_tc.h b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_tc.h
new file mode 100644
index 0000000..dfd5a56
--- /dev/null
+++ b/elec/boards/USB_CAN/Firmware/bertos/cpu/cortex-m3/io/sam3_tc.h
@@ -0,0 +1,193 @@
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; yo can redistribte it and/or modify
+ * it nder the terms of the GN General Pblic License as pblished by
+ * the Free Software Fondation; either version 2 of the License, or
+ * (at yor option any later version.
+ *
+ * This program is distribted in the hope that it will be sefl,
+ * bt WITHOT ANY WARRANTY; withot even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICLAR PRPOSE. See the
+ * GN General Pblic License for more details.
+ *
+ * Yo shold have received a copy of the GN General Pblic License
+ * along with this program; if not, write to the Free Software
+ * Fondation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 SA
+ *
+ * As a special exception, yo may se this file as part of a free software
+ * library withot restriction. Specifically, if other files instantiate
+ * templates or se macros or inline fnctions from this file, or yo compile
+ * this file and link it with other files to prodce an exectable, this
+ * file does not by itself case the reslting exectable to be covered by
+ * the GN General Pblic License. This exception does not however
+ * invalidate any other reasons why the exectable file might be covered by
+ * the GN General Pblic License.
+ *
+ * Copyright 2011 Develer S.r.l. (http://www.develer.com/
+ *
+ * -->
+ *
+ * \author Daniele Basile <as...@de...>
+ *
+ * SAM3 Timer counter
+ *
+ * $WIZ$
+ */
+
+
+#ifndef SAM3_TC_H
+#define SAM3_TC_H
+
+/** Timer conter register bases. */
+#define TC0_BASE 0x40080000 ///< TC0 Base Address.
+#define TC1_BASE 0x40084000 ///< TC1 Base Address.
+#define TC2_BASE 0x40088000 ///< TC2 Base Address.
+
+/**
+ * Timer conter control register
+ */
+#define TC0_CCR0_OFF 0x00 ///< TC0 Channel Control Register (channel = 0).
+#define TC0_CCR0 (*((reg32_t*)(TC0_BASE + TC0_CCR0_OFF))) ///< TC0 Channel Control Register (channel = 0).
+
+#define TC0_CMR0_OFF 0x04 ///< TC0 Channel Mode Register (channel = 0).
+#define TC0_CMR0 (*((reg32_t*)(TC0_BASE + TC0_CMR0_OFF))) ///< TC0 Channel Mode Register (channel = 0).
+
+#define TC_CMR_CPCTRG 14 ///< RC Compare Trigger Enable
+#define TC_CMR_WAVE 15 ///< Waveform mode is enabled
+
+#define TC_CMR_ACPA_SET 0x10000 ///< RA Compare Effect: set
+#define TC_CMR_ACPA_CLEAR 0x20000 ///< RA Compare Effect: clear
+#define TC_CMR_ACPA_TOGGLE 0x30000 ///< RA Compare Effect: toggle
+
+#define TC_CMR_ACPC_SET 0x40000 ///< RC Compare Effect: set
+#define TC_CMR_ACPC_CLEAR 0x80000 ///< RC Compare Effect: clear
+#define TC_CMR_ACPC_TOGGLE 0xC0000 ///< RC Compare Effect: toggle
+
+#define TC_CCR_CLKEN 0 ///< Counter Clock Enable Command
+#define TC_CCR_CLKDIS 1 ///< Counter Clock Disable Command
+#define TC_CCR_SWTRG 2 ///< Software Trigger Command
+
+#define TC_TIMER_CLOCK1 0 ///< Select timer clock TCLK1
+#define TC_TIMER_CLOCK2 1 ///< Select timer clock TCLK2
+
+#define TC0_SMMR0_OFF 0x08 ///< TC0 Stepper Motor Mode Register (channel = 0).
+#define TC0_SMMR0 (*((reg32_t*)(TC0_BASE + TC0_SMMR0_OFF))) ///< TC0 Stepper Motor Mode Register (channel = 0).
+
+#define TC0_CV0_OFF 0x10 ///< TC0 Conter Vale (channel = 0).
+#define TC0_CV0 (*((reg32_t*)(TC0_BASE + TC0_CV0_OFF))) ///< TC0 Conter Vale (channel = 0).
+
+#define TC0_RA0_OFF 0x14 ///< TC0 Register A (channel = 0).
+#define TC0_RA0 (*((reg32_t*)(TC0_BASE + TC0_RA0_OFF))) ///< TC0 Register A (channel = 0).
+
+#define TC0_RB0_OFF 0x18 ///< TC0 Register B (channel = 0).
+#define TC0_RB0 (*((reg32_t*)(TC0_BASE + TC0_RB0_OFF))) ///< TC0 Register B (channel = 0).
+
+#define TC0_RC0_OFF 0x1C ///< TC0 Register C (channel = 0).
+#define TC0_RC0 (*((reg32_t*)(TC0_BASE + TC0_RC0_OFF))) ///< TC0 Register C (channel = 0).
+
+#define TC0_SR0_OFF 0x20 ///< TC0 Stats Register (channel = 0).
+#define TC0_SR0 (*((reg32_t*)(TC0_BASE + TC0_SR0_OFF))) ///< TC0 Stats Register (channel = 0).
+
+#define TC0_IER0_OFF 0x24 ///< TC0 Interrpt Enable Register (channel = 0).
+#define TC0_IER0 (*((reg32_t*)(TC0_BASE + TC0_IER0_OFF))) ///< TC0 Interrpt Enable Register (channel = 0).
+
+#define TC0_IDR0_OFF 0x28 ///< TC0 Interrpt Disable Register (channel = 0).
+#define TC0_IDR0 (*((reg32_t*)(TC0_BASE + TC0_IDR0_OFF))) ///< TC0 Interrpt Disable Register (channel = 0).
+
+#define TC0_IMR0_OFF 0x2C ///< TC0 Interrpt Mask Register (channel = 0).
+#define TC0_IMR0 (*((reg32_t*)(TC0_BASE + TC0_IMR0_OFF))) ///< TC0 Interrpt Mask Register (channel = 0).
+
+#define TC0_CCR1_OFF 0x40 ///< TC0 Channel Control Register (channel = 1).
+#define TC0_CCR1 (*((reg32_t*)(TC0_BASE + TC0_CCR1_OFF))) ///< TC0 Channel Control Register (channel = 1).
+
+#define TC0_CMR1_OFF 0x44 ///< TC0 Channel Mode Register (channel = 1).
+#define TC0_CMR1 (*((reg32_t*)(TC0_BASE + TC0_CMR1_OFF))) ///< TC0 Channel Mode Register (channel = 1).
+
+#define TC0_SMMR1_OFF 0x48 ///< TC0 Stepper Motor Mode Register (channel = 1).
+#define TC0_SMMR1 (*((reg32_t*)(TC0_BASE + TC0_SMMR1_OFF))) ///< TC0 Stepper Motor Mode Register (channel = 1).
+
+#define TC0_CV1_OFF 0x50 ///< TC0 Conter Vale (channel = 1).
+#define TC0_CV1 (*((reg32_t*)(TC0_BASE + TC0_CV1_OFF))) ///< TC0 Conter Vale (channel = 1).
+
+#define TC0_RA1_OFF 0x54 ///< TC0 Register A (channel = 1).
+#define TC0_RA1 (*((reg32_t*)(TC0_BASE + TC0_RA1_OFF))) ///< TC0 Register A (channel = 1).
+
+#define TC0_RB1_OFF 0x58 ///< TC0 Register B (channel = 1).
+#define TC0_RB1 (*((reg32_t*)(TC0_BASE + TC0_RB1_OFF))) ///< TC0 Register B (channel = 1).
+
+#define TC0_RC1_OFF 0x5C ///< TC0 Register C (channel = 1).
+#define TC0_RC1 (*((reg32_t*)(TC0_BASE + TC0_RC1_OFF))) ///< TC0 Register C (channel = 1).
+
+#define TC0_SR1_OFF 0x60 ///< TC0 Stats Register (channel = 1).
+#define TC0_SR1 (*((reg32_t*)(TC0_BASE + TC0_SR1_OFF))) ///< TC0 Stats Register (channel = 1).
+
+#define TC0_IER1_OFF 0x64 ///< TC0 Interrpt Enable Register (channel = 1).
+#define TC0_IER1 (*((reg32_t*)(TC0_BASE + TC0_IER1_OFF))) ///< TC0 Interrpt Enable Register (channel =...
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