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[Krobot-commits] [SCM] krobot branch, master, updated. cd2cfc4c2e3ad7102f78c6d6d508c23a6f2139aa
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From: Xavier L. <Ba...@us...> - 2011-03-09 17:43:29
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot".
The branch, master has been updated
via cd2cfc4c2e3ad7102f78c6d6d508c23a6f2139aa (commit)
via 8909d78726794fe3c2322ac35cfe2a49f6172a18 (commit)
from d66c75758ef8ece9b93d406ace55c474d0480d77 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit cd2cfc4c2e3ad7102f78c6d6d508c23a6f2139aa
Author: Xavier Lagorce <Xav...@cr...>
Date: Wed Mar 9 18:41:11 2011 +0100
[Motor_Controller_STM32] Added a rapid stm32lib inclusion for PWM management
commit 8909d78726794fe3c2322ac35cfe2a49f6172a18
Author: Xavier Lagorce <Xav...@cr...>
Date: Wed Mar 9 18:35:45 2011 +0100
[Motor_Controller_STM32] Trying to activate USART3 Remapping
-----------------------------------------------------------------------
Changes:
diff --git a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/controller_motor_stm32_user.mk b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/controller_motor_stm32_user.mk
index ee4547c..7202af8 100644
--- a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/controller_motor_stm32_user.mk
+++ b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/controller_motor_stm32_user.mk
@@ -9,6 +9,9 @@ controller_motor_stm32_PROGRAMMER_PORT = none
# Files included by the user.
controller_motor_stm32_USER_CSRC = \
+ $(controller_motor_stm32_SRC_PATH)/stm32lib/stm32f10x_rcc.c \
+ $(controller_motor_stm32_SRC_PATH)/stm32lib/stm32f10x_tim.c \
+ $(controller_motor_stm32_SRC_PATH)/motor.c \
$(controller_motor_stm32_SRC_PATH)/main.c \
#
diff --git a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/main.c b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/main.c
index 507af4e..65e8e2e 100644
--- a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/main.c
+++ b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/main.c
@@ -1,4 +1,8 @@
-// Empty main.c file generated by the wizard
+/*
+ * Firmware for Controller Motor STM32
+ *
+ * Author : Xavier Lagorce <Xav...@cr...>
+ */
#include <cpu/irq.h>
#include <cfg/debug.h>
#include <drv/timer.h>
@@ -8,13 +12,20 @@
#include <math.h>
#include "hw/hw_led.h"
+#include "motor.h"
static void init(void)
{
IRQ_ENABLE;
// Remapping peripherals
+ // Enable clocking on AFIO
+ RCC->APB2ENR |= RCC_APB2_AFIO;
+ // Remap UART3
stm32_gpioRemap(GPIO_PARTIALREMAP_USART3, GPIO_REMAP_ENABLE);
+ // UART3 TX in ouput AF mode
+ stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, BV(10),
+ GPIO_MODE_AF_PP, GPIO_SPEED_50MHZ);
/* Initialize debugging module (allow kprintf(), etc.) */
kdbg_init();
@@ -29,9 +40,9 @@ static void init(void)
// Initialize LED driver
LEDS_INIT();
- stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, BV(10),
- GPIO_MODE_AF_PP, GPIO_SPEED_50MHZ);
+ // Initialize MOTOR driver
+ motorsInit();
}
static void NORETURN speaktome_process(void)
diff --git a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/motor.c b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/motor.c
new file mode 100644
index 0000000..8ef9979
--- /dev/null
+++ b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/motor.c
@@ -0,0 +1,359 @@
+/*
+ * Motor controller interface
+ * This is a quick implementation based of the stm32lib from ST and from
+ * previous implementations.
+ *
+ * This is supposed to be quick and dirty, waiting for BeRTOS proper
+ * PWMs integration, to allow work on other systems using PWMs.
+ *
+ * Author : Xavier Lagorce
+ */
+
+#include "motor.h"
+#include <cfg/macros.h>
+#include <drv/gpio_stm32.h>
+#include "stm32lib/stm32f10x_tim.h"
+
+uint8_t enabledMotors = 0, indMotors = 0;
+signed char currentSpeedSign[] = {0, 0, 0, 0};
+TIM_OCInitTypeDef TIM_OCInitStructure;
+
+/*
+ Some dirty imports from the stm32lib from ST <stm32_lib>
+ */
+
+//#define __IO volatile /*!< defines 'read / write' permissions */
+//typedef __IO uint16_t vu16;
+
+
+/*
+ End of imports </stm32_lib>
+ */
+
+/*
+ * Initialises TIM2 for PWM generation and associated GPIOs
+ */
+void motorsInit(void) {
+
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+
+ //Enable GPIOA, GPIOB, GPIOC and GPIOD clock
+ RCC->APB2ENR |= RCC_APB2_GPIOA | RCC_APB2_GPIOB | RCC_APB2_GPIOC | RCC_APB2_GPIOD;
+
+ //Enable timer clock
+ RCC->APB1ENR |= RCC_APB1_TIM2;
+
+ //Setup timer for quadrature encoder interface
+ //Motor1 : EN PA5
+ // INA PC4
+ // INB PC5
+ // PWM PA0
+ // IND LED1
+ //Motor2 : EN PB15
+ // INA PB1
+ // INB PB14
+ // PWM PA1
+ // IND LED2
+ //Motor3 : EN PA10
+ // INA PC10
+ // INB PC11
+ // PWM PA2
+ // IND LED3
+ //Motor4 : EN PD2
+ // INA PB5
+ // INB PD9
+ // PWM PA3
+ // IND LED4
+ stm32_gpioPinConfig(((struct stm32_gpio *)GPIOA_BASE),
+ BV(5) | BV(10),
+ GPIO_MODE_OUT_PP, GPIO_SPEED_50MHZ);
+ stm32_gpioPinConfig(((struct stm32_gpio *)GPIOA_BASE),
+ BV(0) | BV(1) | BV(2) | BV(3),
+ GPIO_MODE_AF_PP, GPIO_SPEED_50MHZ);
+ stm32_gpioPinConfig(((struct stm32_gpio *)GPIOB_BASE),
+ BV(1) | BV(5) | BV(9) | BV(14) | BV(15),
+ GPIO_MODE_OUT_PP, GPIO_SPEED_50MHZ);
+ stm32_gpioPinConfig(((struct stm32_gpio *)GPIOC_BASE),
+ BV(4) | BV(5) | BV(10) | BV(11),
+ GPIO_MODE_OUT_PP, GPIO_SPEED_50MHZ);
+ stm32_gpioPinConfig(((struct stm32_gpio *)GPIOD_BASE),
+ BV(2),
+ GPIO_MODE_OUT_PP, GPIO_SPEED_50MHZ);
+
+ // Default value of H-Bridge configuration
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOA_BASE),
+ BV(5) | BV(10), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE),
+ BV(1) | BV(5) | BV(9) | BV(14) | BV(15), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE),
+ BV(4) | BV(5) | BV(10) | BV(11), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOD_BASE),
+ BV(2), 0);
+
+ // TimeBase configuration
+ TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (72000000 / 72000000) - 1;;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseStructure.TIM_Period = 3600; // 20 kHz
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+
+ // PWM1 Mode configuration: Channel1
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+ TIM_OCInitStructure.TIM_Pulse = 0;
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+
+ TIM_OC1Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_OC2Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_OC3Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_OC4Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Enable);
+
+ // All motors are disabled
+ enabledMotors = 0;
+
+ //Enable timer Peripherals
+ TIM_Cmd(TIM2,ENABLE);
+
+ // Disable indicators
+ //GPIO_ResetBits(GPIOC, GPIO_Pin_3 | GPIO_Pin_5 | GPIO_Pin_9);
+}
+
+/*
+ * Enable a motor driver
+ */
+void enableMotor(uint8_t motor) {
+
+ if (motor & MOTOR1) {
+ enabledMotors |= MOTOR1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOA_BASE), BV(5), 1);
+ }
+ if (motor & MOTOR2) {
+ enabledMotors |= MOTOR2;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(15), 1);
+ }
+ if (motor & MOTOR3) {
+ enabledMotors |= MOTOR3;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOA_BASE), BV(10), 1);
+ }
+ if (motor & MOTOR4) {
+ enabledMotors |= MOTOR4;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOD_BASE), BV(2), 1);
+ }
+}
+
+/*
+ * Disable a motor driver
+ */
+void disableMotor(uint8_t motor) {
+
+ if (motor & MOTOR1) {
+ enabledMotors &= ~MOTOR1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOA_BASE), BV(5), 0);
+ }
+ if (motor & MOTOR2) {
+ enabledMotors &= ~MOTOR2;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(15), 0);
+ }
+ if (motor & MOTOR3) {
+ enabledMotors &= ~MOTOR3;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOA_BASE), BV(10), 0);
+ }
+ if (motor & MOTOR4) {
+ enabledMotors &= ~MOTOR4;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOD_BASE), BV(2), 0);
+ }
+}
+
+/*
+ * Step one motor's speed
+ */
+void motorSetSpeed(uint8_t motor, int32_t speed) {
+
+ uint8_t ind = 0;
+
+ if (speed == 0) {
+ motorStop(motor, MOTOR_BRAKE);
+ return;
+ }
+
+ if (speed >= MAX_PWM) {
+ speed = MAX_PWM;
+ ind = 1;
+ } else if (speed <= -MAX_PWM) {
+ speed = -MAX_PWM;
+ ind = 1;
+ } else {
+ ind = 0;
+ }
+
+ if (motor & MOTOR1) {
+ if(speed > 0) {
+ if (currentSpeedSign[0] != 1) {
+ currentSpeedSign[0] = 1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(4), 1);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(5), 0);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)speed;
+ } else {
+ if (currentSpeedSign[0] != -1) {
+ currentSpeedSign[0] = -1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(4), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(5), 1);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)(-speed);
+ }
+ TIM_OC1Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_ARRPreloadConfig(TIM2, ENABLE);
+ if (ind) {
+ if ((indMotors & MOTOR1) == 0) {
+ //GPIO_SetBits(GPIOC, GPIO_Pin_3);
+ indMotors |= MOTOR1;
+ }
+ } else if ((indMotors & MOTOR1) != 0) {
+ //GPIO_ResetBits(GPIOC, GPIO_Pin_3);
+ indMotors &= ~MOTOR1;
+ }
+ }
+ if (motor & MOTOR2) {
+ if(speed > 0) {
+ if (currentSpeedSign[1] != 1) {
+ currentSpeedSign[1] = 1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(1), 1);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(14), 0);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)speed;
+ } else {
+ if (currentSpeedSign[1] != -1) {
+ currentSpeedSign[1] = -1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(1), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(14), 1);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)(-speed);
+ }
+ TIM_OC2Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_ARRPreloadConfig(TIM2, ENABLE);
+ if (ind) {
+ if ((indMotors & MOTOR2) == 0) {
+ //GPIO_SetBits(GPIOC, GPIO_Pin_5);
+ indMotors |= MOTOR2;
+ }
+ } else if ((indMotors & MOTOR2) != 0) {
+ //GPIO_ResetBits(GPIOC, GPIO_Pin_5);
+ indMotors &= ~MOTOR2;
+ }
+ }
+ if (motor & MOTOR3) {
+ if(speed > 0) {
+ if (currentSpeedSign[2] != 1) {
+ currentSpeedSign[2] = 1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(10), 1);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(11), 0);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)speed;
+ } else {
+ if (currentSpeedSign[2] != -1) {
+ currentSpeedSign[2] = -1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(10), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(11), 1);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)(-speed);
+ }
+ TIM_OC3Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_ARRPreloadConfig(TIM2, ENABLE);
+ if (ind) {
+ if ((indMotors & MOTOR3) == 0) {
+ //GPIO_SetBits(GPIOC, GPIO_Pin_9);
+ indMotors |= MOTOR3;
+ }
+ } else if ((indMotors & MOTOR3) != 0) {
+ //GPIO_ResetBits(GPIOC, GPIO_Pin_9);
+ indMotors &= ~MOTOR3;
+ }
+ }
+ if (motor & MOTOR4) {
+ if(speed > 0) {
+ if (currentSpeedSign[3] != 1) {
+ currentSpeedSign[3] = 1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(5), 1);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(9), 0);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)speed;
+ } else {
+ if (currentSpeedSign[3] != -1) {
+ currentSpeedSign[3] = -1;
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(5), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(9), 1);
+ }
+ TIM_OCInitStructure.TIM_Pulse = (uint16_t)(-speed);
+ }
+ TIM_OC4Init(TIM2, &TIM_OCInitStructure);
+ TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Enable);
+ TIM_ARRPreloadConfig(TIM2, ENABLE);
+ if (ind) {
+ if ((indMotors & MOTOR4) == 0) {
+ //GPIO_SetBits(GPIOC, GPIO_Pin_9);
+ indMotors |= MOTOR4;
+ }
+ } else if ((indMotors & MOTOR4) != 0) {
+ //GPIO_ResetBits(GPIOC, GPIO_Pin_9);
+ indMotors &= ~MOTOR4;
+ }
+ }
+}
+
+/*
+ * Stop a motor using the 'mode' mode.
+ */
+void motorStop(uint8_t motor, uint8_t mode) {
+
+ if (mode == MOTOR_STOP) {
+ if (motor & MOTOR1) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(4), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(5), 0);
+ currentSpeedSign[0] = 0;
+ }
+ if (motor & MOTOR2) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(1), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(14), 0);
+ currentSpeedSign[1] = 0;
+ }
+ if (motor & MOTOR3) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(10), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(11), 0);
+ currentSpeedSign[2] = 0;
+ }
+ if (motor & MOTOR4) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(5), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(9), 0);
+ currentSpeedSign[3] = 0;
+ }
+ } else if (mode == MOTOR_BRAKE) {
+ if (motor & MOTOR1) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(4), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(5), 0);
+ currentSpeedSign[0] = 0;
+ }
+ if (motor & MOTOR2) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(1), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(14), 0);
+ currentSpeedSign[1] = 0;
+ }
+ if (motor & MOTOR3) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(10), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOC_BASE), BV(11), 0);
+ currentSpeedSign[2] = 0;
+ }
+ if (motor & MOTOR4) {
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(5), 0);
+ stm32_gpioPinWrite(((struct stm32_gpio *)GPIOB_BASE), BV(9), 0);
+ currentSpeedSign[3] = 0;
+ }
+ }
+}
diff --git a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/motor.h b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/motor.h
new file mode 100644
index 0000000..d69ceeb
--- /dev/null
+++ b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/motor.h
@@ -0,0 +1,34 @@
+/*
+ * Motor controller interface
+ * This is a quick implementation based of the stm32lib from ST and from
+ * previous implementations.
+ *
+ * This is supposed to be quick and dirty, waiting for BeRTOS proper
+ * PWMs integration, to allow work on other systems using PWMs.
+ *
+ * Author : Xavier Lagorce
+ */
+
+#ifndef HEADER__MOTOR
+#define HEADER__MOTOR
+
+#define MOTOR1 1
+#define MOTOR2 2
+#define MOTOR3 4
+#define MOTOR4 8
+
+#define MOTOR_STOP 1
+#define MOTOR_BRAKE 2
+
+#define MAX_PWM 3600
+
+#include <drv/gpio_stm32.h>
+#include <drv/clock_stm32.h>
+
+void motorsInit(void);
+void enableMotor(uint8_t motor);
+void disableMotor(uint8_t motor);
+void motorSetSpeed(uint8_t motor, int32_t speed);
+void motorStop(uint8_t motor, uint8_t mode);
+
+#endif
diff --git a/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/stm32lib/core_cm3.h b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/stm32lib/core_cm3.h
new file mode 100644
index 0000000..5c75ec8
--- /dev/null
+++ b/elec/boards/Controller_Motor_STM32/Firmware/controller_motor_stm32/stm32lib/core_cm3.h
@@ -0,0 +1,1842 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * Parts of this files have been modified in ChibiOS/RT in order to fix
+ * some code quality issues.
+ */
+
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V1.30
+ * @date 30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ * - Error 10: \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';'
+ * .
+ * - Error 530: \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized
+ * .
+ * - Error 550: \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed
+ * .
+ * - Error 754: \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
+ * .
+ * - Error 750: \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
+ * .
+ * - Error 528: \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
+ * .
+ * - Error 751: \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
+ * .
+ * Note: To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core registers and bitfields
+ - Cortex-M core peripheral base address
+ @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+#include <stdint.h> /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
+} NVIC_Type;
+/*@}*/ /* end of group CMSIS_CM3_NVIC */
+
+
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
+ memory mapped structure for System Control Block (SCB)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM3_SCB */
+
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+ memory mapped structure for SysTick
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+/*@}*/ /* end of group CMSIS_CM3_ITM */
+
+
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
+ memory mapped structure for Interrupt Type
+ @{
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
+ memory mapped structure for Memory Protection Unit (MPU)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region S...
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