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[Krobot-resources] [SCM] krobot-resources branch, master, updated. 1f9606b5d51a8dce38491bf562793497196dd2f5
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From: Xavier L. <Sup...@us...> - 2010-04-17 14:54:07
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- Log -----------------------------------------------------------------
commit 1f9606b5d51a8dce38491bf562793497196dd2f5
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Apr 17 16:50:05 2010 +0200
Added a project template for the STM32 ARM processor
* It uses ST libraries
* It will blink the LED on the Olimex STM32-P103 developpement board
* It contains openocd configuration to flash the previously mentioned board
usage :
* clean : make clean
* compile : make all
* flash : make flash
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/template/jtag/flash.cfg b/arm/STM32/template/jtag/flash.cfg
new file mode 100644
index 0000000..75d09b1
--- /dev/null
+++ b/arm/STM32/template/jtag/flash.cfg
@@ -0,0 +1,7 @@
+init
+reset halt
+stm32x mass_erase 0
+flash write_bank 0 main.bin 0
+reset init
+reset run
+shutdown
\ No newline at end of file
diff --git a/arm/STM32/template/jtag/openocd.cfg b/arm/STM32/template/jtag/openocd.cfg
new file mode 100644
index 0000000..0f3a9a2
--- /dev/null
+++ b/arm/STM32/template/jtag/openocd.cfg
@@ -0,0 +1,84 @@
+#
+# Olimex ARM-USB-OCD
+#
+# http://www.olimex.com/dev/arm-usb-ocd.html
+#
+
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003
+
+# script for stm32
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# Use the correct size for the card
+set WORKAREASIZE 0x5000
+
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ # FIXME this never gets used to override defaults...
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0008
+ # Section 29.6.2
+ # Low density devices, Rev A
+ set _BSTAPID1 0x06412041
+ # Medium density devices, Rev A
+ set _BSTAPID2 0x06410041
+ # Medium density devices, Rev B and Rev Z
+ set _BSTAPID3 0x16410041
+ # High density devices, Rev A
+ set _BSTAPID4 0x06414041
+ # Connectivity line devices, Rev A and Rev Z
+ set _BSTAPID5 0x06418041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+ -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+ -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
+
diff --git a/arm/STM32/template/jtag/target.ini b/arm/STM32/template/jtag/target.ini
new file mode 100644
index 0000000..da18158
--- /dev/null
+++ b/arm/STM32/template/jtag/target.ini
@@ -0,0 +1,93 @@
+#
+# GDB init file for STM32x family
+#
+
+set complaints 1
+set output-radix 16
+set input-radix 16
+
+# GDB must be set to big endian mode first if needed.
+#set endian little
+
+# add str9lib src to gdb search path
+#dir /cygdrive/c/progra~1/anglia/idealist/examples/stm32/libstr32x/src
+#dir C:/Progra~1/Anglia/IDEaliST/examples/stm32/libstm32x/src
+
+# change gdb prompt
+set prompt (arm-gdb)
+
+# You will need to change this to reflect the address of your jtag interface.
+#target remote localhost:2000
+
+# The libremote daemon must be set to big endian before the
+# executable is loaded.
+#monitor endian little
+
+# Increase the packet size to improve download speed.
+# to view current setting use:
+# show remote memory-write-packet-size
+
+set remote memory-write-packet-size 1024
+set remote memory-write-packet-size fixed
+
+set remote memory-read-packet-size 1024
+set remote memory-read-packet-size fixed
+set remote hardware-watchpoint-limit 6
+set remote hardware-breakpoint-limit 6
+
+# Load the program executable (ram only)
+#load
+
+# Set a breakpoint at main().
+#b main
+
+# Run to the breakpoint.
+#c
+
+#
+# GDB command helpers
+#
+
+#
+# reset and map 0 to internal ram
+#
+
+define ramreset
+reset
+set *(int*)0xE000ED08 = 0x20000000
+echo Internal RAM set to address 0x0.
+end
+
+#
+# reset and map 0 to flash
+#
+
+define flashreset
+reset
+thb main
+echo Internal Flash set to address 0x0.
+end
+
+#
+# reset target
+#
+
+define reset
+monitor reset
+end
+
+document ramreset
+ramreset
+Causes a target reset, remaps Internal RAM to address 0x0.
+end
+
+document flashreset
+flashreset
+Causes a target reset, remaps Internal Flash to address 0x0.
+A temporary breakpoint is set at start of function main
+end
+
+document reset
+reset
+Causes a target reset.
+end
diff --git a/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld b/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld
new file mode 100644
index 0000000..5e4ce87
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld
@@ -0,0 +1,29 @@
+/*
+Linker script for STM32F10x
+Copyright RAISONANCE 2007 (modified by Lanchon 1-Feb-2008)
+You can use, copy and distribute this file freely, but without any waranty.
+Configure memory sizes, end of stack and boot mode for your project here.
+*/
+
+
+/* include the common STM32F10x sub-script */
+INCLUDE "STM32_COMMON.ld"
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* also change _estack below */
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
+ FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+}
+
+/* highest address of the user mode stack */
+_estack = 0x20005000;
+
+/* include the section management sub-script */
+/* (either "STM32_SEC_FLASH.ld" or "STM32_SEC_RAM.ld") */
+INCLUDE "STM32_SEC_FLASH.ld"
diff --git a/arm/STM32/template/lib/STM32_COMMON.ld b/arm/STM32/template/lib/STM32_COMMON.ld
new file mode 100644
index 0000000..6794c70
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_COMMON.ld
@@ -0,0 +1,164 @@
+/*
+Common part of the linker scripts for STR32 devices
+Copyright RAISONANCE 2007
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+
+/* default stack sizes.
+
+These are used by the startup in order to allocate stacks for the different modes.
+*/
+
+__Stack_Size = 1024 ;
+
+PROVIDE ( _Stack_Size = __Stack_Size ) ;
+
+__Stack_Init = _estack - __Stack_Size ;
+
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
+PROVIDE ( _Stack_Init = __Stack_Init ) ;
+
+/*
+There will be a link error if there is not this amount of RAM free at the end.
+*/
+_Minimum_Stack_Size = 0x100 ;
+
+
+
+/*
+this sends all unreferenced IRQHandlers to reset
+*/
+
+
+PROVIDE ( Undefined_Handler = 0 ) ;
+PROVIDE ( SWI_Handler = 0 ) ;
+PROVIDE ( IRQ_Handler = 0 ) ;
+PROVIDE ( Prefetch_Handler = 0 ) ;
+PROVIDE ( Abort_Handler = 0 ) ;
+PROVIDE ( FIQ_Handler = 0 ) ;
+
+PROVIDE ( NMIException = 0 ) ;
+PROVIDE ( HardFaultException = 0 ) ;
+PROVIDE ( MemManageException = 0 ) ;
+PROVIDE ( BusFaultException = 0 ) ;
+PROVIDE ( UsageFaultException = 0 ) ;
+PROVIDE ( SVCHandler = 0 ) ;
+PROVIDE ( DebugMonitor = 0 ) ;
+PROVIDE ( PendSVC = 0 ) ;
+PROVIDE ( SysTickHandler = 0 ) ;
+PROVIDE ( WWDG_IRQHandler = 0 ) ;
+PROVIDE ( PVD_IRQHandler = 0 ) ;
+PROVIDE ( TAMPER_IRQHandler = 0 ) ;
+PROVIDE ( RTC_IRQHandler = 0 ) ;
+PROVIDE ( FLASH_IRQHandler = 0 ) ;
+PROVIDE ( RCC_IRQHandler = 0 ) ;
+PROVIDE ( EXTI0_IRQHandler = 0 ) ;
+PROVIDE ( EXTI1_IRQHandler = 0 ) ;
+PROVIDE ( EXTI2_IRQHandler = 0 ) ;
+PROVIDE ( EXTI3_IRQHandler = 0 ) ;
+PROVIDE ( EXTI4_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
+PROVIDE ( ADC_IRQHandler = 0 ) ;
+PROVIDE ( USB_HP_CAN_TX_IRQHandler = 0 ) ;
+PROVIDE ( USB_LP_CAN_RX0_IRQHandler = 0 ) ;
+PROVIDE ( CAN_RX1_IRQHandler = 0 ) ;
+PROVIDE ( CAN_SCE_IRQHandler = 0 ) ;
+PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
+PROVIDE ( TIM2_IRQHandler = 0 ) ;
+PROVIDE ( TIM3_IRQHandler = 0 ) ;
+PROVIDE ( TIM4_IRQHandler = 0 ) ;
+PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
+PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
+PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
+PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
+PROVIDE ( SPI1_IRQHandler = 0 ) ;
+PROVIDE ( SPI2_IRQHandler = 0 ) ;
+PROVIDE ( USART1_IRQHandler = 0 ) ;
+PROVIDE ( USART2_IRQHandler = 0 ) ;
+PROVIDE ( USART3_IRQHandler = 0 ) ;
+PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
+PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
+PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
+
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/*this allows to compile the ST lib in "non-debug" mode*/
+
+
+/* Peripheral and SRAM base address in the alias region */
+PERIPH_BB_BASE = 0x42000000;
+SRAM_BB_BASE = 0x22000000;
+
+/* Peripheral and SRAM base address in the bit-band region */
+SRAM_BASE = 0x20000000;
+PERIPH_BASE = 0x40000000;
+
+/* Flash registers base address */
+PROVIDE ( FLASH_BASE = 0x40022000);
+/* Flash Option Bytes base address */
+PROVIDE ( OB_BASE = 0x1FFFF800);
+
+/* Peripheral memory map */
+APB1PERIPH_BASE = PERIPH_BASE ;
+APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
+AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
+
+PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
+PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
+PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
+PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
+PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
+PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
+PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
+PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
+PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
+PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
+PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
+PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
+PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
+PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
+
+PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
+PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
+PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
+PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
+PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
+PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
+PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
+PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
+PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
+PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
+PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
+PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
+
+PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
+PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
+PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
+PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
+PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
+PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
+PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
+PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
+PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
+
+/* System Control Space memory map */
+SCS_BASE = 0xE000E000;
+
+PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
+PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
+PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
+
diff --git a/arm/STM32/template/lib/STM32_SEC_EXT.ld b/arm/STM32/template/lib/STM32_SEC_EXT.ld
new file mode 100644
index 0000000..3623d06
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_EXT.ld
@@ -0,0 +1,181 @@
+/*
+Common part of the linker scripts for STR71x devices in EXT mode
+(that is, the EXT is seen at 0)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+ /* the program code is stored in the .text section */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *crt0*.o (.text) /* Startup code */
+ *startup.o (.text) /* Startup code */
+ *(.text) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ _etext = .;
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = _etext ;
+ } >EXTMEMB0
+
+
+
+ /* This is the initialized data section
+ The program executes knowing that the data is in the RAM
+ but the loader puts the initial values in the EXTMEM.
+ It is one task of the startup to copy the initial values from EXTMEMB0 to RAM. */
+ .data : AT ( _etext )
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+
+
+ /* This is the uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ } >RAM
+
+ PROVIDE ( end = _ebss );
+ PROVIDE ( _end = _ebss );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ _eusrstack = ALIGN(4) ;
+ . = .;
+ } >RAM
+
+
+ /* this is the FLASH Bank0 */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+ .fb0text :
+ {
+ *(.fb0text) /* remaining code */
+ *(.fb0rodata) /* read-only data (constants) */
+ *(.fb0rodata*)
+ } >FLASH
+
+ /* this is the FLASH Bank1 */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+ .fb1text :
+ {
+ *(.fb1text) /* remaining code */
+ *(.fb1rodata) /* read-only data (constants) */
+ *(.fb1rodata*)
+ } >FLASHB1
+
+ /* EXTMEM Bank1 */
+ .eb1text :
+ {
+ *(.b1text) /* remaining code */
+ *(.b1rodata) /* read-only data (constants) */
+ *(.b1rodata*)
+ } >EXTMEMB1
+
+ /* EXTMEM Bank2 */
+ .eb2text :
+ {
+ *(.b2text) /* remaining code */
+ *(.b2rodata) /* read-only data (constants) */
+ *(.b2rodata*)
+ } >EXTMEMB2
+
+ /* EXTMEM Bank0 */
+ .eb3text :
+ {
+ *(.b3text) /* remaining code */
+ *(.b3rodata) /* read-only data (constants) */
+ *(.b3rodata*)
+ } >EXTMEMB3
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/STM32_SEC_FLASH.ld b/arm/STM32/template/lib/STM32_SEC_FLASH.ld
new file mode 100644
index 0000000..cd8c4fa
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_FLASH.ld
@@ -0,0 +1,201 @@
+/*
+Common part of the linker scripts for STR71x devices in FLASH mode
+(that is, the FLASH is seen at 0)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
+ .flashtext :
+ {
+ . = ALIGN(4);
+ *(.flashtext) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+
+ /* the program code is stored in the .text section, which goes to Flash */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ _etext = .;
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = _etext;
+ } >FLASH
+
+
+
+ /* This is the initialized data section
+ The program executes knowing that the data is in the RAM
+ but the loader puts the initial values in the FLASH (inidata).
+ It is one task of the startup to copy the initial values from FLASH to RAM. */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+
+
+ /* This is the uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+ } >RAM
+
+ PROVIDE ( end = _ebss );
+ PROVIDE ( _end = _ebss );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ . = ALIGN(4);
+ _eusrstack = . ;
+ } >RAM
+
+
+
+ /* this is the FLASH Bank1 */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+ .b1text :
+ {
+ *(.b1text) /* remaining code */
+ *(.b1rodata) /* read-only data (constants) */
+ *(.b1rodata*)
+ } >FLASHB1
+
+ /* this is the EXTMEM */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+
+ /* EXTMEM Bank0 */
+ .eb0text :
+ {
+ *(.eb0text) /* remaining code */
+ *(.eb0rodata) /* read-only data (constants) */
+ *(.eb0rodata*)
+ } >EXTMEMB0
+
+ /* EXTMEM Bank1 */
+ .eb1text :
+ {
+ *(.eb1text) /* remaining code */
+ *(.eb1rodata) /* read-only data (constants) */
+ *(.eb1rodata*)
+ } >EXTMEMB1
+
+ /* EXTMEM Bank2 */
+ .eb2text :
+ {
+ *(.eb2text) /* remaining code */
+ *(.eb2rodata) /* read-only data (constants) */
+ *(.eb2rodata*)
+ } >EXTMEMB2
+
+ /* EXTMEM Bank0 */
+ .eb3text :
+ {
+ *(.eb3text) /* remaining code */
+ *(.eb3rodata) /* read-only data (constants) */
+ *(.eb3rodata*)
+ } >EXTMEMB3
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/STM32_SEC_RAM.ld b/arm/STM32/template/lib/STM32_SEC_RAM.ld
new file mode 100644
index 0000000..4b44bb2
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_RAM.ld
@@ -0,0 +1,156 @@
+/*
+Common part of the linker scripts for STR71x devices in RAM mode
+(that is, the RAM is seen at 0 and we assume that the loader initializes it)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+/* Sections Definitions */
+
+SECTIONS
+{
+
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to start of RAM */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+ /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
+ .flashtext :
+ {
+ . = ALIGN(4);
+ *(.flashtext) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* the program code is stored in the .text section, which goes to RAM */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *(.text ) /* remaining code */
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ } >RAM
+
+ /* This is the uninitialized data section. */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = . ;
+ _etext = _ebss ;
+
+ } >RAM
+
+
+ /* read-only data (constants) */
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .idata :
+ {
+ _sidata = . ;
+ } > FLASH
+
+
+ /* This is the initialized data section. */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ *(.data)
+ . = ALIGN(4);
+ _edata = . ;
+ } >RAM
+
+
+
+ PROVIDE ( end = _edata );
+ PROVIDE ( _end = _edata );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ . = ALIGN(4);
+ _eusrstack = . ;
+ } >RAM
+
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+/* .debug_info 0 : { * ( EXCLUDE_FILE ( *libc.a *libm.a ) .debug_info .gnu.linkonce.wi.*) }*/
+ .debug_info 0 : { * ( .debug_info .gnu.linkonce.wi.*) }
+/* .debug_abbrev 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_abbrev) }*/
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+/* .debug_line 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_line) }*/
+ .debug_line 0 : { *( .debug_line) }
+ /* (*(EXCLUDE_FILE (*crtend.o *otherfile.o) .ctors)) */
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/STM32_SEC_RAMonly.ld b/arm/STM32/template/lib/STM32_SEC_RAMonly.ld
new file mode 100644
index 0000000..fa90799
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_RAMonly.ld
@@ -0,0 +1,157 @@
+/*
+Common part of the linker scripts for STR71x devices in RAM mode
+(that is, the RAM is seen at 0 and we assume that the loader initializes it)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+/* Sections Definitions */
+
+SECTIONS
+{
+
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to start of RAM */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ *(.isr_vector) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+
+ /* the beginning of the startup code is stored in the .flashtext section */
+ .flashtext :
+ {
+ . = ALIGN(4);
+
+ *crt0*.o (.flashtext) /* Startup code */
+ *startup.o (.flashtext) /* Startup code */
+ *(.flashtext) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+ /* the program code is stored in the .text section */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *crt0*.o (.text) /* Startup code */
+ *startup.o (.text) /* Startup code */
+ *(.text ) /* remaining code */
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ } >RAM
+
+ /* This is the uninitialized data section. */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = . ;
+ _etext = _ebss ;
+
+ } >RAM
+
+
+ /* read-only data (constants) */
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } > RAM
+
+
+ /* This is the initialized data section. */
+ .data :
+ {
+ . = ALIGN(4);
+ _sidata = . ; /*this is useless but allows the same startup as for the other modes to be used.*/
+ _sdata = .;
+ *(.data)
+ . = ALIGN(4);
+ _edata = . ;
+ } >RAM
+
+
+
+ PROVIDE ( end = _edata );
+ PROVIDE ( _end = _edata );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ . = ALIGN(4);
+ _eusrstack = . ;
+ } >RAM
+
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+/* .debug_info 0 : { * ( EXCLUDE_FILE ( *libc.a *libm.a ) .debug_info .gnu.linkonce.wi.*) }*/
+ .debug_info 0 : { * ( .debug_info .gnu.linkonce.wi.*) }
+/* .debug_abbrev 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_abbrev) }*/
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+/* .debug_line 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_line) }*/
+ .debug_line 0 : { *( .debug_line) }
+ /* (*(EXCLUDE_FILE (*crtend.o *otherfile.o) .ctors)) */
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/inc/cortexm3_macro.h b/arm/STM32/template/lib/inc/cortexm3_macro.h
new file mode 100644
index 0000000..822d019
--- /dev/null
+++ b/arm/STM32/template/lib/inc/cortexm3_macro.h
@@ -0,0 +1,51 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : cortexm3_macro.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : Header file for cortexm3_macro.s.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void __WFI(void);
+void __WFE(void);
+void __SEV(void);
+void __ISB(void);
+void __DSB(void);
+void __DMB(void);
+void __SVC(void);
+u32 __MRS_CONTROL(void);
+void __MSR_CONTROL(u32 Control);
+u32 __MRS_PSP(void);
+void __MSR_PSP(u32 TopOfProcessStack);
+u32 __MRS_MSP(void);
+void __MSR_MSP(u32 TopOfMainStack);
+void __SETPRIMASK(void);
+void __RESETPRIMASK(void);
+void __SETFAULTMASK(void);
+void __RESETFAULTMASK(void);
+void __BASEPRICONFIG(u32 NewPriority);
+u32 __GetBASEPRI(void);
+u16 __REV_HalfWord(u16 Data);
+u32 __REV_Word(u32 Data);
+
+#endif /* __CORTEXM3_MACRO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_adc.h b/arm/STM32/template/lib/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..452d04e
--- /dev/null
+++ b/arm/STM32/template/lib/inc/stm32f10x_adc.h
@@ -0,0 +1,265 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_adc.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the functions prototypes for the
+* ADC firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* ADC Init structure definition */
+typedef struct
+{
+ u32 ADC_Mode;
+ FunctionalState ADC_ScanConvMode;
+ FunctionalState ADC_ContinuousConvMode;
+ u32 ADC_ExternalTrigConv;
+ u32 ADC_DataAlign;
+ u8 ADC_NbrOfChannel;
+}ADC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ADC dual mode -------------------------------------------------------------*/
+#define ADC_Mode_Independent ((u32)0x00000000)
+#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
+#define ADC_Mode_InjecSimult ((u32)0x00050000)
+#define ADC_Mode_RegSimult ((u32)0x00060000)
+#define ADC_Mode_FastInterl ((u32)0x00070000)
+#define ADC_Mode_SlowInterl ((u32)0x00080000)
+#define ADC_Mode_AlterTrig ((u32)0x00090000)
+
+#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
+ (MODE == ADC_Mode_RegInjecSimult) || \
+ (MODE == ADC_Mode_RegSimult_AlterTrig) || \
+ (MODE == ADC_Mode_InjecSimult_FastInterl) || \
+ (MODE == ADC_Mode_InjecSimult_SlowInterl) || \
+ (MODE == ADC_Mode_InjecSimult) || \
+ (MODE == ADC_Mode_RegSimult) || \
+ (MODE == ADC_Mode_FastInterl) || \
+ (MODE == ADC_Mode_SlowInterl) || \
+ (MODE == ADC_Mode_AlterTrig))
+
+/* ADC extrenal trigger sources for regular channels conversion --------------*/
+#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
+#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
+#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)
+#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
+
+#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
+ (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
+ (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
+ (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
+ (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
+ (TRIG1 == ADC_ExternalTrigConv_None))
+
+/* ADC data align ------------------------------------------------------------*/
+#define ADC_DataAlign_Right ((u32)0x00000000)
+#define ADC_DataAlign_Left ((u32)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
+ (ALIGN == ADC_DataAlign_Left))
+
+/* ADC channels --------------------------------------------------------------*/
+#define ADC_Channel_0 ((u8)0x00)
+#define ADC_Channel_1 ((u8)0x01)
+#define ADC_Channel_2 ((u8)0x02)
+#define ADC_Channel_3 ((u8)0x03)
+#define ADC_Channel_4 ((u8)0x04)
+#define ADC_Channel_5 ((u8)0x05)
+#define ADC_Channel_6 ((u8)0x06)
+#define ADC_Channel_7 ((u8)0x07)
+#define ADC_Channel_8 ((u8)0x08)
+#define ADC_Channel_9 ((u8)0x09)
+#define ADC_Channel_10 ((u8)0x0A)
+#define ADC_Channel_11 ((u8)0x0B)
+#define ADC_Channel_12 ((u8)0x0C)
+#define ADC_Channel_13 ((u8)0x0D)
+#define ADC_Channel_14 ((u8)0x0E)
+#define ADC_Channel_15 ((u8)0x0F)
+#define ADC_Channel_16 ((u8)0x10)
+#define ADC_Channel_17 ((u8)0x11)
+
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
+ (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
+ (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
+ (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
+ (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
+ (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
+ (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
+ (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
+ (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
+
+/* ADC sampling times --------------------------------------------------------*/
+#define ADC_SampleTime_1Cycles5 ((u8)0x00)
+#define ADC_SampleTime_7Cycles5 ((u8)0x01)
+#define ADC_SampleTime_13Cycles5 ((u8)0x02)
+#define ADC_SampleTime_28Cycles5 ((u8)0x03)
+#define ADC_SampleTime_41Cycles5 ((u8)0x04)
+#define ADC_SampleTime_55Cycles5 ((u8)0x05)
+#define ADC_SampleTime_71Cycles5 ((u8)0x06)
+#define ADC_SampleTime_239Cycles5 ((u8)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
+ (TIME == ADC_SampleTime_7Cycles5) || \
+ (TIME == ADC_SampleTime_13Cycles5) || \
+ (TIME == ADC_SampleTime_28Cycles5) || \
+ (TIME == ADC_SampleTime_41Cycles5) || \
+ (TIME == ADC_SampleTime_55Cycles5) || \
+ (TIME == ADC_SampleTime_71Cycles5) || \
+ (TIME == ADC_SampleTime_239Cycles5))
+
+/* ADC extrenal trigger sources for injected channels conversion -------------*/
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)
+#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
+
+#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
+ (TRIG == ADC_ExternalTrigInjecConv_None))
+
+/* ADC injected channel selection --------------------------------------------*/
+#define ADC_InjectedChannel_1 ((u8)0x14)
+#define ADC_InjectedChannel_2 ((u8)0x18)
+#define ADC_InjectedChannel_3 ((u8)0x1C)
+#define ADC_InjectedChannel_4 ((u8)0x20)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
+ (CHANNEL == ADC_InjectedChannel_2) || \
+ (CHANNEL == ADC_InjectedChannel_3) || \
+ (CHANNEL == ADC_InjectedChannel_4))
+
+/* ADC analog watchdog selection ---------------------------------------------*/
+#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
+#define ADC_AnalogWatchdog_None ((u32)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_None))
+
+/* ADC interrupts definition -------------------------------------------------*/
+#define ADC_IT_EOC ((u16)0x0220)
+#define ADC_IT_AWD ((u16)0x0140)
+#define ADC_IT_JEOC ((u16)0x0480)
+
+#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
+#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
+ (IT == ADC_IT_JEOC))
+
+/* ADC flags definition ------------------------------------------------------*/
+#define ADC_FLAG_AWD ((u8)0x01)
+#define ADC_FLAG_EOC ((u8)0x02)
+#define ADC_FLAG_JEOC ((u8)0x04)
+#define ADC_FLAG_JSTRT ((u8)0x08)
+#define ADC_FLAG_STRT ((u8)0x10)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
+ (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
+ (FLAG == ADC_FLAG_STRT))
+
+/* ADC thresholds ------------------------------------------------------------*/
+#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
+
+/* ADC injected offset -------------------------------------------------------*/
+#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
+
+/* ADC injected length -------------------------------------------------------*/
+#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
+
+/* ADC injected rank ---------------------------------------------------------*/
+#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
+
+/* ADC regular length --------------------------------------------------------*/
+#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
+
+/* ADC regular rank ----------------------------------------------------------*/
+#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
+
+/* ADC regular discontinuous mode number -------------------------------------*/
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
+u32 ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
+
+#endif /*__STM32F10x_ADC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_bkp.h b/arm/STM32/template/lib/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..79e702f
--- /dev/null
+++ b/arm/STM32/template/lib/inc/stm32f10x_bkp.h
@@ -0,0 +1,80 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_bkp.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the functions prototypes for the
+* BKP firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Tamper Pin active level */
+#define BKP_TamperPinLevel_High ((u16)0x0000)
+#define BKP_TamperPinLevel_Low ((u16)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \
+ (LEVEL == BKP_TamperPinLevel_Low))
+
+/* RTC output source to output on the Tamper pin */
+#define BKP_RTCOutputSource_None ((u16)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
+#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
+#define BKP_RTCOutputSource_Second ((u16)0x0300)
+
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) ((SOURCE == BKP_RTCOutputSource_None) || \
+ (SOURCE == BKP_RTCOutputSource_CalibClock) || \
+ (SOURCE == BKP_RTCOutputSource_Alarm) || \
+ (SOURCE == BKP_RTCOutputSource_Second))
+
+/* Data Backup Register */
+#define BKP_DR1 ((u16)0x0004)
+#define BKP_DR2 ((u16)0x0008)
+#define BKP_DR3 ((u16)0x000C)
+#define BKP_DR4 ((u16)0x0010)
+#define BKP_DR5 ((u16)0x0014)
+#define BKP_DR6 ((u16)0x0018)
+#define BKP_DR7 ((u16)0x001C)
+#define BKP_DR8 ((u16)0x0020)
+#define BKP_DR9 ((u16)0x0024)
+#define BKP_DR10 ((u16)0x0028)
+
+#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \
+ (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \
+ (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \
+ (DR == BKP_DR10))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
+u16 BKP_ReadBackupRegister(u16 BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#endif /* __STM32F10x_BKP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_can.h b/arm/STM32/template/lib/inc/stm32f10x_can.h
new file mode 100644
index 0000000..a8c170d
--- /dev/null
+++ b/arm/STM32/template/lib/inc/stm32f10x_can.h
@@ -0,0 +1,263 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_can.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the functions prototypes for the
+* CAN firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* CAN init structure definition */
+typedef struct
+{
+ FunctionalState CAN_TTCM;
+ FunctionalState CAN_ABOM;
+ FunctionalState CAN_AWUM;
+ FunctionalState CAN_NART;
+ FunctionalState CAN_RFLM;
+ FunctionalState ...
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