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[Krobot-resources] [SCM] krobot-resources branch, master, updated. ba642d9142f0b7a05347e682bb0f3add311919ea
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From: Xavier L. <Sup...@us...> - 2010-01-16 20:57:24
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- Log -----------------------------------------------------------------
commit ba642d9142f0b7a05347e682bb0f3add311919ea
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 21:52:10 2010 +0100
Adding an usage example of the driver_7seg and decoder_7seg components
commit be079913ec09e057766a1a94f70f3faeaf5be832
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 21:48:05 2010 +0100
Added comments in the files and corrected some errors in the design.
This version of the driver is operational
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/decoder_7seg.vhd b/fpga/components/decoder_7seg.vhd
index dcf698b..b39ea79 100644
--- a/fpga/components/decoder_7seg.vhd
+++ b/fpga/components/decoder_7seg.vhd
@@ -19,16 +19,16 @@ use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_7seg is
- port(val : in std_logic_vector(3 downto 0);
- pti : in std_logic;
- a : out std_logic;
- b : out std_logic;
- c : out std_logic;
- d : out std_logic;
- e : out std_logic;
- f : out std_logic;
- g : out std_logic;
- pt : out std_logic
+ port(val : in std_logic_vector(3 downto 0); -- BCD value to decode
+ pti : in std_logic; -- Decimal point
+ a : out std_logic; -- Decoded segment
+ b : out std_logic; -- "
+ c : out std_logic; -- "
+ d : out std_logic; -- "
+ e : out std_logic; -- "
+ f : out std_logic; -- "
+ g : out std_logic; -- "
+ pt : out std_logic -- "
);
end decoder_7seg;
@@ -37,126 +37,126 @@ begin
process(val, pti)
begin
case val is
- when "0000" => a <= '1'; -- 0
- b <= '1';
- c <= '1';
- d <= '1';
- e <= '1';
- f <= '1';
- g <= '0';
- when "0001" => a <= '0'; -- 1
- b <= '1';
- c <= '1';
+ when "0000" => a <= '0'; -- 0
+ b <= '0';
+ c <= '0';
d <= '0';
e <= '0';
f <= '0';
- g <= '0';
- when "0010" => a <= '1'; -- 2
- b <= '1';
+ g <= '1';
+ when "0001" => a <= '1'; -- 1
+ b <= '0';
c <= '0';
d <= '1';
e <= '1';
- f <= '0';
- g <= '1';
- when "0011" => a <= '1'; -- 3
- b <= '1';
- c <= '1';
- d <= '1';
- e <= '0';
- f <= '0';
+ f <= '1';
g <= '1';
- when "0100" => a <= '0'; -- 4
- b <= '1';
+ when "0010" => a <= '0'; -- 2
+ b <= '0';
c <= '1';
d <= '0';
e <= '0';
f <= '1';
- g <= '1';
- when "0101" => a <= '1'; -- 5
+ g <= '0';
+ when "0011" => a <= '0'; -- 3
b <= '0';
- c <= '1';
- d <= '1';
- e <= '0';
+ c <= '0';
+ d <= '0';
+ e <= '1';
f <= '1';
- g <= '1';
- when "0110" => a <= '1'; -- 6
+ g <= '0';
+ when "0100" => a <= '1'; -- 4
b <= '0';
- c <= '1';
+ c <= '0';
d <= '1';
e <= '1';
- f <= '1';
- g <= '1';
- when "0111" => a <= '1'; -- 7
- b <= '1';
- c <= '1';
- d <= '0';
- e <= '0';
f <= '0';
g <= '0';
- when "1000" => a <= '1'; -- 8
+ when "0101" => a <= '0'; -- 5
b <= '1';
- c <= '1';
- d <= '1';
+ c <= '0';
+ d <= '0';
e <= '1';
- f <= '1';
- g <= '1';
- when "1001" => a <= '1'; -- 9
- b <= '1';
- c <= '1';
- d <= '1';
- e <= '0';
- f <= '1';
- g <= '1';
- when "1010" => a <= '1'; -- A
+ f <= '0';
+ g <= '0';
+ when "0110" => a <= '0'; -- 6
b <= '1';
- c <= '1';
+ c <= '0';
d <= '0';
- e <= '1';
- f <= '1';
- g <= '1';
- when "1011" => a <= '0'; -- B
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "0111" => a <= '0'; -- 7
b <= '0';
- c <= '1';
+ c <= '0';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
- when "1100" => a <= '1'; -- C
+ when "1000" => a <= '0'; -- 8
b <= '0';
c <= '0';
- d <= '1';
- e <= '1';
- f <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
g <= '0';
- when "1101" => a <= '0'; -- D
- b <= '1';
- c <= '1';
- d <= '1';
+ when "1001" => a <= '0'; -- 9
+ b <= '0';
+ c <= '0';
+ d <= '0';
e <= '1';
f <= '0';
- g <= '1';
- when "1110" => a <= '1'; -- E
+ g <= '0';
+ when "1010" => a <= '0'; -- A
b <= '0';
c <= '0';
d <= '1';
- e <= '1';
- f <= '1';
- g <= '1';
- when "1111" => a <= '1'; -- F
- b <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1011" => a <= '1'; -- B
+ b <= '1';
c <= '0';
d <= '0';
- e <= '1';
- f <= '1';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1100" => a <= '0'; -- C
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
g <= '1';
- when others => a <= '0'; -- shouldn't happen
+ when "1101" => a <= '1'; -- D
b <= '0';
c <= '0';
d <= '0';
e <= '0';
+ f <= '1';
+ g <= '0';
+ when "1110" => a <= '0'; -- E
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1111" => a <= '0'; -- F
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '0';
f <= '0';
g <= '0';
+ when others => a <= '1'; -- shouldn't happen
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '1';
end case;
end process;
- pt <= pti;
+ pt <= pti; -- don't need to decode the decimal point
end hexa_dec;
diff --git a/fpga/components/driver_7seg.vhd b/fpga/components/driver_7seg.vhd
index 4f1a551..b2293f5 100644
--- a/fpga/components/driver_7seg.vhd
+++ b/fpga/components/driver_7seg.vhd
@@ -24,17 +24,17 @@ entity driver_7seg is
dok : in STD_LOGIC; -- data OK
oe : in STD_LOGIC; -- output enable
a : out STD_LOGIC; -- segments
- b : out STD_LOGIC; -- ...
- c : out STD_LOGIC; -- ...
- d : out STD_LOGIC; -- ...
- e : out STD_LOGIC; -- ...
- f : out STD_LOGIC; -- ...
- g : out STD_LOGIC; -- ...
+ b : out STD_LOGIC; -- "
+ c : out STD_LOGIC; -- "
+ d : out STD_LOGIC; -- "
+ e : out STD_LOGIC; -- "
+ f : out STD_LOGIC; -- "
+ g : out STD_LOGIC; -- "
dp : out STD_LOGIC; -- decimal point
an0 : out STD_LOGIC; -- number selection
- an1 : out STD_LOGIC; -- ...
- an2 : out STD_LOGIC; -- ...
- an3 : out STD_LOGIC -- ...
+ an1 : out STD_LOGIC; -- "
+ an2 : out STD_LOGIC; -- "
+ an3 : out STD_LOGIC -- "
);
end driver_7seg;
@@ -58,22 +58,22 @@ signal display_state : std_logic_vector(1 downto 0);
signal output : std_logic_vector(7 downto 0);
-- Description
begin
- -- Multiplex to link the internal memories to the display
+ -- Multiplexer to link the internal memories to the display
display_mux : mux8_4 port map(display_state, val1, val2, val3, val4, output);
-- Link output of the multiplexer to the output lines going to the display
- a <= output(0);
- b <= output(1);
- c <= output(2);
- d <= output(3);
- e <= output(4);
- f <= output(5);
- g <= output(6);
- dp <= output(7);
+ a <= output(7);
+ b <= output(6);
+ c <= output(5);
+ d <= output(4);
+ e <= output(3);
+ f <= output(2);
+ g <= output(1);
+ dp <= output(0);
-- Display scanning
process (clk)
begin
if (clk'event and clk = '1') then
- if (oe = '1') then
+ if (oe = '1') then -- let's refresh if output is enabled
case display_state is
when "00" => display_state <= "01";
an0 <= '1';
@@ -102,7 +102,7 @@ begin
an3 <= '1';
end case;
else
- an0 <= '1';
+ an0 <= '1'; -- don't refresh if output disabled
an1 <= '1';
an2 <= '1';
an3 <= '1';
@@ -118,7 +118,7 @@ begin
when "01" => val2 <= data;
when "10" => val3 <= data;
when "11" => val4 <= data;
- when others => null;
+ when others => val1 <= data; -- shouldn't happen
end case;
end if;
end process;
diff --git a/fpga/examples/example_driver_7segs.ucf b/fpga/examples/example_driver_7segs.ucf
new file mode 100644
index 0000000..b125f1a
--- /dev/null
+++ b/fpga/examples/example_driver_7segs.ucf
@@ -0,0 +1,46 @@
+-- UCF file for the Nexys 2 board
+-- This file is associated to the example_driver_7segs.vhd design
+
+-- Clock input
+NET "clk" LOC = "B8";
+
+-- LEDs
+NET "Led<0>" LOC = "J14";
+NET "Led<1>" LOC = "J15";
+NET "Led<2>" LOC = "K15";
+NET "Led<3>" LOC = "K14";
+NET "Led<4>" LOC = "E16";
+NET "Led<5>" LOC = "P16";
+NET "Led<6>" LOC = "E4";
+NET "Led<7>" LOC = "P4";
+
+-- 7 segments display
+NET "a" LOC = "L18";
+NET "b" LOC = "F18";
+NET "c" LOC = "D17";
+NET "d" LOC = "D16";
+NET "e" LOC = "G14";
+NET "f" LOC = "J17";
+NET "g" LOC = "H14";
+NET "dp" LOC = "C17";
+
+NET "an0" LOC = "F17";
+NET "an1" LOC = "H17";
+NET "an2" LOC = "C18";
+NET "an3" LOC = "F15";
+
+-- Switches
+NET "sw<0>" LOC = "G18";
+NET "sw<1>" LOC = "H18";
+NET "sw<2>" LOC = "K18";
+NET "sw<3>" LOC = "K17";
+NET "sw<4>" LOC = "L14";
+NET "sw<5>" LOC = "L13";
+NET "sw<6>" LOC = "N17";
+NET "sw<7>" LOC = "R17";
+
+-- Buttons
+NET "btn<0>" LOC = "B18";
+NET "btn<1>" LOC = "D18";
+NET "btn<2>" LOC = "E18";
+NET "btn<3>" LOC = "H13";
diff --git a/fpga/examples/example_driver_7segs.vhd b/fpga/examples/example_driver_7segs.vhd
new file mode 100644
index 0000000..4e826fc
--- /dev/null
+++ b/fpga/examples/example_driver_7segs.vhd
@@ -0,0 +1,143 @@
+----------------------------------------------------------------------------------
+-- Create Date: 16/01/2010
+-- Module Name: example_driver_7segs
+-- Authors : X. Lagorce
+-- Description: Example for the 7 segments display
+-- This file shows the use of the driver_7seg and decoder_7seg
+-- components.
+--
+-- Dependencies: driver_7seg, decoder_7seg, div_clk
+--
+-- Revision:
+-- Revision 0.1 : First implementation
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity example_driver_7segs is
+ port( clk : in STD_LOGIC; -- refresh clock
+ a : out STD_LOGIC; -- segments
+ b : out STD_LOGIC; -- "
+ c : out STD_LOGIC; -- "
+ d : out STD_LOGIC; -- "
+ e : out STD_LOGIC; -- "
+ f : out STD_LOGIC; -- "
+ g : out STD_LOGIC; -- "
+ dp : out STD_LOGIC; -- decimal point
+ an0 : out STD_LOGIC; -- number selection
+ an1 : out STD_LOGIC; -- "
+ an2 : out STD_LOGIC; -- "
+ an3 : out STD_LOGIC; -- "
+ btn : in STD_LOGIC_VECTOR(3 downto 0);
+ sw : in STD_LOGIC_VECTOR(7 downto 0);
+ led : out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end example_driver_7segs;
+
+architecture Behavioral of example_driver_7segs is
+-- Components declarations
+ component driver_7seg is
+ port( clk : in STD_LOGIC; -- refresh clock
+ data : in STD_LOGIC_VECTOR(7 downto 0); -- segments + decimal point
+ add : in STD_LOGIC_VECTOR(1 downto 0); -- segment address
+ dok : in STD_LOGIC; -- data OK
+ oe : in STD_LOGIC; -- output enable
+ a : out STD_LOGIC; -- segments
+ b : out STD_LOGIC; -- "
+ c : out STD_LOGIC; -- "
+ d : out STD_LOGIC; -- "
+ e : out STD_LOGIC; -- "
+ f : out STD_LOGIC; -- "
+ g : out STD_LOGIC; -- "
+ dp : out STD_LOGIC; -- decimal point
+ an0 : out STD_LOGIC; -- number selection
+ an1 : out STD_LOGIC; -- "
+ an2 : out STD_LOGIC; -- "
+ an3 : out STD_LOGIC -- "
+ );
+ end component;
+ component div_clk is
+ Port (clkin : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ clkout1 : out STD_LOGIC; -- 1.49 Hz
+ clkout2 : out STD_LOGIC; -- 763 Hz
+ clkout3 : out STD_LOGIC; -- 98 kHz
+ clkout4 : out STD_LOGIC); -- 1.56 MHz
+ end component;
+ component decoder_7seg is
+ port(val : in std_logic_vector(3 downto 0);
+ pti : in std_logic;
+ a : out std_logic;
+ b : out std_logic;
+ c : out std_logic;
+ d : out std_logic;
+ e : out std_logic;
+ f : out std_logic;
+ g : out std_logic;
+ pt : out std_logic
+ );
+ end component;
+ for all : driver_7seg use entity work.driver_7seg(Behavioral);
+ for all : div_clk use entity work.div_clk(Behavioral);
+ for all : decoder_7seg use entity work.decoder_7seg(hexa_dec);
+-- Signals declarations
+ signal data : std_logic_vector(7 downto 0);
+ signal add : std_logic_vector(1 downto 0);
+ signal val : std_logic_vector(3 downto 0);
+ signal dok, oe, reset, clk1, clk2, clk3, clk4 : std_logic;
+ signal ad, bd, cd, dd, ed, ffd, gd, ptd, pti : std_logic;
+-- Description
+begin
+ -- Components declarations
+ -- Let's get some slower clocks
+ div : div_clk port map (clk, reset, clk1, clk2, clk3, clk4);
+ -- The display driver
+ driver : driver_7seg port map (clk2, data, add, dok, oe, a, b, c,
+ d, e, f, g, dp, an0, an1, an2, an3);
+ -- component to decode BCD to 7 segments pattern
+ decoder : decoder_7seg port map (val, pti, ad, bd, cd, dd, ed,
+ ffd, gd, ptd);
+ -- Internal signals assignations
+ data(7) <= ad; -- vectorisation of the segments signals
+ data(6) <= bd;
+ data(5) <= cd;
+ data(4) <= dd;
+ data(3) <= ed;
+ data(2) <= ffd; -- fd is a keywork to add a Verilog
+ -- component in a VHDL design
+ data(1) <= gd;
+ data(0) <= ptd;
+
+ val <= sw(3 downto 0); -- enter a value on these switches
+ oe <= sw(4); -- this switch enables the output
+ pti <= sw(5); -- Decimal point
+
+ led(3 downto 0) <= val; -- display the value on LEDs
+ led(4) <= clk1; -- "I'm alive !" blinky
+ led(5) <= dok; -- Data OK signal
+ led(7 downto 6) <= add; -- Addressed display
+
+ reset <= '0'; -- Never reset the clock divider
+
+ -- Loading values into the driver
+ -- This process generates the address accordingly to the switch pressed
+ process (btn)
+ begin
+ case btn is
+ when "0001" => add <= "00";
+ dok <= '1';
+ when "0010" => add <= "01";
+ dok <= '1';
+ when "0100" => add <= "10";
+ dok <= '1';
+ when "1000" => add <= "11";
+ dok <= '1';
+ when others => add <= "00";
+ dok <= '0';
+ end case;
+ end process;
+end Behavioral;
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