[Krobot-resources] [SCM] krobot-resources branch, master, updated. 39a9f01750a2a5da1e6b085fcac4fb4a4d12b509

[Xavier L. <Sup...@us...>]

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- Log -----------------------------------------------------------------
commit 39a9f01750a2a5da1e6b085fcac4fb4a4d12b509
Author: Xavier Lagorce <Xav...@cr...>
Date:   Sat Jan 16 17:32:03 2010 +0100

    Modification des coefficients de division pour prendre en compte l'horloge
    réelle de la carte

-----------------------------------------------------------------------

Changes:
diff --git a/fpga/components/div_clk.vhd b/fpga/components/div_clk.vhd
index 355d385..59d09e4 100644
--- a/fpga/components/div_clk.vhd
+++ b/fpga/components/div_clk.vhd
@@ -19,25 +19,25 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity div_clk is
   Port (clkin   :  in  STD_LOGIC;
         reset   :  in  STD_LOGIC;
-        clkout1 : out  STD_LOGIC;  -- 1.19  Hz
-        clkout2 : out  STD_LOGIC;  -- 153   Hz
-        clkout3 : out  STD_LOGIC;  -- 78   kHz
-        clkout4 : out  STD_LOGIC); -- 1.25 MHz
+        clkout1 : out  STD_LOGIC;  -- 1.49  Hz
+        clkout2 : out  STD_LOGIC;  -- 763   Hz
+        clkout3 : out  STD_LOGIC;  -- 98   kHz
+        clkout4 : out  STD_LOGIC); -- 1.56 MHz
 end div_clk;
 
 architecture Behavioral of div_clk is
-  signal compt : std_logic_vector(23 downto 0);
+  signal compt : std_logic_vector(26 downto 0);
 begin
   process (clkin, reset)
   begin
     if (reset = '1') then
-      compt <= "000000000000000000000000";
+      compt <= "000000000000000000000000000";
     elsif (clkin'event and clkin = '1') then
       compt <= compt + 1;
     end if;
   end process;
-  clkout1 <= compt(23);
-  clkout2 <= compt(16);
-  clkout3 <= compt(7);
-  clkout4 <= compt(4);
+  clkout1 <= compt(26);
+  clkout2 <= compt(17);
+  clkout3 <= compt(11);
+  clkout4 <= compt(6);
 end Behavioral;


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