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From: Xavier L. <Sup...@us...> - 2010-01-15 22:25:50
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from dd33d9d9d64f8d99756af9ec22019c996a2dcbc4 (commit)
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- Log -----------------------------------------------------------------
commit 9eb0bf1daac3d4a94cf8c181825e4528c49ab713
Author: Xavier Lagorce <Xav...@cr...>
Date: Fri Jan 15 23:25:23 2010 +0100
Correction d'une erreur et accélération de l'horloge pour le driver PS2
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/div_clk.vhd b/fpga/components/div_clk.vhd
index ac8d65a..355d385 100644
--- a/fpga/components/div_clk.vhd
+++ b/fpga/components/div_clk.vhd
@@ -21,22 +21,23 @@ entity div_clk is
reset : in STD_LOGIC;
clkout1 : out STD_LOGIC; -- 1.19 Hz
clkout2 : out STD_LOGIC; -- 153 Hz
- clkout3 : out STD_LOGIC; -- 19.5 kHz
+ clkout3 : out STD_LOGIC; -- 78 kHz
clkout4 : out STD_LOGIC); -- 1.25 MHz
+end div_clk;
- architecture Behavioral of div_clk is
- signal compt : std_logic_vector(23 downto 0);
+architecture Behavioral of div_clk is
+ signal compt : std_logic_vector(23 downto 0);
+begin
+ process (clkin, reset)
begin
- process (clkin, reset)
- begin
- if (reset = '1') then
- compt <= "000000000000000000000000";
- elsif (clkin'event and clkin = '1') then
- compt <= compt + 1;
- end if;
- end process;
- clkout1 <= compt(23);
- clkout2 <= compt(16);
- clkout3 <= compt(9);
- clkout4 <= compt(4);
- end Behavioral;
+ if (reset = '1') then
+ compt <= "000000000000000000000000";
+ elsif (clkin'event and clkin = '1') then
+ compt <= compt + 1;
+ end if;
+ end process;
+ clkout1 <= compt(23);
+ clkout2 <= compt(16);
+ clkout3 <= compt(7);
+ clkout4 <= compt(4);
+end Behavioral;
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--
UNNAMED PROJECT
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