[Krobot-resources] [SCM] UNNAMED PROJECT branch, master, updated. dd33d9d9d64f8d99756af9ec22019c996a2dcbc4

[Xavier L. <Sup...@us...>]

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- Log -----------------------------------------------------------------
commit dd33d9d9d64f8d99756af9ec22019c996a2dcbc4
Author: Xavier Lagorce <Xav...@cr...>
Date:   Fri Jan 15 23:14:04 2010 +0100

    Ajout d'un composant diviseur d'horloge

-----------------------------------------------------------------------

Changes:
diff --git a/fpga/components/div_clk.vhd b/fpga/components/div_clk.vhd
new file mode 100644
index 0000000..ac8d65a
--- /dev/null
+++ b/fpga/components/div_clk.vhd
@@ -0,0 +1,42 @@
+----------------------------------------------------------------------------------
+-- Create Date: 15/01/2010 
+-- Module Name: div_clk - Behavioral
+-- Authors    : X. Lagorce
+-- Description: Clock divider with multiple outputs
+--
+-- Dependencies: /
+--
+-- Revision: 
+-- Revision 0.1 : Simple implementation
+-- Additional Comments: This should use integrated clock circuits
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity div_clk is
+  Port (clkin   :  in  STD_LOGIC;
+        reset   :  in  STD_LOGIC;
+        clkout1 : out  STD_LOGIC;  -- 1.19  Hz
+        clkout2 : out  STD_LOGIC;  -- 153   Hz
+        clkout3 : out  STD_LOGIC;  -- 19.5 kHz
+        clkout4 : out  STD_LOGIC); -- 1.25 MHz
+
+  architecture Behavioral of div_clk is
+    signal compt : std_logic_vector(23 downto 0);
+  begin
+    process (clkin, reset)
+    begin
+      if (reset = '1') then
+        compt <= "000000000000000000000000";
+      elsif (clkin'event and clkin = '1') then
+        compt <= compt + 1;
+      end if;
+    end process;
+    clkout1 <= compt(23);
+    clkout2 <= compt(16);
+    clkout3 <= compt(9);
+    clkout4 <= compt(4);
+  end Behavioral;


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