Menu
▾
▴
krobot-resources — resources commits
You can subscribe to this list here.
| 2010 |
Jan
(18) |
Feb
|
Mar
|
Apr
(3) |
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2011 |
Jan
(1) |
Feb
|
Mar
(2) |
Apr
(1) |
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2012 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|
From: Nicolas D. <Sup...@us...> - 2012-01-07 13:40:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 0ae525387ae08ed38daf3d3199be651f3bda4fa7 (commit)
from fed6bc0cba773c21980fa79904a344fb521b2879 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0ae525387ae08ed38daf3d3199be651f3bda4fa7
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Sat Jan 7 14:39:18 2012 +0100
[build-arm-toolchain] update
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/build-arm-toolchain b/arm/STM32/build-arm-toolchain
index cf041b3..95d6ddf 100755
--- a/arm/STM32/build-arm-toolchain
+++ b/arm/STM32/build-arm-toolchain
@@ -6,36 +6,32 @@ HOST=i686-linux-gnu # Or: HOST=x86_64-linux-gnu
PREFIX=/home/nicolasd/opt/arm-i386 # Install location of your final toolchain
echo "HOST is \`$HOST', PREFIX is \`$PREFIX'."
-echo
-echo "/!\\ USE A DEFINITIVE PREFIX, GCC IS NOT RELOCATABLE! /!\\"
-echo
-echo "Make sure this is okay and remove the exit 1 line in the script."
-exit 1
TARGET=arm-none-eabi # Or: TARGET=arm-elf
PARALLEL="-j3" # Or: PARALLEL=""
-BINUTILS=binutils-2.21
-GCC=gcc-4.5.2
+BINUTILS=binutils-2.22
+GCC=gcc-4.6.2
NEWLIB=newlib-1.19.0
-GDB=gdb-7.2
+GDB=gdb-7.3.1
export PATH="$PATH:$PREFIX/bin"
mkdir build
-wget -c http://ftp.gnu.org/gnu/binutils/$BINUTILS.tar.bz2
-tar xfvj $BINUTILS.tar.bz2
+wget -c http://ftp.crans.org/debian/pool/main/b/binutils/${BINUTILS/-/_}.orig.tar.gz
+tar xfvz binutils*.orig.tar.gz
cd build
../$BINUTILS/configure --target=$TARGET --prefix=$PREFIX --with-sysroot=$PREFIX --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls
make $PARALLEL
make install
cd ..
rm -rf build/
+
mkdir build
wget -c ftp://ftp.gnu.org/gnu/gcc/$GCC/$GCC.tar.bz2
-tar xfvj $GCC.tar.bz2
+tar xfvj $GCC.tar.bz2
cd build
-../$GCC/configure --target=$TARGET --prefix=$PREFIX --with-sysroot=$PREFIX --enable-interwork --enable-multilib --enable-languages="c" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --disable-libssp --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb
+../$GCC/configure --target=$TARGET --prefix=$PREFIX --with-sysroot=$PREFIX --enable-interwork --enable-multilib --enable-languages="c" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --disable-libssp --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb
make $PARALLEL all-gcc
make install-gcc
cd ..
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2011-04-03 17:00:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via fed6bc0cba773c21980fa79904a344fb521b2879 (commit)
from 0d945464874b53fdc04d37e7e07ae8cf8c66f5bf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit fed6bc0cba773c21980fa79904a344fb521b2879
Author: chambart <cha...@cr...>
Date: Sun Apr 3 18:58:16 2011 +0200
[bezier] create the directory, create some code to do computation for the robot
-----------------------------------------------------------------------
Changes:
diff --git a/bezier/compute_optimal_bezier.ml b/bezier/compute_optimal_bezier.ml
new file mode 100644
index 0000000..0650da1
--- /dev/null
+++ b/bezier/compute_optimal_bezier.ml
@@ -0,0 +1,177 @@
+let ( +| ) (x1,y1) (x2,y2) = x1 +. x2, y1 +. y2
+let ( -| ) (x1,y1) (x2,y2) = x1 -. x2, y1 -. y2
+let norm (x,y) = sqrt (x**2. +. y**2.)
+let normalize (x,y) =
+ let n = sqrt (x**2. +. y**2.) in
+ (x /. n, y /. n)
+let prod_vect (x1,y1) (x2,y2) = (x1 *. x2) +. (y1 *. y2)
+let prod_scal r (x1,y1) = (r *. x1), (r *. y1)
+let rotation_trigo_pi_over_2 (x,y) = (-.y,x)
+
+type bezier_f =
+ { a0 : float; a1 : float; a2 : float; a3 : float }
+
+type bezier_2d =
+ { cx : bezier_f; cy : bezier_f }
+
+type robot =
+ { r_width : float; (* distance between wheels: m *)
+ r_max_wheel_speed : float; (* m / s *)
+ r_max_a : float; } (* m / s^2 *)
+
+let epsilon = 0.00001
+
+let check_u u =
+ if ( u <= 0. -. epsilon && u >= 1. +. epsilon )
+ then failwith (Printf.sprintf "cacaaa: %f" u)
+ else ()
+
+let compute ~u b =
+ check_u u;
+ b.a0 *. ( ( 1. -. u ) ** 3. ) +. 3.*.b.a1*.u*.((1.-.u) ** 2.) +. 3. *. b.a2*.(1.-.u)*.( (u)**2. ) +. b.a3 *. ( (u) ** 3. )
+
+let df ~u b =
+ check_u u;
+ ( 3. *. b.a3 -. 9. *. b.a2 +. 9. *. b.a1 -. 3. *. b.a0 ) *. ( u ** 2. )
+ +. ( 6. *. b.a2 -. 12. *. b.a1 +. 6. *. b.a0 ) *. u +. 3. *. b.a1 -. 3. *. b.a0
+
+let ddf ~u b =
+ check_u u;
+ ( 6. *. b.a3 -. 18. *. b.a2 +. 18. *. b.a1 -. 6. *. b.a0 ) *. u
+ +. 6. *. b.a2 -. 12. *. b.a1 +. 6. *. b.a0
+
+let point ~u b =
+ compute ~u b.cx , compute ~u b.cy
+
+let dp ~u b =
+ df ~u b.cx, df ~u b.cy
+
+let ddp ~u b =
+ ddf ~u b.cx, ddf ~u b.cy
+
+let integrate n f ui uf =
+ let du = ( uf -. ui ) /. (float n) in
+ let acc = ref 0. in
+ for i = 0 to (n-1) do
+ acc := !acc +. (f ~du ~u:( ui +. ( (float i) *. du ) ) ) *. du ;
+ done;
+ !acc
+
+let wheel_rapport r ~u b =
+ let s' = norm (dp u b) in
+ let y' = df u b.cy in
+ let x' = df u b.cx in
+ let y'' = ddf u b.cy in
+ let x'' = ddf u b.cx in
+ let theta' = ( y'' *. x' -. x'' *. y' ) /. ( x' *. x' +. y' *. y' ) in
+ let rapport = ( r.r_width *. theta' *. 0.5 +. s' )
+ /. ( -. r.r_width *. theta' *. 0.5 +. s' ) in
+ rapport
+
+(* [v']: previous speed *)
+(*
+ (* probleme quand v' = 0 *)
+ let previous_speed = prod_scal v' (normalize (dp ~u b)) in
+ let dt' = du /. (fst previous_speed) in
+ let max_reachable_speed = v' +. r.r_max_a *. dt' in
+*)
+
+let max_wheel_speed ~u r b =
+ let rapport = wheel_rapport r ~u b in
+ let rapport' = abs_float rapport in
+ let rapport = ( min rapport' (1. /. rapport') )
+ *. (if rapport >= 0. then 1. else -.1.) in
+ ( 1. +. rapport ) *. 0.5 *. r.r_max_wheel_speed
+
+let trajectory n r b =
+ let du = 1. /. (float n) in
+ let rec aux i =
+ if i > n
+ then []
+ else
+ let u = du *. (float i) in
+ let v = max_wheel_speed ~u r b in
+ let p = point ~u b in
+ (p,v)::(aux (i+1))
+ in
+ aux 0
+
+let pi = 4. *. atan 1.
+
+let bezier_x ~a0 ~a3 ~theta1 ~theta2 ~d1 ~d2 =
+ { a0 = a0;
+ a1 = a0 +. d1 *. ( cos theta1 );
+ a2 = a3 +. d2 *. ( cos ( pi +. theta2 ));
+ a3 = a3 }
+
+let bezier_y ~b0 ~b3 ~theta1 ~theta2 ~d1 ~d2 =
+ { a0 = b0;
+ a1 = b0 +. d1 *. ( sin theta1 );
+ a2 = b3 +. d2 *. ( sin ( pi +. theta2 ));
+ a3 = b3 }
+
+let bezier_traj n r (a0,b0) (a3,b3) ~theta1 ~theta2 ~d1 ~d2 =
+ let b =
+ { cx = bezier_x ~a0 ~a3 ~theta1 ~theta2 ~d1 ~d2;
+ cy = bezier_y ~b0 ~b3 ~theta1 ~theta2 ~d1 ~d2 } in
+ trajectory n r b
+
+(*** TEST ***)
+
+let robot =
+ { r_width = 0.3;
+ r_max_wheel_speed = 1.;
+ r_max_a = 0.1; }
+
+let a0,b0,a3,b3 = 0.,0.,2.,0.
+let d1,d2 = 0.5,0.5
+let theta1,theta2 = 0.,0.
+let theta1,theta2 = pi/.4.,(-.(pi/.4.))
+
+let b =
+ { cx = bezier_x ~a0 ~a3 ~theta1 ~theta2 ~d1 ~d2;
+ cy = bezier_y ~b0 ~b3 ~theta1 ~theta2 ~d1 ~d2 }
+
+let _ = wheel_rapport robot ~u:1. b
+
+let test =
+ bezier_traj 10 robot (0.,0.) (2.,0.) ~theta1:(pi/.4.) ~theta2:(-.pi/.4.) ~d1:0.5 ~d2:0.5
+(*(
+let limit_acceleration v_init du r l =
+ let l =
+ match l with
+ | [] -> failure "empty list"
+ | (p,_)::q -> q
+ in
+ let limit (p_prev,v_prev,l) (p,v_p) =
+ (* TODO -> limitation en fonction de l'acceleration *)
+
+ let v_max = min (dt *. r.r_max_a +. v_prev) (v_p) in
+ (p,v_max, (p,v_max)::l )
+ in
+ List.fold_left ...
+*)
+
+(*
+let test =
+ bezier_traj 10 robot (0.,0.) (1.,0.) ~v_init:0. ~theta1:(pi/.4.) ~theta2:(-.pi/.4.) ~d1:1. ~d2:1.
+
+let dist ~du ~u b =
+ let p1 = point u b in
+ let p2 = point (u+.du) b in
+ norm (p2 -| p1)
+
+let time n b r =
+ integrate n (fun ~du ~u ->
+ min_time ~du ~u r b ) ) 0. 1.
+
+let bezier_time n r (a0,b0) (a3,b3) ~theta1 ~theta2 ~d1 ~d2 =
+ let b =
+ { cx = bezier_x ~a0 ~a3 ~theta1 ~theta2 ~d1 ~d2;
+ cy = bezier_y ~b0 ~b3 ~theta1 ~theta2 ~d1 ~d2 } in
+ time n b r
+
+
+
+
+*)
hooks/post-receive
--
krobot-resources
|
|
From: Nicolas D. <Sup...@us...> - 2011-03-12 18:05:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 0d945464874b53fdc04d37e7e07ae8cf8c66f5bf (commit)
from 6f6f774a6e98e390a3fe2187b80fa73df3207bf2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0d945464874b53fdc04d37e7e07ae8cf8c66f5bf
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Sat Mar 12 19:02:39 2011 +0100
[arm] Update toolchain building script
The toolchain is now relocatable.
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/build-arm-toolchain b/arm/STM32/build-arm-toolchain
index 8caf42e..cf041b3 100755
--- a/arm/STM32/build-arm-toolchain
+++ b/arm/STM32/build-arm-toolchain
@@ -15,19 +15,18 @@ exit 1
TARGET=arm-none-eabi # Or: TARGET=arm-elf
PARALLEL="-j3" # Or: PARALLEL=""
-BINUTILS=binutils-2.20.1
-GCC=gcc-4.5.1
-NEWLIB=newlib-1.18.0
+BINUTILS=binutils-2.21
+GCC=gcc-4.5.2
+NEWLIB=newlib-1.19.0
GDB=gdb-7.2
export PATH="$PATH:$PREFIX/bin"
-
mkdir build
wget -c http://ftp.gnu.org/gnu/binutils/$BINUTILS.tar.bz2
tar xfvj $BINUTILS.tar.bz2
cd build
-../$BINUTILS/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls
+../$BINUTILS/configure --target=$TARGET --prefix=$PREFIX --with-sysroot=$PREFIX --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls
make $PARALLEL
make install
cd ..
@@ -36,7 +35,7 @@ mkdir build
wget -c ftp://ftp.gnu.org/gnu/gcc/$GCC/$GCC.tar.bz2
tar xfvj $GCC.tar.bz2
cd build
-../$GCC/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --enable-languages="c" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --disable-libssp --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb
+../$GCC/configure --target=$TARGET --prefix=$PREFIX --with-sysroot=$PREFIX --enable-interwork --enable-multilib --enable-languages="c" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --disable-libssp --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb
make $PARALLEL all-gcc
make install-gcc
cd ..
@@ -56,7 +55,7 @@ mkdir build
# Yes, you need to build gcc again!
cd build
-../$GCC/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --enable-languages="c,c++" --with-newlib --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb --disable-libssp
+../$GCC/configure --target=$TARGET --prefix=$PREFIX --with-sysroot=$PREFIX --enable-interwork --enable-multilib --enable-languages="c,c++" --with-newlib --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb --disable-libssp
make $PARALLEL
make install
cd ..
hooks/post-receive
--
krobot-resources
|
|
From: Nicolas D. <Sup...@us...> - 2011-03-02 20:23:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 6f6f774a6e98e390a3fe2187b80fa73df3207bf2 (commit)
from aa2014bd10e386cc1c6520edec0555c0de7bdb3a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6f6f774a6e98e390a3fe2187b80fa73df3207bf2
Author: Nicolas Dandrimont <Nic...@cr...>
Date: Wed Mar 2 21:22:39 2011 +0100
Add toolchain-building script.
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/build-arm-toolchain b/arm/STM32/build-arm-toolchain
new file mode 100755
index 0000000..8caf42e
--- /dev/null
+++ b/arm/STM32/build-arm-toolchain
@@ -0,0 +1,74 @@
+#!/bin/bash -e
+# Written by Uwe Hermann <uw...@he...>, released as public domain.
+# Heavily edited by Nicolas Dandrimont <ol...@cr...>, for use in [Kro]bot. Still released as Public Domain/CC0 where applicable.
+
+HOST=i686-linux-gnu # Or: HOST=x86_64-linux-gnu
+PREFIX=/home/nicolasd/opt/arm-i386 # Install location of your final toolchain
+
+echo "HOST is \`$HOST', PREFIX is \`$PREFIX'."
+echo
+echo "/!\\ USE A DEFINITIVE PREFIX, GCC IS NOT RELOCATABLE! /!\\"
+echo
+echo "Make sure this is okay and remove the exit 1 line in the script."
+exit 1
+
+TARGET=arm-none-eabi # Or: TARGET=arm-elf
+PARALLEL="-j3" # Or: PARALLEL=""
+
+BINUTILS=binutils-2.20.1
+GCC=gcc-4.5.1
+NEWLIB=newlib-1.18.0
+GDB=gdb-7.2
+
+export PATH="$PATH:$PREFIX/bin"
+
+mkdir build
+
+wget -c http://ftp.gnu.org/gnu/binutils/$BINUTILS.tar.bz2
+tar xfvj $BINUTILS.tar.bz2
+cd build
+../$BINUTILS/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls
+make $PARALLEL
+make install
+cd ..
+rm -rf build/
+mkdir build
+wget -c ftp://ftp.gnu.org/gnu/gcc/$GCC/$GCC.tar.bz2
+tar xfvj $GCC.tar.bz2
+cd build
+../$GCC/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --enable-languages="c" --with-newlib --without-headers --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --disable-libssp --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb
+make $PARALLEL all-gcc
+make install-gcc
+cd ..
+rm -rf build/
+mkdir build
+
+wget -c ftp://sources.redhat.com/pub/newlib/$NEWLIB.tar.gz
+tar xfvz $NEWLIB.tar.gz
+cd build
+../$NEWLIB/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --with-gnu-as --with-gnu-ld --disable-nls --disable-newlib-supplied-syscalls
+make $PARALLEL
+make install
+cd ..
+rm -rf build/
+mkdir build
+
+# Yes, you need to build gcc again!
+
+cd build
+../$GCC/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib --enable-languages="c,c++" --with-newlib --disable-shared --with-gnu-as --with-gnu-ld --with-system-zlib --with-float=soft --with-cpu=cortex-m3 --with-tune=cortex-m3 --with-mode=thumb --disable-libssp
+make $PARALLEL
+make install
+cd ..
+rm -rf build/
+mkdir build
+
+wget -c ftp://ftp.gnu.org/gnu/gdb/$GDB.tar.bz2
+tar xfvj $GDB.tar.bz2
+cd build
+../$GDB/configure --target=$TARGET --prefix=$PREFIX --enable-interwork --enable-multilib
+make $PARALLEL
+make install
+cd ..
+rm -rf build
+
hooks/post-receive
--
krobot-resources
|
|
From: Olivier B. <Sup...@us...> - 2011-01-05 19:43:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via aa2014bd10e386cc1c6520edec0555c0de7bdb3a (commit)
from d7ed81ff9569e9b871b3b56452b0aaf665431652 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit aa2014bd10e386cc1c6520edec0555c0de7bdb3a
Author: unknown <Olivier@.(none)>
Date: Wed Jan 5 20:41:34 2011 +0100
Ajout des sources du Guide du Krobot
-----------------------------------------------------------------------
Changes:
diff --git a/guide/.gitignore b/guide/.gitignore
new file mode 100644
index 0000000..8717fd0
--- /dev/null
+++ b/guide/.gitignore
@@ -0,0 +1,11 @@
+*.log
+*.aux
+*.out
+*.toc
+*.lof
+*.ist
+*.gls
+*.glo
+*.glg
+*.blg
+*.bbl
diff --git a/guide/Cours.pdf b/guide/Cours.pdf
new file mode 100644
index 0000000..b90eb09
--- /dev/null
+++ b/guide/Cours.pdf
@@ -0,0 +1,25411 @@
+%PDF-1.4
+%
+4 0 obj
+<< /S /GoTo /D (part.1) >>
+endobj
+7 0 obj
+(I Composants et th\351orie)
+endobj
+8 0 obj
+<< /S /GoTo /D (section.1) >>
+endobj
+11 0 obj
+(1 Les r\351sistances)
+endobj
+12 0 obj
+<< /S /GoTo /D (subsection.1.1) >>
+endobj
+15 0 obj
+(1.1 Code des couleurs)
+endobj
+16 0 obj
+<< /S /GoTo /D (subsection.1.2) >>
+endobj
+19 0 obj
+(1.2 S\351ries normalis\351es)
+endobj
+20 0 obj
+<< /S /GoTo /D (subsection.1.3) >>
+endobj
+23 0 obj
+(1.3 La r\351sistance de tirage)
+endobj
+24 0 obj
+<< /S /GoTo /D (subsection.1.4) >>
+endobj
+27 0 obj
+(1.4 La r\351sistance de limitation de courant)
+endobj
+28 0 obj
+<< /S /GoTo /D (subsubsection.1.4.1) >>
+endobj
+31 0 obj
+(1.4.1 Structure interne des sorties des circuits logiques)
+endobj
+32 0 obj
+<< /S /GoTo /D (subsubsection.1.4.2) >>
+endobj
+35 0 obj
+(1.4.2 Montage d'une LED sur la sortie d'un circuit logique)
+endobj
+36 0 obj
+<< /S /GoTo /D (subsection.1.5) >>
+endobj
+39 0 obj
+(1.5 Les r\351sistances de puissance)
+endobj
+40 0 obj
+<< /S /GoTo /D (subsection.1.6) >>
+endobj
+43 0 obj
+(1.6 Les r\351seaux de r\351sistances)
+endobj
+44 0 obj
+<< /S /GoTo /D (section.2) >>
+endobj
+47 0 obj
+(2 Les condensateurs)
+endobj
+48 0 obj
+<< /S /GoTo /D (subsection.2.1) >>
+endobj
+51 0 obj
+(2.1 Principales caract\351ristiques)
+endobj
+52 0 obj
+<< /S /GoTo /D (subsection.2.2) >>
+endobj
+55 0 obj
+(2.2 Les types de condensateurs)
+endobj
+56 0 obj
+<< /S /GoTo /D (subsubsection.2.2.1) >>
+endobj
+59 0 obj
+(2.2.1 C\351ramiques)
+endobj
+60 0 obj
+<< /S /GoTo /D (subsubsection.2.2.2) >>
+endobj
+63 0 obj
+(2.2.2 A film plastique \(MK\))
+endobj
+64 0 obj
+<< /S /GoTo /D (subsubsection.2.2.3) >>
+endobj
+67 0 obj
+(2.2.3 \311lectrolytiques)
+endobj
+68 0 obj
+<< /S /GoTo /D (subsubsection.2.2.4) >>
+endobj
+71 0 obj
+(2.2.4 Au mica)
+endobj
+72 0 obj
+<< /S /GoTo /D (subsubsection.2.2.5) >>
+endobj
+75 0 obj
+(2.2.5 Au papier)
+endobj
+76 0 obj
+<< /S /GoTo /D (subsection.2.3) >>
+endobj
+79 0 obj
+(2.3 Marquage des condensateurs)
+endobj
+80 0 obj
+<< /S /GoTo /D (subsubsection.2.3.1) >>
+endobj
+83 0 obj
+(2.3.1 Indication de la capacit\351)
+endobj
+84 0 obj
+<< /S /GoTo /D (subsubsection.2.3.2) >>
+endobj
+87 0 obj
+(2.3.2 Indication de la tol\351rance)
+endobj
+88 0 obj
+<< /S /GoTo /D (subsubsection.2.3.3) >>
+endobj
+91 0 obj
+(2.3.3 Indication de la tension nominale)
+endobj
+92 0 obj
+<< /S /GoTo /D (subsubsection.2.3.4) >>
+endobj
+95 0 obj
+(2.3.4 Indication de la d\351rive de la capacit\351)
+endobj
+96 0 obj
+<< /S /GoTo /D (subsubsection.2.3.5) >>
+endobj
+99 0 obj
+(2.3.5 Codification couleur des condensateurs c\351ramique et plastique)
+endobj
+100 0 obj
+<< /S /GoTo /D (subsubsection.2.3.6) >>
+endobj
+103 0 obj
+(2.3.6 Codification des condensateurs au mica)
+endobj
+104 0 obj
+<< /S /GoTo /D (subsection.2.4) >>
+endobj
+107 0 obj
+(2.4 Les condensateurs de d\351couplage)
+endobj
+108 0 obj
+<< /S /GoTo /D (subsection.2.5) >>
+endobj
+111 0 obj
+(2.5 Les condensateurs de lissage)
+endobj
+112 0 obj
+<< /S /GoTo /D (section.3) >>
+endobj
+115 0 obj
+(3 Les diodes)
+endobj
+116 0 obj
+<< /S /GoTo /D (subsection.3.1) >>
+endobj
+119 0 obj
+(3.1 Rep\351rage anode - cathode)
+endobj
+120 0 obj
+<< /S /GoTo /D (subsection.3.2) >>
+endobj
+123 0 obj
+(3.2 Marquage des diodes)
+endobj
+124 0 obj
+<< /S /GoTo /D (subsubsection.3.2.1) >>
+endobj
+127 0 obj
+(3.2.1 Le code JEDEC)
+endobj
+128 0 obj
+<< /S /GoTo /D (section.4) >>
+endobj
+131 0 obj
+(4 Les circuits int\351gr\351s)
+endobj
+132 0 obj
+<< /S /GoTo /D (subsection.4.1) >>
+endobj
+135 0 obj
+(4.1 Les familles de circuits logiques)
+endobj
+136 0 obj
+<< /S /GoTo /D (subsubsection.4.1.1) >>
+endobj
+139 0 obj
+(4.1.1 Technologie TTL)
+endobj
+140 0 obj
+<< /S /GoTo /D (subsubsection.4.1.2) >>
+endobj
+143 0 obj
+(4.1.2 Technologie CMOS)
+endobj
+144 0 obj
+<< /S /GoTo /D (subsection.4.2) >>
+endobj
+147 0 obj
+(4.2 Compatibilit\351 TTL - CMOS)
+endobj
+148 0 obj
+<< /S /GoTo /D (subsubsection.4.2.1) >>
+endobj
+151 0 obj
+(4.2.1 TTL vers CMOS)
+endobj
+152 0 obj
+<< /S /GoTo /D (subsubsection.4.2.2) >>
+endobj
+155 0 obj
+(4.2.2 CMOS vers TTL)
+endobj
+156 0 obj
+<< /S /GoTo /D (subsection.4.3) >>
+endobj
+159 0 obj
+(4.3 Les entr\351es inutilis\351es)
+endobj
+160 0 obj
+<< /S /GoTo /D (subsection.4.4) >>
+endobj
+163 0 obj
+(4.4 L'\351lectricit\351 statique)
+endobj
+164 0 obj
+<< /S /GoTo /D (section.5) >>
+endobj
+167 0 obj
+(5 Les PICs)
+endobj
+168 0 obj
+<< /S /GoTo /D (subsection.5.1) >>
+endobj
+171 0 obj
+(5.1 Installation de l'environnement de d\351veloppement)
+endobj
+172 0 obj
+<< /S /GoTo /D (subsubsection.5.1.1) >>
+endobj
+175 0 obj
+(5.1.1 Int\351grer MPLAB C18 \340 MPLAB IDE)
+endobj
+176 0 obj
+<< /S /GoTo /D (subsubsection.5.1.2) >>
+endobj
+179 0 obj
+(5.1.2 Cr\351er un projet avec MPLAB IDE)
+endobj
+180 0 obj
+<< /S /GoTo /D (subsubsection.5.1.3) >>
+endobj
+183 0 obj
+(5.1.3 Transfert du programme sur le PIC)
+endobj
+184 0 obj
+<< /S /GoTo /D (subsection.5.2) >>
+endobj
+187 0 obj
+(5.2 Caract\351ristiques du PIC18F452)
+endobj
+188 0 obj
+<< /S /GoTo /D (subsubsection.5.2.1) >>
+endobj
+191 0 obj
+(5.2.1 Le composant)
+endobj
+192 0 obj
+<< /S /GoTo /D (subsubsection.5.2.2) >>
+endobj
+195 0 obj
+(5.2.2 L'horloge \(CLOCK\))
+endobj
+196 0 obj
+<< /S /GoTo /D (subsubsection.5.2.3) >>
+endobj
+199 0 obj
+(5.2.3 L'initialisation \(RESET\))
+endobj
+200 0 obj
+<< /S /GoTo /D (subsubsection.5.2.4) >>
+endobj
+203 0 obj
+(5.2.4 La m\351moire)
+endobj
+204 0 obj
+<< /S /GoTo /D (subsubsection.5.2.5) >>
+endobj
+207 0 obj
+(5.2.5 Les entr\351es/sorties)
+endobj
+208 0 obj
+<< /S /GoTo /D (subsubsection.5.2.6) >>
+endobj
+211 0 obj
+(5.2.6 Les timers)
+endobj
+212 0 obj
+<< /S /GoTo /D (subsection.5.3) >>
+endobj
+215 0 obj
+(5.3 Un montage de base)
+endobj
+216 0 obj
+<< /S /GoTo /D (subsection.5.4) >>
+endobj
+219 0 obj
+(5.4 La programmation)
+endobj
+220 0 obj
+<< /S /GoTo /D (subsubsection.5.4.1) >>
+endobj
+223 0 obj
+(5.4.1 Faire clignoter une LED)
+endobj
+224 0 obj
+<< /S /GoTo /D (subsubsection.5.4.2) >>
+endobj
+227 0 obj
+(5.4.2 Les interruptions)
+endobj
+228 0 obj
+<< /S /GoTo /D (subsubsection.5.4.3) >>
+endobj
+231 0 obj
+(5.4.3 Faire clignoter une LED sur interruption)
+endobj
+232 0 obj
+<< /S /GoTo /D (part.2) >>
+endobj
+235 0 obj
+(II Conception et r\351alisation de cartes)
+endobj
+236 0 obj
+<< /S /GoTo /D (section.6) >>
+endobj
+239 0 obj
+(6 Utilisation d'OrCAD Capture)
+endobj
+240 0 obj
+<< /S /GoTo /D (subsection.6.1) >>
+endobj
+243 0 obj
+(6.1 Cr\351er un nouveau projet)
+endobj
+244 0 obj
+<< /S /GoTo /D (subsection.6.2) >>
+endobj
+247 0 obj
+(6.2 Prise en main)
+endobj
+248 0 obj
+<< /S /GoTo /D (subsubsection.6.2.1) >>
+endobj
+251 0 obj
+(6.2.1 Les nets)
+endobj
+252 0 obj
+<< /S /GoTo /D (subsubsection.6.2.2) >>
+endobj
+255 0 obj
+(6.2.2 Les alimentations)
+endobj
+256 0 obj
+<< /S /GoTo /D (subsubsection.6.2.3) >>
+endobj
+259 0 obj
+(6.2.3 Les bus)
+endobj
+260 0 obj
+<< /S /GoTo /D (subsubsection.6.2.4) >>
+endobj
+263 0 obj
+(6.2.4 Les principales librairies)
+endobj
+264 0 obj
+<< /S /GoTo /D (subsubsection.6.2.5) >>
+endobj
+267 0 obj
+(6.2.5 Les raccourcis clavier indispensables)
+endobj
+268 0 obj
+<< /S /GoTo /D (subsection.6.3) >>
+endobj
+271 0 obj
+(6.3 Premier sch\351ma \(ultra simple\))
+endobj
+272 0 obj
+<< /S /GoTo /D (section.7) >>
+endobj
+275 0 obj
+(7 Passer d'OrCAD Capture \340 OrCAD Layout)
+endobj
+276 0 obj
+<< /S /GoTo /D (subsection.7.1) >>
+endobj
+279 0 obj
+(7.1 Associer un footprint \340 un composant)
+endobj
+280 0 obj
+<< /S /GoTo /D (subsection.7.2) >>
+endobj
+283 0 obj
+(7.2 G\351n\351rer la netlist pour Layout)
+endobj
+284 0 obj
+<< /S /GoTo /D (subsection.7.3) >>
+endobj
+287 0 obj
+(7.3 Cr\351er un nouveau PCB sous Layout)
+endobj
+288 0 obj
+<< /S /GoTo /D (section.8) >>
+endobj
+291 0 obj
+(8 Conception d'un PCB)
+endobj
+292 0 obj
+<< /S /GoTo /D (subsection.8.1) >>
+endobj
+295 0 obj
+(8.1 Les classes de fabrication)
+endobj
+296 0 obj
+<< /S /GoTo /D (subsection.8.2) >>
+endobj
+299 0 obj
+(8.2 Les couches \(layers\))
+endobj
+300 0 obj
+<< /S /GoTo /D (subsubsection.8.2.1) >>
+endobj
+303 0 obj
+(8.2.1 Plan de masse)
+endobj
+304 0 obj
+<< /S /GoTo /D (subsection.8.3) >>
+endobj
+307 0 obj
+(8.3 Les pistes \(nets\))
+endobj
+308 0 obj
+<< /S /GoTo /D (subsubsection.8.3.1) >>
+endobj
+311 0 obj
+(8.3.1 Largeur des pistes)
+endobj
+312 0 obj
+<< /S /GoTo /D (subsubsection.8.3.2) >>
+endobj
+315 0 obj
+(8.3.2 Espacement entre pistes et/ou pastilles)
+endobj
+316 0 obj
+<< /S /GoTo /D (subsubsection.8.3.3) >>
+endobj
+319 0 obj
+(8.3.3 Configuration de l'espacement dans Layout)
+endobj
+320 0 obj
+<< /S /GoTo /D (subsection.8.4) >>
+endobj
+323 0 obj
+(8.4 Les pastilles \(padstacks\))
+endobj
+324 0 obj
+<< /S /GoTo /D (subsubsection.8.4.1) >>
+endobj
+327 0 obj
+(8.4.1 Modifier les pastilles dans Layout)
+endobj
+328 0 obj
+<< /S /GoTo /D (subsection.8.5) >>
+endobj
+331 0 obj
+(8.5 Routage entre deux broches)
+endobj
+332 0 obj
+<< /S /GoTo /D (subsection.8.6) >>
+endobj
+335 0 obj
+(8.6 Placement des condensateurs de d\351couplage)
+endobj
+336 0 obj
+<< /S /GoTo /D (section.9) >>
+endobj
+339 0 obj
+(9 Le\347ons enseign\351es par la pratique)
+endobj
+340 0 obj
+<< /S /GoTo /D (subsection.9.1) >>
+endobj
+343 0 obj
+(9.1 L'importance des capacit\351s de d\351couplage)
+endobj
+344 0 obj
+<< /S /GoTo /D (subsection.9.2) >>
+endobj
+347 0 obj
+(9.2 La maitrise des bus de communication \(s\351rie / I2C / ...\))
+endobj
+348 0 obj
+<< /S /GoTo /D (part.3) >>
+endobj
+351 0 obj
+(III Sch\351mas classiques)
+endobj
+352 0 obj
+<< /S /GoTo /D (section.10) >>
+endobj
+355 0 obj
+(10 R\351gulateur de tension \(5 V\))
+endobj
+356 0 obj
+<< /S /GoTo /D (subsection.10.1) >>
+endobj
+359 0 obj
+(10.1 Puissance dissip\351e)
+endobj
+360 0 obj
+<< /S /GoTo /D (subsection.10.2) >>
+endobj
+363 0 obj
+(10.2 Dimensionner un radiateur)
+endobj
+364 0 obj
+<< /S /GoTo /D (section.11) >>
+endobj
+367 0 obj
+(11 Commande d'un relais)
+endobj
+368 0 obj
+<< /S /GoTo /D (subsection.11.1) >>
+endobj
+371 0 obj
+(11.1 Caract\351ristiques du relais)
+endobj
+372 0 obj
+<< /S /GoTo /D (subsection.11.2) >>
+endobj
+375 0 obj
+(11.2 Transistor NPN en commutation)
+endobj
+376 0 obj
+<< /S /GoTo /D (subsection.11.3) >>
+endobj
+379 0 obj
+(11.3 Transistor PNP en commutation)
+endobj
+380 0 obj
+<< /S /GoTo /D (subsection.11.4) >>
+endobj
+383 0 obj
+(11.4 Montage Darlington)
+endobj
+384 0 obj
+<< /S /GoTo /D (section.12) >>
+endobj
+387 0 obj
+(12 Commutation de puissance)
+endobj
+388 0 obj
+<< /S /GoTo /D (section.13) >>
+endobj
+391 0 obj
+(13 Conversion s\351rie - RS232)
+endobj
+392 0 obj
+<< /S /GoTo /D (section.14) >>
+endobj
+395 0 obj
+(14 Conversion USB - s\351rie)
+endobj
+396 0 obj
+<< /S /GoTo /D (section.15) >>
+endobj
+399 0 obj
+(15 Interface moteur pas \340 pas bipolaire)
+endobj
+400 0 obj
+<< /S /GoTo /D (part.4) >>
+endobj
+403 0 obj
+(IV R\351alisations)
+endobj
+404 0 obj
+<< /S /GoTo /D (section.16) >>
+endobj
+407 0 obj
+(16 Conception d'un bus)
+endobj
+408 0 obj
+<< /S /GoTo /D (subsection.16.1) >>
+endobj
+411 0 obj
+(16.1 Lecture des donn\351es)
+endobj
+412 0 obj
+<< /S /GoTo /D (subsection.16.2) >>
+endobj
+415 0 obj
+(16.2 \311criture des donn\351es)
+endobj
+416 0 obj
+<< /S /GoTo /D (subsubsection.16.2.1) >>
+endobj
+419 0 obj
+(16.2.1 L'initialisation)
+endobj
+420 0 obj
+<< /S /GoTo /D (subsubsection.16.2.2) >>
+endobj
+423 0 obj
+(16.2.2 L'\351criture)
+endobj
+424 0 obj
+<< /S /GoTo /D (subsection.16.3) >>
+endobj
+427 0 obj
+(16.3 Les interruptions)
+endobj
+428 0 obj
+<< /S /GoTo /D (subsubsection.16.3.1) >>
+endobj
+431 0 obj
+(16.3.1 Activation des interruptions)
+endobj
+432 0 obj
+<< /S /GoTo /D (subsubsection.16.3.2) >>
+endobj
+435 0 obj
+(16.3.2 Gestion des interruptions)
+endobj
+436 0 obj
+<< /S /GoTo /D (section.17) >>
+endobj
+439 0 obj
+(17 Syst\350me de positionnement)
+endobj
+440 0 obj
+<< /S /GoTo /D (subsection.17.1) >>
+endobj
+443 0 obj
+(17.1 Principe de triangularisation)
+endobj
+444 0 obj
+<< /S /GoTo /D (part.5) >>
+endobj
+447 0 obj
+(V M\351canique)
+endobj
+448 0 obj
+<< /S /GoTo /D (section.18) >>
+endobj
+451 0 obj
+(18 La motorisation)
+endobj
+452 0 obj
+<< /S /GoTo /D (subsection.18.1) >>
+endobj
+455 0 obj
+(18.1 Dimensionner ses moteurs)
+endobj
+456 0 obj
+<< /S /GoTo /D (subsubsection.18.1.1) >>
+endobj
+459 0 obj
+(18.1.1 Vitesse de rotation et rapport de r\351duction du moteur)
+endobj
+460 0 obj
+<< /S /GoTo /D (subsubsection.18.1.2) >>
+endobj
+463 0 obj
+(18.1.2 Couple minimum du moteur)
+endobj
+464 0 obj
+<< /S /GoTo /D (subsubsection.18.1.3) >>
+endobj
+467 0 obj
+(18.1.3 Puissance du moteur)
+endobj
+468 0 obj
+<< /S /GoTo /D (part.6) >>
+endobj
+471 0 obj
+(VI Ressources)
+endobj
+472 0 obj
+<< /S /GoTo /D (section.19) >>
+endobj
+475 0 obj
+(19 Adresses utiles)
+endobj
+476 0 obj
+<< /S /GoTo /D (subsection.19.1) >>
+endobj
+479 0 obj
+(19.1 \311lectronique)
+endobj
+480 0 obj
+<< /S /GoTo /D (subsection.19.2) >>
+endobj
+483 0 obj
+(19.2 Robotique)
+endobj
+484 0 obj
+<< /S /GoTo /D (subsection.19.3) >>
+endobj
+487 0 obj
+(19.3 Coupe de robotique)
+endobj
+488 0 obj
+<< /S /GoTo /D (subsection.19.4) >>
+endobj
+491 0 obj
+(19.4 Fournisseurs)
+endobj
+492 0 obj
+<< /S /GoTo /D (section*.40) >>
+endobj
+495 0 obj
+(Glossaire)
+endobj
+496 0 obj
+<< /S /GoTo /D (section*.41) >>
+endobj
+499 0 obj
+(R\351f\351rences)
+endobj
+500 0 obj
+<< /S /GoTo /D [501 0 R /FitH ] >>
+endobj
+506 0 obj <<
+/Length 762
+/Filter /FlateDecode
+>>
+stream
+xTKS'Z([q`ƱJ+
a&5Z1e51)Ȝ^iulP [t vśd\4
+ f C`6MedA<ۺz\.dFϫr
+ kP2%YÅo4F4S*>^p>uf-$KPɅ^Nq,Ҥ^&4rYI |
|
From: Xavier L. <Sup...@us...> - 2010-04-18 11:35:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 962da5704f1772178f4f6ca559e790792dc42743 (commit)
from 841ba80bae5a9095792033d754b40b32a9f1a47c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 962da5704f1772178f4f6ca559e790792dc42743
Author: Xavier Lagorce <Xav...@cr...>
Date: Sun Apr 18 13:34:45 2010 +0200
reorganisation of the template folder
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/template/jtag/flash.cfg b/arm/STM32/template/jtag/flash.cfg
deleted file mode 100644
index 75d09b1..0000000
--- a/arm/STM32/template/jtag/flash.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-init
-reset halt
-stm32x mass_erase 0
-flash write_bank 0 main.bin 0
-reset init
-reset run
-shutdown
\ No newline at end of file
diff --git a/arm/STM32/template/jtag/openocd.cfg b/arm/STM32/template/jtag/openocd.cfg
deleted file mode 100644
index 0f3a9a2..0000000
--- a/arm/STM32/template/jtag/openocd.cfg
+++ /dev/null
@@ -1,84 +0,0 @@
-#
-# Olimex ARM-USB-OCD
-#
-# http://www.olimex.com/dev/arm-usb-ocd.html
-#
-
-interface ft2232
-ft2232_device_desc "Olimex OpenOCD JTAG"
-ft2232_layout olimex-jtag
-ft2232_vid_pid 0x15ba 0x0003
-
-# script for stm32
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# Use the correct size for the card
-set WORKAREASIZE 0x5000
-
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-jtag_khz 1000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.3
- set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- # FIXME this never gets used to override defaults...
- set _BSTAPID $BSTAPID
-} else {
- # See STM Document RM0008
- # Section 29.6.2
- # Low density devices, Rev A
- set _BSTAPID1 0x06412041
- # Medium density devices, Rev A
- set _BSTAPID2 0x06410041
- # Medium density devices, Rev B and Rev Z
- set _BSTAPID3 0x16410041
- # High density devices, Rev A
- set _BSTAPID4 0x06414041
- # Connectivity line devices, Rev A and Rev Z
- set _BSTAPID5 0x06418041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
- -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
- -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
-
diff --git a/arm/STM32/template/jtag/target.ini b/arm/STM32/template/jtag/target.ini
deleted file mode 100644
index da18158..0000000
--- a/arm/STM32/template/jtag/target.ini
+++ /dev/null
@@ -1,93 +0,0 @@
-#
-# GDB init file for STM32x family
-#
-
-set complaints 1
-set output-radix 16
-set input-radix 16
-
-# GDB must be set to big endian mode first if needed.
-#set endian little
-
-# add str9lib src to gdb search path
-#dir /cygdrive/c/progra~1/anglia/idealist/examples/stm32/libstr32x/src
-#dir C:/Progra~1/Anglia/IDEaliST/examples/stm32/libstm32x/src
-
-# change gdb prompt
-set prompt (arm-gdb)
-
-# You will need to change this to reflect the address of your jtag interface.
-#target remote localhost:2000
-
-# The libremote daemon must be set to big endian before the
-# executable is loaded.
-#monitor endian little
-
-# Increase the packet size to improve download speed.
-# to view current setting use:
-# show remote memory-write-packet-size
-
-set remote memory-write-packet-size 1024
-set remote memory-write-packet-size fixed
-
-set remote memory-read-packet-size 1024
-set remote memory-read-packet-size fixed
-set remote hardware-watchpoint-limit 6
-set remote hardware-breakpoint-limit 6
-
-# Load the program executable (ram only)
-#load
-
-# Set a breakpoint at main().
-#b main
-
-# Run to the breakpoint.
-#c
-
-#
-# GDB command helpers
-#
-
-#
-# reset and map 0 to internal ram
-#
-
-define ramreset
-reset
-set *(int*)0xE000ED08 = 0x20000000
-echo Internal RAM set to address 0x0.
-end
-
-#
-# reset and map 0 to flash
-#
-
-define flashreset
-reset
-thb main
-echo Internal Flash set to address 0x0.
-end
-
-#
-# reset target
-#
-
-define reset
-monitor reset
-end
-
-document ramreset
-ramreset
-Causes a target reset, remaps Internal RAM to address 0x0.
-end
-
-document flashreset
-flashreset
-Causes a target reset, remaps Internal Flash to address 0x0.
-A temporary breakpoint is set at start of function main
-end
-
-document reset
-reset
-Causes a target reset.
-end
diff --git a/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld b/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld
deleted file mode 100644
index 5e4ce87..0000000
--- a/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-Linker script for STM32F10x
-Copyright RAISONANCE 2007 (modified by Lanchon 1-Feb-2008)
-You can use, copy and distribute this file freely, but without any waranty.
-Configure memory sizes, end of stack and boot mode for your project here.
-*/
-
-
-/* include the common STM32F10x sub-script */
-INCLUDE "STM32_COMMON.ld"
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* also change _estack below */
- FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
- FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
- EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
-}
-
-/* highest address of the user mode stack */
-_estack = 0x20005000;
-
-/* include the section management sub-script */
-/* (either "STM32_SEC_FLASH.ld" or "STM32_SEC_RAM.ld") */
-INCLUDE "STM32_SEC_FLASH.ld"
diff --git a/arm/STM32/template/lib/STM32_COMMON.ld b/arm/STM32/template/lib/STM32_COMMON.ld
deleted file mode 100644
index 6794c70..0000000
--- a/arm/STM32/template/lib/STM32_COMMON.ld
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
-Common part of the linker scripts for STR32 devices
-Copyright RAISONANCE 2007
-You can use, modify and distribute thisfile freely, but without any waranty.
-*/
-
-
-/* default stack sizes.
-
-These are used by the startup in order to allocate stacks for the different modes.
-*/
-
-__Stack_Size = 1024 ;
-
-PROVIDE ( _Stack_Size = __Stack_Size ) ;
-
-__Stack_Init = _estack - __Stack_Size ;
-
-/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
-PROVIDE ( _Stack_Init = __Stack_Init ) ;
-
-/*
-There will be a link error if there is not this amount of RAM free at the end.
-*/
-_Minimum_Stack_Size = 0x100 ;
-
-
-
-/*
-this sends all unreferenced IRQHandlers to reset
-*/
-
-
-PROVIDE ( Undefined_Handler = 0 ) ;
-PROVIDE ( SWI_Handler = 0 ) ;
-PROVIDE ( IRQ_Handler = 0 ) ;
-PROVIDE ( Prefetch_Handler = 0 ) ;
-PROVIDE ( Abort_Handler = 0 ) ;
-PROVIDE ( FIQ_Handler = 0 ) ;
-
-PROVIDE ( NMIException = 0 ) ;
-PROVIDE ( HardFaultException = 0 ) ;
-PROVIDE ( MemManageException = 0 ) ;
-PROVIDE ( BusFaultException = 0 ) ;
-PROVIDE ( UsageFaultException = 0 ) ;
-PROVIDE ( SVCHandler = 0 ) ;
-PROVIDE ( DebugMonitor = 0 ) ;
-PROVIDE ( PendSVC = 0 ) ;
-PROVIDE ( SysTickHandler = 0 ) ;
-PROVIDE ( WWDG_IRQHandler = 0 ) ;
-PROVIDE ( PVD_IRQHandler = 0 ) ;
-PROVIDE ( TAMPER_IRQHandler = 0 ) ;
-PROVIDE ( RTC_IRQHandler = 0 ) ;
-PROVIDE ( FLASH_IRQHandler = 0 ) ;
-PROVIDE ( RCC_IRQHandler = 0 ) ;
-PROVIDE ( EXTI0_IRQHandler = 0 ) ;
-PROVIDE ( EXTI1_IRQHandler = 0 ) ;
-PROVIDE ( EXTI2_IRQHandler = 0 ) ;
-PROVIDE ( EXTI3_IRQHandler = 0 ) ;
-PROVIDE ( EXTI4_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
-PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
-PROVIDE ( ADC_IRQHandler = 0 ) ;
-PROVIDE ( USB_HP_CAN_TX_IRQHandler = 0 ) ;
-PROVIDE ( USB_LP_CAN_RX0_IRQHandler = 0 ) ;
-PROVIDE ( CAN_RX1_IRQHandler = 0 ) ;
-PROVIDE ( CAN_SCE_IRQHandler = 0 ) ;
-PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
-PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
-PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
-PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
-PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
-PROVIDE ( TIM2_IRQHandler = 0 ) ;
-PROVIDE ( TIM3_IRQHandler = 0 ) ;
-PROVIDE ( TIM4_IRQHandler = 0 ) ;
-PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
-PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
-PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
-PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
-PROVIDE ( SPI1_IRQHandler = 0 ) ;
-PROVIDE ( SPI2_IRQHandler = 0 ) ;
-PROVIDE ( USART1_IRQHandler = 0 ) ;
-PROVIDE ( USART2_IRQHandler = 0 ) ;
-PROVIDE ( USART3_IRQHandler = 0 ) ;
-PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
-PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
-PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
-
-
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/*this allows to compile the ST lib in "non-debug" mode*/
-
-
-/* Peripheral and SRAM base address in the alias region */
-PERIPH_BB_BASE = 0x42000000;
-SRAM_BB_BASE = 0x22000000;
-
-/* Peripheral and SRAM base address in the bit-band region */
-SRAM_BASE = 0x20000000;
-PERIPH_BASE = 0x40000000;
-
-/* Flash registers base address */
-PROVIDE ( FLASH_BASE = 0x40022000);
-/* Flash Option Bytes base address */
-PROVIDE ( OB_BASE = 0x1FFFF800);
-
-/* Peripheral memory map */
-APB1PERIPH_BASE = PERIPH_BASE ;
-APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
-AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
-
-PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
-PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
-PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
-PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
-PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
-PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
-PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
-PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
-PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
-PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
-PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
-PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
-PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
-PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
-
-PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
-PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
-PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
-PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
-PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
-PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
-PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
-PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
-PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
-PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
-PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
-PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
-
-PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
-PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
-PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
-PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
-PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
-PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
-PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
-PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
-PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
-
-/* System Control Space memory map */
-SCS_BASE = 0xE000E000;
-
-PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
-PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
-PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
-
diff --git a/arm/STM32/template/lib/STM32_SEC_EXT.ld b/arm/STM32/template/lib/STM32_SEC_EXT.ld
deleted file mode 100644
index 3623d06..0000000
--- a/arm/STM32/template/lib/STM32_SEC_EXT.ld
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
-Common part of the linker scripts for STR71x devices in EXT mode
-(that is, the EXT is seen at 0)
-Copyright RAISONANCE 2005
-You can use, modify and distribute thisfile freely, but without any waranty.
-*/
-
-
-
-/* Sections Definitions */
-
-SECTIONS
-{
- /* the program code is stored in the .text section */
- .text :
- {
- . = ALIGN(4);
-
- *crt0*.o (.text) /* Startup code */
- *startup.o (.text) /* Startup code */
- *(.text) /* remaining code */
- *(.rodata) /* read-only data (constants) */
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
-
- . = ALIGN(4);
- _etext = .;
- /* This is used by the startup in order to initialize the .data secion */
- _sidata = _etext ;
- } >EXTMEMB0
-
-
-
- /* This is the initialized data section
- The program executes knowing that the data is in the RAM
- but the loader puts the initial values in the EXTMEM.
- It is one task of the startup to copy the initial values from EXTMEMB0 to RAM. */
- .data : AT ( _etext )
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _sdata = . ;
-
- *(.data)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _edata = . ;
- } >RAM
-
-
-
- /* This is the uninitialized data section */
- .bss :
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .;
-
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
-
- } >RAM
-
- PROVIDE ( end = _ebss );
- PROVIDE ( _end = _ebss );
-
- /* This is the user stack section
- This is just to check that there is enough RAM left for the User mode stack
- It should generate an error if it's full.
- */
- ._usrstack :
- {
- . = ALIGN(4);
- _susrstack = . ;
-
- . = . + _Minimum_Stack_Size ;
-
- _eusrstack = ALIGN(4) ;
- . = .;
- } >RAM
-
-
- /* this is the FLASH Bank0 */
- /* the C or assembly source must explicitly place the code or data there
- using the "section" attribute */
- .fb0text :
- {
- *(.fb0text) /* remaining code */
- *(.fb0rodata) /* read-only data (constants) */
- *(.fb0rodata*)
- } >FLASH
-
- /* this is the FLASH Bank1 */
- /* the C or assembly source must explicitly place the code or data there
- using the "section" attribute */
- .fb1text :
- {
- *(.fb1text) /* remaining code */
- *(.fb1rodata) /* read-only data (constants) */
- *(.fb1rodata*)
- } >FLASHB1
-
- /* EXTMEM Bank1 */
- .eb1text :
- {
- *(.b1text) /* remaining code */
- *(.b1rodata) /* read-only data (constants) */
- *(.b1rodata*)
- } >EXTMEMB1
-
- /* EXTMEM Bank2 */
- .eb2text :
- {
- *(.b2text) /* remaining code */
- *(.b2rodata) /* read-only data (constants) */
- *(.b2rodata*)
- } >EXTMEMB2
-
- /* EXTMEM Bank0 */
- .eb3text :
- {
- *(.b3text) /* remaining code */
- *(.b3rodata) /* read-only data (constants) */
- *(.b3rodata*)
- } >EXTMEMB3
-
- __exidx_start = .;
- __exidx_end = .;
-
- /* after that it's only debugging information. */
-
- /* remove the debugging information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
-
-
-
diff --git a/arm/STM32/template/lib/STM32_SEC_FLASH.ld b/arm/STM32/template/lib/STM32_SEC_FLASH.ld
deleted file mode 100644
index cd8c4fa..0000000
--- a/arm/STM32/template/lib/STM32_SEC_FLASH.ld
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
-Common part of the linker scripts for STR71x devices in FLASH mode
-(that is, the FLASH is seen at 0)
-Copyright RAISONANCE 2005
-You can use, modify and distribute thisfile freely, but without any waranty.
-*/
-
-
-
-/* Sections Definitions */
-
-SECTIONS
-{
- /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
- .flashtext :
- {
- . = ALIGN(4);
- *(.flashtext) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
-
- /* the program code is stored in the .text section, which goes to Flash */
- .text :
- {
- . = ALIGN(4);
-
- *(.text) /* remaining code */
- *(.text.*) /* remaining code */
- *(.rodata) /* read-only data (constants) */
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
-
- . = ALIGN(4);
- _etext = .;
- /* This is used by the startup in order to initialize the .data secion */
- _sidata = _etext;
- } >FLASH
-
-
-
- /* This is the initialized data section
- The program executes knowing that the data is in the RAM
- but the loader puts the initial values in the FLASH (inidata).
- It is one task of the startup to copy the initial values from FLASH to RAM. */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _sdata = . ;
-
- *(.data)
- *(.data.*)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _edata = . ;
- } >RAM
-
-
-
- /* This is the uninitialized data section */
- .bss :
- {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .;
-
- *(.bss)
- *(COMMON)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
- } >RAM
-
- PROVIDE ( end = _ebss );
- PROVIDE ( _end = _ebss );
-
- /* This is the user stack section
- This is just to check that there is enough RAM left for the User mode stack
- It should generate an error if it's full.
- */
- ._usrstack :
- {
- . = ALIGN(4);
- _susrstack = . ;
-
- . = . + _Minimum_Stack_Size ;
-
- . = ALIGN(4);
- _eusrstack = . ;
- } >RAM
-
-
-
- /* this is the FLASH Bank1 */
- /* the C or assembly source must explicitly place the code or data there
- using the "section" attribute */
- .b1text :
- {
- *(.b1text) /* remaining code */
- *(.b1rodata) /* read-only data (constants) */
- *(.b1rodata*)
- } >FLASHB1
-
- /* this is the EXTMEM */
- /* the C or assembly source must explicitly place the code or data there
- using the "section" attribute */
-
- /* EXTMEM Bank0 */
- .eb0text :
- {
- *(.eb0text) /* remaining code */
- *(.eb0rodata) /* read-only data (constants) */
- *(.eb0rodata*)
- } >EXTMEMB0
-
- /* EXTMEM Bank1 */
- .eb1text :
- {
- *(.eb1text) /* remaining code */
- *(.eb1rodata) /* read-only data (constants) */
- *(.eb1rodata*)
- } >EXTMEMB1
-
- /* EXTMEM Bank2 */
- .eb2text :
- {
- *(.eb2text) /* remaining code */
- *(.eb2rodata) /* read-only data (constants) */
- *(.eb2rodata*)
- } >EXTMEMB2
-
- /* EXTMEM Bank0 */
- .eb3text :
- {
- *(.eb3text) /* remaining code */
- *(.eb3rodata) /* read-only data (constants) */
- *(.eb3rodata*)
- } >EXTMEMB3
-
- __exidx_start = .;
- __exidx_end = .;
-
- /* after that it's only debugging information. */
-
- /* remove the debugging information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
-
-
-
diff --git a/arm/STM32/template/lib/STM32_SEC_RAM.ld b/arm/STM32/template/lib/STM32_SEC_RAM.ld
deleted file mode 100644
index 4b44bb2..0000000
--- a/arm/STM32/template/lib/STM32_SEC_RAM.ld
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
-Common part of the linker scripts for STR71x devices in RAM mode
-(that is, the RAM is seen at 0 and we assume that the loader initializes it)
-Copyright RAISONANCE 2005
-You can use, modify and distribute thisfile freely, but without any waranty.
-*/
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
- /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to start of RAM */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >RAM
-
- /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
- .flashtext :
- {
- . = ALIGN(4);
- *(.flashtext) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* the program code is stored in the .text section, which goes to RAM */
- .text :
- {
- . = ALIGN(4);
-
- *(.text ) /* remaining code */
- *(.glue_7)
- *(.glue_7t)
-
- . = ALIGN(4);
- } >RAM
-
- /* This is the uninitialized data section. */
- .bss :
- {
- . = ALIGN(4);
- _sbss = .;
-
- *(.bss)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = . ;
- _etext = _ebss ;
-
- } >RAM
-
-
- /* read-only data (constants) */
- .rodata :
- {
- *(.rodata)
- *(.rodata*)
- . = ALIGN(4);
- } > FLASH
-
-
- .idata :
- {
- _sidata = . ;
- } > FLASH
-
-
- /* This is the initialized data section. */
- .data : AT ( _sidata )
- {
- . = ALIGN(4);
- _sdata = .;
- *(.data)
- . = ALIGN(4);
- _edata = . ;
- } >RAM
-
-
-
- PROVIDE ( end = _edata );
- PROVIDE ( _end = _edata );
-
- /* This is the user stack section
- This is just to check that there is enough RAM left for the User mode stack
- It should generate an error if it's full.
- */
- ._usrstack :
- {
- . = ALIGN(4);
- _susrstack = . ;
-
- . = . + _Minimum_Stack_Size ;
-
- . = ALIGN(4);
- _eusrstack = . ;
- } >RAM
-
-
- __exidx_start = .;
- __exidx_end = .;
-
- /* after that it's only debugging information. */
-
- /* remove the debugging information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
-/* .debug_info 0 : { * ( EXCLUDE_FILE ( *libc.a *libm.a ) .debug_info .gnu.linkonce.wi.*) }*/
- .debug_info 0 : { * ( .debug_info .gnu.linkonce.wi.*) }
-/* .debug_abbrev 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_abbrev) }*/
- .debug_abbrev 0 : { *(.debug_abbrev) }
-/* .debug_line 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_line) }*/
- .debug_line 0 : { *( .debug_line) }
- /* (*(EXCLUDE_FILE (*crtend.o *otherfile.o) .ctors)) */
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
-
-
-
diff --git a/arm/STM32/template/lib/STM32_SEC_RAMonly.ld b/arm/STM32/template/lib/STM32_SEC_RAMonly.ld
deleted file mode 100644
index fa90799..0000000
--- a/arm/STM32/template/lib/STM32_SEC_RAMonly.ld
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
-Common part of the linker scripts for STR71x devices in RAM mode
-(that is, the RAM is seen at 0 and we assume that the loader initializes it)
-Copyright RAISONANCE 2005
-You can use, modify and distribute thisfile freely, but without any waranty.
-*/
-
-/* Sections Definitions */
-
-SECTIONS
-{
-
- /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to start of RAM */
- .isr_vector :
- {
- . = ALIGN(4);
- *(.isr_vector) /* Startup code */
- . = ALIGN(4);
- } >RAM
-
-
- /* the beginning of the startup code is stored in the .flashtext section */
- .flashtext :
- {
- . = ALIGN(4);
-
- *crt0*.o (.flashtext) /* Startup code */
- *startup.o (.flashtext) /* Startup code */
- *(.flashtext) /* Startup code */
- . = ALIGN(4);
- } >RAM
-
- /* the program code is stored in the .text section */
- .text :
- {
- . = ALIGN(4);
-
- *crt0*.o (.text) /* Startup code */
- *startup.o (.text) /* Startup code */
- *(.text ) /* remaining code */
- *(.glue_7)
- *(.glue_7t)
-
- . = ALIGN(4);
- } >RAM
-
- /* This is the uninitialized data section. */
- .bss :
- {
- . = ALIGN(4);
- _sbss = .;
-
- *(.bss)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = . ;
- _etext = _ebss ;
-
- } >RAM
-
-
- /* read-only data (constants) */
- .rodata :
- {
- *(.rodata)
- *(.rodata*)
- . = ALIGN(4);
- } > RAM
-
-
- /* This is the initialized data section. */
- .data :
- {
- . = ALIGN(4);
- _sidata = . ; /*this is useless but allows the same startup as for the other modes to be used.*/
- _sdata = .;
- *(.data)
- . = ALIGN(4);
- _edata = . ;
- } >RAM
-
-
-
- PROVIDE ( end = _edata );
- PROVIDE ( _end = _edata );
-
- /* This is the user stack section
- This is just to check that there is enough RAM left for the User mode stack
- It should generate an error if it's full.
- */
- ._usrstack :
- {
- . = ALIGN(4);
- _susrstack = . ;
-
- . = . + _Minimum_Stack_Size ;
-
- . = ALIGN(4);
- _eusrstack = . ;
- } >RAM
-
-
- __exidx_start = .;
- __exidx_end = .;
-
- /* after that it's only debugging information. */
-
- /* remove the debugging information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
-/* .debug_info 0 : { * ( EXCLUDE_FILE ( *libc.a *libm.a ) .debug_info .gnu.linkonce.wi.*) }*/
- .debug_info 0 : { * ( .debug_info .gnu.linkonce.wi.*) }
-/* .debug_abbrev 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_abbrev) }*/
- .debug_abbrev 0 : { *(.debug_abbrev) }
-/* .debug_line 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_line) }*/
- .debug_line 0 : { *( .debug_line) }
- /* (*(EXCLUDE_FILE (*crtend.o *otherfile.o) .ctors)) */
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
-
-
-
diff --git a/arm/STM32/template/lib/inc/cortexm3_macro.h b/arm/STM32/template/lib/inc/cortexm3_macro.h
deleted file mode 100644
index 822d019..0000000
--- a/arm/STM32/template/lib/inc/cortexm3_macro.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
-* File Name : cortexm3_macro.h
-* Author : MCD Application Team
-* Version : V1.0
-* Date : 10/08/2007
-* Description : Header file for cortexm3_macro.s.
-********************************************************************************
-* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __CORTEXM3_MACRO_H
-#define __CORTEXM3_MACRO_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_type.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void __WFI(void);
-void __WFE(void);
-void __SEV(void);
-void __ISB(void);
-void __DSB(void);
-void __DMB(void);
-void __SVC(void);
-u32 __MRS_CONTROL(void);
-void __MSR_CONTROL(u32 Control);
-u32 __MRS_PSP(void);
-void __MSR_PSP(u32 TopOfProcessStack);
-u32 __MRS_MSP(void);
-void __MSR_MSP(u32 TopOfMainStack);
-void __SETPRIMASK(void);
-void __RESETPRIMASK(void);
-void __SETFAULTMASK(void);
-void __RESETFAULTMASK(void);
-void __BASEPRICONFIG(u32 NewPriority);
-u32 __GetBASEPRI(void);
-u16 __REV_HalfWord(u16 Data);
-u32 __REV_Word(u32 Data);
-
-#endif /* __CORTEXM3_MACRO_H */
-
-/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_adc.h b/arm/STM32/template/lib/inc/stm32f10x_adc.h
deleted file mode 100644
index 452d04e..0000000
--- a/arm/STM32/template/lib/inc/stm32f10x_adc.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
-* File Name : stm32f10x_adc.h
-* Author : MCD Application Team
-* Version : V1.0
-* Date : 10/08/2007
-* Description : This file contains all the functions prototypes for the
-* ADC firmware library.
-********************************************************************************
-* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_ADC_H
-#define __STM32F10x_ADC_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* ADC Init structure definition */
-typedef struct
-{
- u32 ADC_Mode;
- FunctionalState ADC_ScanConvMode;
- FunctionalState ADC_ContinuousConvMode;
- u32 ADC_ExternalTrigConv;
- u32 ADC_DataAlign;
- u8 ADC_NbrOfChannel;
-}ADC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/* ADC dual mode -------------------------------------------------------------*/
-#define ADC_Mode_Independent ((u32)0x00000000)
-#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
-#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
-#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
-#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
-#define ADC_Mode_InjecSimult ((u32)0x00050000)
-#define ADC_Mode_RegSimult ((u32)0x00060000)
-#define ADC_Mode_FastInterl ((u32)0x00070000)
-#define ADC_Mode_SlowInterl ((u32)0x00080000)
-#define ADC_Mode_AlterTrig ((u32)0x00090000)
-
-#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
- (MODE == ADC_Mode_RegInjecSimult) || \
- (MODE == ADC_Mode_RegSimult_AlterTrig) || \
- (MODE == ADC_Mode_InjecSimult_FastInterl) || \
- (MODE == ADC_Mode_InjecSimult_SlowInterl) || \
- (MODE == ADC_Mode_InjecSimult) || \
- (MODE == ADC_Mode_RegSimult) || \
- (MODE == ADC_Mode_FastInterl) || \
- (MODE == ADC_Mode_SlowInterl) || \
- (MODE == ADC_Mode_AlterTrig))
-
-/* ADC extrenal trigger sources for regular channels conversion --------------*/
-#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
-#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
-#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
-#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
-#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
-#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)
-#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
-
-#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
- (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
- (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
- (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
- (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
- (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
- (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
- (TRIG1 == ADC_ExternalTrigConv_None))
-
-/* ADC data align ------------------------------------------------------------*/
-#define ADC_DataAlign_Right ((u32)0x00000000)
-#define ADC_DataAlign_Left ((u32)0x00000800)
-
-#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
- (ALIGN == ADC_DataAlign_Left))
-
-/* ADC channels --------------------------------------------------------------*/
-#define ADC_Channel_0 ((u8)0x00)
-#define ADC_Channel_1 ((u8)0x01)
-#define ADC_Channel_2 ((u8)0x02)
-#define ADC_Channel_3 ((u8)0x03)
-#define ADC_Channel_4 ((u8)0x04)
-#define ADC_Channel_5 ((u8)0x05)
-#define ADC_Channel_6 ((u8)0x06)
-#define ADC_Channel_7 ((u8)0x07)
-#define ADC_Channel_8 ((u8)0x08)
-#define ADC_Channel_9 ((u8)0x09)
-#define ADC_Channel_10 ((u8)0x0A)
-#define ADC_Channel_11 ((u8)0x0B)
-#define ADC_Channel_12 ((u8)0x0C)
-#define ADC_Channel_13 ((u8)0x0D)
-#define ADC_Channel_14 ((u8)0x0E)
-#define ADC_Channel_15 ((u8)0x0F)
-#define ADC_Channel_16 ((u8)0x10)
-#define ADC_Channel_17 ((u8)0x11)
-
-#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
- (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
- (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
- (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
- (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
- (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
- (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
- (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
- (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
-
-/* ADC sampling times --------------------------------------------------------*/
-#define ADC_SampleTime_1Cycles5 ((u8)0x00)
-#define ADC_SampleTime_7Cycles5 ((u8)0x01)
-#define ADC_SampleTime_13Cycles5 ((u8)0x02)
-#define ADC_SampleTime_28Cycles5 ((u8)0x03)
-#define ADC_SampleTime_41Cycles5 ((u8)0x04)
-#define ADC_SampleTime_55Cycles5 ((u8)0x05)
-#define ADC_SampleTime_71Cycles5 ((u8)0x06)
-#define ADC_SampleTime_239Cycles5 ((u8)0x07)
-
-#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
- (TIME == ADC_SampleTime_7Cycles5) || \
- (TIME == ADC_SampleTime_13Cycles5) || \
- (TIME == ADC_SampleTime_28Cycles5) || \
- (TIME == ADC_SampleTime_41Cycles5) || \
- (TIME == ADC_SampleTime_55Cycles5) || \
- (TIME == ADC_SampleTime_71Cycles5) || \
- (TIME == ADC_SampleTime_239Cycles5))
-
-/* ADC extrenal trigger sources for injected channels conversion -------------*/
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
-#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)
-#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
-
-#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
- (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
- (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
- (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
- (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
- (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
- (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
- (TRIG == ADC_ExternalTrigInjecConv_None))
-
-/* ADC injected channel selection --------------------------------------------*/
-#define ADC_InjectedChannel_1 ((u8)0x14)
-#define ADC_InjectedChannel_2 ((u8)0x18)
-#define ADC_InjectedChannel_3 ((u8)0x1C)
-#define ADC_InjectedChannel_4 ((u8)0x20)
-
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
- (CHANNEL == ADC_InjectedChannel_2) || \
- (CHANNEL == ADC_InjectedChannel_3) || \
- (CHANNEL == ADC_InjectedChannel_4))
-
-/* ADC analog watchdog selection ---------------------------------------------*/
-#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
-#define ADC_AnalogWatchdog_None ((u32)0x00000000)
-
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
- (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
- (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
- (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
- (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
- (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
- (WATCHDOG == ADC_AnalogWatchdog_None))
-
-/* ADC interrupts definition -------------------------------------------------*/
-#define ADC_IT_EOC ((u16)0x0220)
-#define ADC_IT_AWD ((u16)0x0140)
-#define ADC_IT_JEOC ((u16)0x0480)
-
-#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
-#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
- (IT == ADC_IT_JEOC))
-
-/* ADC flags definition ------------------------------------------------------*/
-#define ADC_FLAG_AWD ((u8)0x01)
-#define ADC_FLAG_EOC ((u8)0x02)
-#define ADC_FLAG_JEOC ((u8)0x04)
-#define ADC_FLAG_JSTRT ((u8)0x08)
-#define ADC_FLAG_STRT ((u8)0x10)
-
-#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
-#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
- (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
- (FLAG == ADC_FLAG_STRT))
-
-/* ADC thresholds ------------------------------------------------------------*/
-#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
-
-/* ADC injected offset -------------------------------------------------------*/
-#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
-
-/* ADC injected length -------------------------------------------------------*/
-#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
-
-/* ADC injected rank ---------------------------------------------------------*/
-#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
-
-/* ADC regular length --------------------------------------------------------*/
-#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
-
-/* ADC regular rank ----------------------------------------------------------*/
-#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
-
-/* ADC regular discontinuous mode number -------------------------------------*/
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void ADC_DeInit(ADC_TypeDef* ADCx);
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
-void ADC_ResetCalibration(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
-void ADC_StartCalibration(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
-u32 ADC_GetDualModeConversionValue(void);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
-u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
-
-#endif /*__STM32F10x_ADC_H */
-
-/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_bkp.h b/arm/STM32/template/lib/inc/stm32f10x_bkp.h
deleted file mode 100644
index 79e702f..0000000
--- a/arm/STM32/template/lib/inc/stm32f10x_bkp.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
-* File Name : stm32f10x_bkp.h
-* Author : MCD Application Team
-* Version : V1.0
-* Date : 10/08/2007
-* Description : This file contains all the functions prototypes for the
-* BKP firmware library.
-********************************************************************************
-* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_BKP_H
-#define __STM32F10x_BKP_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Tamper Pin active level */
-#define BKP_TamperPinLevel_High ((u16)0x0000)
-#define BKP_TamperPinLevel_Low ((u16)0x0001)
-
-#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \
- (LEVEL == BKP_TamperPinLevel_Low))
-
-/* RTC output source to output on the Tamper pin */
-#define BKP_RTCOutputSource_None ((u16)0x0000)
-#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
-#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
-#define BKP_RTCOutputSource_Second ((u16)0x0300)
-
-#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) ((SOURCE == BKP_RTCOutputSource_None) || \
- (SOURCE == BKP_RTCOutputSource_CalibClock) || \
- (SOURCE == BKP_RTCOutputSource_Alarm) || \
- (SOURCE == BKP_RTCOutputSource_Second))
-
-/* Data Backup Register */
-#define BKP_DR1 ((u16)0x0004)
-#define BKP_DR2 ((u16)0x0008)
-#define BKP_DR3 ((u16)0x000C)
-#define BKP_DR4 ((u16)0x0010)
-#define BKP_DR5 ((u16)0x0014)
-#define BKP_DR6 ((u16)0x0018)
-#define BKP_DR7 ((u16)0x001C)
-#define BKP_DR8 ((u16)0x0020)
-#define BKP_DR9 ((u16)0x0024)
-#define BKP_DR10 ((u16)0x0028)
-
-#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \
- (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \
- (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \
- (DR == BKP_DR10))
-
-#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void BKP_DeInit(void);
-void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
-void BKP_TamperPinCmd(FunctionalState NewState);
-void BKP_ITConfig(FunctionalState NewState);
-void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
-void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
-void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
-u16 BKP_ReadBackupRegister(u16 BKP_DR);
-FlagStatus BKP_GetFlagStatus(void);
-void BKP_ClearFlag(void);
-ITStatus BKP_GetITStatus(void);
-void BKP_ClearITPendingBit(void);
-
-#endif /* __STM32F10x_BKP_H */
-
-/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_can.h b/arm/STM32/template/lib/inc/stm32f10x_can.h
deleted file mode 100644
index a8c170d..0000000
--- a/arm/STM32/template/lib/inc/stm32f10x_can.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
-* File Name : stm32f10x_can.h
-* Author : MCD Application Team
-* Version : V1.0
-* Date : 10/08/2007
-* Description : This file contains all the functions prototypes for the
-* CAN firmware library.
-********************************************************************************
-* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-*******************************************************************************/
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CAN_H
-#define __STM32F10x_CAN_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_map.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* CAN init structure definition */
-typedef struct
-{
- FunctionalState CAN_TTCM;
- FunctionalState CAN_ABOM;
- FunctionalState CAN_AWUM;
- FunctionalState CAN_NART;
- FunctionalState CAN_RFLM;
- FunctionalState CAN_TXFP;
- u8 CAN_Mode;
- u8 CAN_SJW;
- u8 CAN_BS1;
- u8 CAN_BS2;
- u16 CAN_Prescaler;
-} CAN_InitTypeDef;
-
-/* CAN filter init structure definition */
-typedef struct
-{
- u8 CAN_FilterNumber;
- u8 CAN_FilterMode;
- u8 CAN_FilterScale...
[truncated message content] |
|
From: Xavier L. <Sup...@us...> - 2010-04-17 19:31:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 841ba80bae5a9095792033d754b40b32a9f1a47c (commit)
via a351343e422cf23cda623f220b99aeab4a6beb74 (commit)
from 1f9606b5d51a8dce38491bf562793497196dd2f5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 841ba80bae5a9095792033d754b40b32a9f1a47c
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Apr 17 21:31:14 2010 +0200
Minor corrections and modifications
commit a351343e422cf23cda623f220b99aeab4a6beb74
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Apr 17 21:28:43 2010 +0200
removed files generated by compiler
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/template/main.c b/arm/STM32/template/main.c
index 15ed902..cb3cd4b 100644
--- a/arm/STM32/template/main.c
+++ b/arm/STM32/template/main.c
@@ -48,11 +48,8 @@ int main(void)
/* NVIC Configuration */
NVIC_Configuration();
-
- /* Enable GPIOC clock */
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
- /* Configure PC.4 as Output push-pull */
+ /* Configure PC.12 as Output push-pull */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
@@ -60,12 +57,12 @@ int main(void)
while (1)
{
- /* Turn on led connected to PC.4 pin */
+ /* Turn on led connected to PC.12 pin */
GPIO_SetBits(GPIOC, GPIO_Pin_12);
/* Insert delay */
Delay(0xFFFFF);
- /* Turn off led connected to PC.4 pin */
+ /* Turn off led connected to PC.12 pin */
GPIO_ResetBits(GPIOC, GPIO_Pin_12);
/* Insert delay */
Delay(0xFFFFF);
@@ -126,6 +123,9 @@ void RCC_Configuration(void)
{
}
}
+
+ /* Enable GPIOC clock */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
}
/*******************************************************************************
diff --git a/arm/STM32/template/main.elf.map b/arm/STM32/template/main.elf.map
deleted file mode 100644
index 01d0650..0000000
--- a/arm/STM32/template/main.elf.map
+++ /dev/null
@@ -1,1630 +0,0 @@
-Archive member included because of file (symbol)
-
-lib/libstm32.a(stm32f10x_flash.o)
- main.o (FLASH_SetLatency)
-lib/libstm32.a(stm32f10x_gpio.o)
- main.o (GPIO_Init)
-lib/libstm32.a(stm32f10x_nvic.o)
- main.o (NVIC_SetVectorTable)
-lib/libstm32.a(stm32f10x_rcc.o)
- main.o (RCC_DeInit)
-lib/libstm32.a(cortexm3_macro.o)
- lib/libstm32.a(stm32f10x_nvic.o) (__SETPRIMASK)
-lib/libstm32.a(stm32f10x_vector.o)
- (Reset_Handler)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o (atexit)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o (exit)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o) (_global_impure_ptr)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o (__libc_init_array)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o (memset)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o (initialise_monitor_handles)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o) (__register_exitproc)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o) (__call_exitprocs)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o) (__errno)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o) (__sinit)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o) (_fwalk)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o) (_malloc_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o) (__malloc_lock)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o) (_sbrk_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o) (__sread)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o) (strlen)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o) (_write_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o) (_close_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o) (fclose)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o) (_fflush_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o) (_free_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o) (_lseek_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-readr.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o) (_read_r)
-/home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o) (errno)
-
-Allocating common symbols
-Common symbol size file
-
-HSEStartUpStatus 0x1 main.o
-errno 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
-GPIO_InitStructure 0x4 main.o
-
-Discarded input sections
-
- .text 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .init 0x00000000 0xc /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .fini 0x00000000 0xc /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .text 0x00000000 0x94 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .data 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .bss 0x00000000 0x1c /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .init_array 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .fini_array 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .eh_frame 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .jcr 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .text 0x00000000 0x10c /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .data 0x00000000 0x110 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .ARM.extab 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .ARM.exidx 0x00000000 0x8 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .data 0x00000000 0x0 main.o
- .bss 0x00000000 0x0 main.o
- .data 0x00000000 0x0 stm32f10x_it.o
- .bss 0x00000000 0x0 stm32f10x_it.o
- .data 0x00000000 0x0 lib/libstm32.a(stm32f10x_flash.o)
- .bss 0x00000000 0x0 lib/libstm32.a(stm32f10x_flash.o)
- .data 0x00000000 0x0 lib/libstm32.a(stm32f10x_gpio.o)
- .bss 0x00000000 0x0 lib/libstm32.a(stm32f10x_gpio.o)
- .data 0x00000000 0x0 lib/libstm32.a(stm32f10x_nvic.o)
- .bss 0x00000000 0x0 lib/libstm32.a(stm32f10x_nvic.o)
- .data 0x00000000 0x0 lib/libstm32.a(stm32f10x_rcc.o)
- .data 0x00000000 0x0 lib/libstm32.a(cortexm3_macro.o)
- .bss 0x00000000 0x0 lib/libstm32.a(cortexm3_macro.o)
- .data 0x00000000 0x0 lib/libstm32.a(stm32f10x_vector.o)
- .bss 0x00000000 0x0 lib/libstm32.a(stm32f10x_vector.o)
- .text 0x00000000 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- .text 0x00000000 0x34 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- .text 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .data 0x00000000 0x430 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .rodata 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .rodata.str1.4
- 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .text 0x00000000 0xc4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- .text 0x00000000 0xf8 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- .text 0x00000000 0x8e0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .bss 0x00000000 0xb0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .rodata.str1.4
- 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .text 0x00000000 0xf4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- .text 0x00000000 0x164 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- .text 0x00000000 0x10 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- .text 0x00000000 0x334 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- .text 0x00000000 0x10c /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- .text 0x00000000 0x710 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- .data 0x00000000 0x410 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- .bss 0x00000000 0x34 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- .text 0x00000000 0x8 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- .text 0x00000000 0x40 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- .text 0x00000000 0xe0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- .text 0x00000000 0x60 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- .text 0x00000000 0x44 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- .text 0x00000000 0x3c /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- .text 0x00000000 0x10c /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- .text 0x00000000 0x298 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- .text 0x00000000 0x360 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- .text 0x00000000 0x44 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- .text 0x00000000 0x44 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-readr.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-readr.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-readr.o)
- .text 0x00000000 0x1a4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- COMMON 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- .text 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
- .eh_frame 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
- .jcr 0x00000000 0x4 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
- .text 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
- .data 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
- .bss 0x00000000 0x0 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
- .init 0x00000000 0xc /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
- .fini 0x00000000 0xc /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
-
-Memory Configuration
-
-Name Origin Length Attributes
-RAM 0x20000000 0x00005000 xrw
-FLASH 0x08000000 0x00020000 xr
-FLASHB1 0x00000000 0x00000000 xr
-EXTMEMB0 0x00000000 0x00000000 xr
-EXTMEMB1 0x00000000 0x00000000 xr
-EXTMEMB2 0x00000000 0x00000000 xr
-EXTMEMB3 0x00000000 0x00000000 xr
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
-LOAD main.o
-LOAD stm32f10x_it.o
-LOAD lib/libstm32.a
-START GROUP
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/libgcc.a
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a
-END GROUP
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
-LOAD /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
- 0x00000400 __Stack_Size = 0x400
- 0x00000400 PROVIDE (_Stack_Size, __Stack_Size)
- 0x20004c00 __Stack_Init = (_estack - __Stack_Size)
- 0x20004c00 PROVIDE (_Stack_Init, __Stack_Init)
- 0x00000100 _Minimum_Stack_Size = 0x100
- 0x00000000 PROVIDE (Undefined_Handler, 0x0)
- 0x00000000 PROVIDE (SWI_Handler, 0x0)
- 0x00000000 PROVIDE (IRQ_Handler, 0x0)
- 0x00000000 PROVIDE (Prefetch_Handler, 0x0)
- 0x00000000 PROVIDE (Abort_Handler, 0x0)
- 0x00000000 PROVIDE (FIQ_Handler, 0x0)
- 0x00000000 PROVIDE (NMIException, 0x0)
- 0x00000000 PROVIDE (HardFaultException, 0x0)
- 0x00000000 PROVIDE (MemManageException, 0x0)
- 0x00000000 PROVIDE (BusFaultException, 0x0)
- 0x00000000 PROVIDE (UsageFaultException, 0x0)
- 0x00000000 PROVIDE (SVCHandler, 0x0)
- 0x00000000 PROVIDE (DebugMonitor, 0x0)
- 0x00000000 PROVIDE (PendSVC, 0x0)
- 0x00000000 PROVIDE (SysTickHandler, 0x0)
- 0x00000000 PROVIDE (WWDG_IRQHandler, 0x0)
- 0x00000000 PROVIDE (PVD_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TAMPER_IRQHandler, 0x0)
- 0x00000000 PROVIDE (RTC_IRQHandler, 0x0)
- 0x00000000 PROVIDE (FLASH_IRQHandler, 0x0)
- 0x00000000 PROVIDE (RCC_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI0_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI1_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI2_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI3_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI4_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel1_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel2_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel3_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel4_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel5_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel6_IRQHandler, 0x0)
- 0x00000000 PROVIDE (DMAChannel7_IRQHandler, 0x0)
- 0x00000000 PROVIDE (ADC_IRQHandler, 0x0)
- 0x00000000 PROVIDE (USB_HP_CAN_TX_IRQHandler, 0x0)
- 0x00000000 PROVIDE (USB_LP_CAN_RX0_IRQHandler, 0x0)
- 0x00000000 PROVIDE (CAN_RX1_IRQHandler, 0x0)
- 0x00000000 PROVIDE (CAN_SCE_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI9_5_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM1_BRK_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM1_UP_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM1_TRG_COM_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM1_CC_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM2_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM3_IRQHandler, 0x0)
- 0x00000000 PROVIDE (TIM4_IRQHandler, 0x0)
- 0x00000000 PROVIDE (I2C1_EV_IRQHandler, 0x0)
- 0x00000000 PROVIDE (I2C1_ER_IRQHandler, 0x0)
- 0x00000000 PROVIDE (I2C2_EV_IRQHandler, 0x0)
- 0x00000000 PROVIDE (I2C2_ER_IRQHandler, 0x0)
- 0x00000000 PROVIDE (SPI1_IRQHandler, 0x0)
- 0x00000000 PROVIDE (SPI2_IRQHandler, 0x0)
- 0x00000000 PROVIDE (USART1_IRQHandler, 0x0)
- 0x00000000 PROVIDE (USART2_IRQHandler, 0x0)
- 0x00000000 PROVIDE (USART3_IRQHandler, 0x0)
- 0x00000000 PROVIDE (EXTI15_10_IRQHandler, 0x0)
- 0x00000000 PROVIDE (RTCAlarm_IRQHandler, 0x0)
- 0x00000000 PROVIDE (USBWakeUp_IRQHandler, 0x0)
- 0x42000000 PERIPH_BB_BASE = 0x42000000
- 0x22000000 SRAM_BB_BASE = 0x22000000
- 0x20000000 SRAM_BASE = 0x20000000
- 0x40000000 PERIPH_BASE = 0x40000000
- 0x40022000 PROVIDE (FLASH_BASE, 0x40022000)
- 0x1ffff800 PROVIDE (OB_BASE, 0x1ffff800)
- 0x40000000 APB1PERIPH_BASE = PERIPH_BASE
- 0x40010000 APB2PERIPH_BASE = (PERIPH_BASE + 0x10000)
- 0x40020000 AHBPERIPH_BASE = (PERIPH_BASE + 0x20000)
- 0x40000000 PROVIDE (TIM2, (APB1PERIPH_BASE + 0x0))
- 0x40000400 PROVIDE (TIM3, (APB1PERIPH_BASE + 0x400))
- 0x40000800 PROVIDE (TIM4, (APB1PERIPH_BASE + 0x800))
- 0x40002800 PROVIDE (RTC, (APB1PERIPH_BASE + 0x2800))
- 0x40002c00 PROVIDE (WWDG, (APB1PERIPH_BASE + 0x2c00))
- 0x40003000 PROVIDE (IWDG, (APB1PERIPH_BASE + 0x3000))
- 0x40003800 PROVIDE (SPI2, (APB1PERIPH_BASE + 0x3800))
- 0x40004400 PROVIDE (USART2, (APB1PERIPH_BASE + 0x4400))
- 0x40004800 PROVIDE (USART3, (APB1PERIPH_BASE + 0x4800))
- 0x40005400 PROVIDE (I2C1, (APB1PERIPH_BASE + 0x5400))
- 0x40005800 PROVIDE (I2C2, (APB1PERIPH_BASE + 0x5800))
- 0x40006400 PROVIDE (CAN, (APB1PERIPH_BASE + 0x6400))
- 0x40006c00 PROVIDE (BKP, (APB1PERIPH_BASE + 0x6c00))
- 0x40007000 PROVIDE (PWR, (APB1PERIPH_BASE + 0x7000))
- 0x40010000 PROVIDE (AFIO, (APB2PERIPH_BASE + 0x0))
- 0x40010400 PROVIDE (EXTI, (APB2PERIPH_BASE + 0x400))
- 0x40010800 PROVIDE (GPIOA, (APB2PERIPH_BASE + 0x800))
- 0x40010c00 PROVIDE (GPIOB, (APB2PERIPH_BASE + 0xc00))
- 0x40011000 PROVIDE (GPIOC, (APB2PERIPH_BASE + 0x1000))
- 0x40011400 PROVIDE (GPIOD, (APB2PERIPH_BASE + 0x1400))
- 0x40011800 PROVIDE (GPIOE, (APB2PERIPH_BASE + 0x1800))
- 0x40012400 PROVIDE (ADC1, (APB2PERIPH_BASE + 0x2400))
- 0x40012800 PROVIDE (ADC2, (APB2PERIPH_BASE + 0x2800))
- 0x40012c00 PROVIDE (TIM1, (APB2PERIPH_BASE + 0x2c00))
- 0x40013000 PROVIDE (SPI1, (APB2PERIPH_BASE + 0x3000))
- 0x40013800 PROVIDE (USART1, (APB2PERIPH_BASE + 0x3800))
- 0x40020000 PROVIDE (DMA, (AHBPERIPH_BASE + 0x0))
- 0x40020008 PROVIDE (DMA_Channel1, (AHBPERIPH_BASE + 0x8))
- 0x4002001c PROVIDE (DMA_Channel2, (AHBPERIPH_BASE + 0x1c))
- 0x40020030 PROVIDE (DMA_Channel3, (AHBPERIPH_BASE + 0x30))
- 0x40020044 PROVIDE (DMA_Channel4, (AHBPERIPH_BASE + 0x44))
- 0x40020058 PROVIDE (DMA_Channel5, (AHBPERIPH_BASE + 0x58))
- 0x4002006c PROVIDE (DMA_Channel6, (AHBPERIPH_BASE + 0x6c))
- 0x40020080 PROVIDE (DMA_Channel7, (AHBPERIPH_BASE + 0x80))
- 0x40021000 PROVIDE (RCC, (AHBPERIPH_BASE + 0x1000))
- 0xe000e000 SCS_BASE = 0xe000e000
- 0xe000e010 PROVIDE (SysTick, (SCS_BASE + 0x10))
- 0xe000e100 PROVIDE (NVIC, (SCS_BASE + 0x100))
- 0xe000ed00 PROVIDE (SCB, (SCS_BASE + 0xd00))
- 0x20005000 _estack = 0x20005000
-
-.isr_vector 0x08000000 0x10c
- 0x08000000 . = ALIGN (0x4)
- *(.isr_vector)
- .isr_vector 0x08000000 0x10c lib/libstm32.a(stm32f10x_vector.o)
- 0x08000000 g_pfnVectors
- 0x0800010c . = ALIGN (0x4)
-
-.flashtext 0x0800010c 0x0
- 0x0800010c . = ALIGN (0x4)
- *(.flashtext)
- 0x0800010c . = ALIGN (0x4)
-
-.text 0x0800010c 0x1fe8
- 0x0800010c . = ALIGN (0x4)
- *(.text)
- .text 0x0800010c 0x15c main.o
- 0x0800010c main
- 0x0800019c RCC_Configuration
- 0x08000230 NVIC_Configuration
- 0x08000244 Delay
- .text 0x08000268 0x260 stm32f10x_it.o
- 0x08000268 NMIException
- 0x08000274 HardFaultException
- 0x0800027c MemManageException
- 0x08000284 BusFaultException
- 0x0800028c UsageFaultException
- 0x08000294 DebugMonitor
- 0x080002a0 SVCHandler
- 0x080002ac PendSVC
- 0x080002b8 SysTickHandler
- 0x080002c4 WWDG_IRQHandler
- 0x080002d0 PVD_IRQHandler
- 0x080002dc TAMPER_IRQHandler
- 0x080002e8 RTC_IRQHandler
- 0x080002f4 FLASH_IRQHandler
- 0x08000300 RCC_IRQHandler
- 0x0800030c EXTI0_IRQHandler
- 0x08000318 EXTI1_IRQHandler
- 0x08000324 EXTI2_IRQHandler
- 0x08000330 EXTI3_IRQHandler
- 0x0800033c EXTI4_IRQHandler
- 0x08000348 DMAChannel1_IRQHandler
- 0x08000354 DMAChannel2_IRQHandler
- 0x08000360 DMAChannel3_IRQHandler
- 0x0800036c DMAChannel4_IRQHandler
- 0x08000378 DMAChannel5_IRQHandler
- 0x08000384 DMAChannel6_IRQHandler
- 0x08000390 DMAChannel7_IRQHandler
- 0x0800039c ADC_IRQHandler
- 0x080003a8 USB_HP_CAN_TX_IRQHandler
- 0x080003b4 USB_LP_CAN_RX0_IRQHandler
- 0x080003c0 CAN_RX1_IRQHandler
- 0x080003cc CAN_SCE_IRQHandler
- 0x080003d8 EXTI9_5_IRQHandler
- 0x080003e4 TIM1_BRK_IRQHandler
- 0x080003f0 TIM1_UP_IRQHandler
- 0x080003fc TIM1_TRG_COM_IRQHandler
- 0x08000408 TIM1_CC_IRQHandler
- 0x08000414 TIM2_IRQHandler
- 0x08000420 TIM3_IRQHandler
- 0x0800042c TIM4_IRQHandler
- 0x08000438 I2C1_EV_IRQHandler
- 0x08000444 I2C1_ER_IRQHandler
- 0x08000450 I2C2_EV_IRQHandler
- 0x0800045c I2C2_ER_IRQHandler
- 0x08000468 SPI1_IRQHandler
- 0x08000474 SPI2_IRQHandler
- 0x08000480 USART1_IRQHandler
- 0x0800048c USART2_IRQHandler
- 0x08000498 USART3_IRQHandler
- 0x080004a4 EXTI15_10_IRQHandler
- 0x080004b0 RTCAlarm_IRQHandler
- 0x080004bc USBWakeUp_IRQHandler
- .text 0x080004c8 0xcc lib/libstm32.a(stm32f10x_flash.o)
- 0x080004c8 FLASH_SetLatency
- 0x0800050c FLASH_HalfCycleAccessCmd
- 0x08000550 FLASH_PrefetchBufferCmd
- .text 0x08000594 0x670 lib/libstm32.a(stm32f10x_gpio.o)
- 0x08000594 GPIO_DeInit
- 0x08000678 GPIO_AFIODeInit
- 0x08000698 GPIO_Init
- 0x0800085c GPIO_StructInit
- 0x08000888 GPIO_ReadInputDataBit
- 0x080008c4 GPIO_ReadInputData
- 0x080008e0 GPIO_ReadOutputDataBit
- 0x0800091c GPIO_ReadOutputData
- 0x08000938 GPIO_SetBits
- 0x08000954 GPIO_ResetBits
- 0x08000970 GPIO_WriteBit
- 0x080009a0 GPIO_Write
- 0x080009bc GPIO_PinLockConfig
- 0x08000a00 GPIO_EventOutputConfig
- 0x08000a5c GPIO_EventOutputCmd
- 0x08000a7c GPIO_PinRemapConfig
- 0x08000b4c GPIO_EXTILineConfig
- .text 0x08000c04 0x978 lib/libstm32.a(stm32f10x_nvic.o)
- 0x08000c04 NVIC_DeInit
- 0x08000c88 NVIC_SCBDeInit
- 0x08000d4c NVIC_PriorityGroupConfig
- 0x08000d74 NVIC_Init
- 0x08000ed8 NVIC_StructInit
- 0x08000f0c NVIC_SETPRIMASK
- 0x08000f18 NVIC_RESETPRIMASK
- 0x08000f24 NVIC_SETFAULTMASK
- 0x08000f30 NVIC_RESETFAULTMASK
- 0x08000f3c NVIC_BASEPRICONFIG
- 0x08000f58 NVIC_GetBASEPRI
- 0x08000f68 NVIC_GetCurrentPendingIRQChannel
- 0x08000f90 NVIC_GetIRQChannelPendingBitStatus
- 0x08000ff8 NVIC_SetIRQChannelPendingBit
- 0x08001018 NVIC_ClearIRQChannelPendingBit
- 0x08001054 NVIC_GetCurrentActiveHandler
- 0x08001078 NVIC_GetIRQChannelActiveBitStatus
- 0x080010e0 NVIC_GetCPUID
- 0x080010f8 NVIC_SetVectorTable
- 0x08001128 NVIC_GenerateSystemReset
- 0x08001144 NVIC_GenerateCoreReset
- 0x08001160 NVIC_SystemLPConfig
- 0x080011b8 NVIC_SystemHandlerConfig
- 0x08001224 NVIC_SystemHandlerPriorityConfig
- 0x08001334 NVIC_GetSystemHandlerPendingBitStatus
- 0x080013a0 NVIC_SetSystemHandlerPendingBit
- 0x080013e4 NVIC_ClearSystemHandlerPendingBit
- 0x0800142c NVIC_GetSystemHandlerActiveBitStatus
- 0x08001494 NVIC_GetFaultHandlerSources
- 0x0800152c NVIC_GetFaultAddress
- .text 0x0800157c 0xa6c lib/libstm32.a(stm32f10x_rcc.o)
- 0x0800157c RCC_DeInit
- 0x08001660 RCC_HSEConfig
- 0x080016e8 RCC_WaitForHSEStartUp
- 0x08001758 RCC_AdjustHSICalibrationValue
- 0x080017a0 RCC_HSICmd
- 0x080017c0 RCC_PLLConfig
- 0x0800180c RCC_PLLCmd
- 0x0800182c RCC_SYSCLKConfig
- 0x08001870 RCC_GetSYSCLKSource
- 0x08001890 RCC_HCLKConfig
- 0x080018d4 RCC_PCLK1Config
- 0x08001918 RCC_PCLK2Config
- 0x08001960 RCC_ITConfig
- 0x080019c4 RCC_USBCLKConfig
- 0x080019e4 RCC_ADCCLKConfig
- 0x08001a28 RCC_LSEConfig
- 0x08001a84 RCC_LSICmd
- 0x08001aa4 RCC_RTCCLKConfig
- 0x08001ad0 RCC_RTCCLKCmd
- 0x08001af0 RCC_GetClocksFreq
- 0x08001cbc RCC_AHBPeriphClockCmd
- 0x08001d14 RCC_APB2PeriphClockCmd
- 0x08001d6c RCC_APB1PeriphClockCmd
- 0x08001dc4 RCC_APB2PeriphResetCmd
- 0x08001e1c RCC_APB1PeriphResetCmd
- 0x08001e74 RCC_BackupResetCmd
- 0x08001e94 RCC_ClockSecuritySystemCmd
- 0x08001eb4 RCC_MCOConfig
- 0x08001ed4 RCC_GetFlagStatus
- 0x08001f64 RCC_ClearFlag
- 0x08001f88 RCC_GetITStatus
- 0x08001fc8 RCC_ClearITPendingBit
- .text 0x08001fe8 0x6e lib/libstm32.a(cortexm3_macro.o)
- 0x08001fe8 __WFI
- 0x08001fec __WFE
- 0x08001ff0 __SEV
- 0x08001ff4 __ISB
- 0x08001ffa __DSB
- 0x08002000 __DMB
- 0x08002006 __SVC
- 0x0800200a __MRS_CONTROL
- 0x08002010 __MSR_CONTROL
- 0x0800201a __MRS_PSP
- 0x08002020 __MSR_PSP
- 0x08002026 __MRS_MSP
- 0x0800202c __MSR_MSP
- 0x08002032 __SETPRIMASK
- 0x08002036 __RESETPRIMASK
- 0x0800203a __SETFAULTMASK
- 0x0800203e __RESETFAULTMASK
- 0x08002042 __BASEPRICONFIG
- 0x08002048 __GetBASEPRI
- 0x0800204e __REV_HalfWord
- 0x08002052 __REV_Word
- *fill* 0x08002056 0x2 00
- .text 0x08002058 0x88 lib/libstm32.a(stm32f10x_vector.o)
- 0x08002058 Reset_Handler
- *(.text.*)
- *(.rodata)
- .rodata 0x080020e0 0x14 lib/libstm32.a(stm32f10x_rcc.o)
- *(.rodata*)
- *(.glue_7)
- .glue_7 0x00000000 0x0 linker stubs
- *(.glue_7t)
- .glue_7t 0x00000000 0x0 linker stubs
- 0x080020f4 . = ALIGN (0x4)
- 0x080020f4 _etext = .
- 0x080020f4 _sidata = _etext
-
-.vfp11_veneer 0x20000000 0x0
- .vfp11_veneer 0x00000000 0x0 linker stubs
-
-.v4_bx 0x20000000 0x0
- .v4_bx 0x00000000 0x0 linker stubs
-
-.data 0x20000000 0x0 load address 0x080020f4
- 0x20000000 . = ALIGN (0x4)
- 0x20000000 _sdata = .
- *(.data)
- *(.data.*)
- 0x20000000 . = ALIGN (0x4)
- 0x20000000 _edata = .
-
-.bss 0x20000000 0x10
- 0x20000000 . = ALIGN (0x4)
- 0x20000000 _sbss = .
- *(.bss)
- .bss 0x20000000 0x8 lib/libstm32.a(stm32f10x_rcc.o)
- *(COMMON)
- COMMON 0x20000008 0x8 main.o
- 0x20000008 HSEStartUpStatus
- 0x2000000c GPIO_InitStructure
- 0x20000010 . = ALIGN (0x4)
- 0x20000010 _ebss = .
- 0x20000010 PROVIDE (end, _ebss)
- 0x20000010 PROVIDE (_end, _ebss)
-
-._usrstack 0x20000010 0x100
- 0x20000010 . = ALIGN (0x4)
- 0x20000010 _susrstack = .
- 0x20000110 . = (. + _Minimum_Stack_Size)
- *fill* 0x20000010 0x100 00
- 0x20000110 . = ALIGN (0x4)
- 0x20000110 _eusrstack = .
-
-.b1text
- *(.b1text)
- *(.b1rodata)
- *(.b1rodata*)
-
-.eb0text
- *(.eb0text)
- *(.eb0rodata)
- *(.eb0rodata*)
-
-.eb1text
- *(.eb1text)
- *(.eb1rodata)
- *(.eb1rodata*)
-
-.eb2text
- *(.eb2text)
- *(.eb2rodata)
- *(.eb2rodata*)
-
-.eb3text
- *(.eb3text)
- *(.eb3rodata)
- *(.eb3rodata*)
- 0x20000110 __exidx_start = .
- 0x20000110 __exidx_end = .
-
-/DISCARD/
- libc.a(*)
- libm.a(*)
- libgcc.a(*)
-
-.stab
- *(.stab)
-
-.stabstr
- *(.stabstr)
-
-.stab.excl
- *(.stab.excl)
-
-.stab.exclstr
- *(.stab.exclstr)
-
-.stab.index
- *(.stab.index)
-
-.stab.indexstr
- *(.stab.indexstr)
-
-.ARM.attributes
- 0x00000000 0x2f
- .ARM.attributes
- 0x00000000 0x14 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .ARM.attributes
- 0x00000014 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- .ARM.attributes
- 0x00000044 0x14 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .ARM.attributes
- 0x00000058 0x31 main.o
- .ARM.attributes
- 0x00000089 0x31 stm32f10x_it.o
- .ARM.attributes
- 0x000000ba 0x31 lib/libstm32.a(stm32f10x_flash.o)
- .ARM.attributes
- 0x000000eb 0x31 lib/libstm32.a(stm32f10x_gpio.o)
- .ARM.attributes
- 0x0000011c 0x31 lib/libstm32.a(stm32f10x_nvic.o)
- .ARM.attributes
- 0x0000014d 0x31 lib/libstm32.a(stm32f10x_rcc.o)
- .ARM.attributes
- 0x0000017e 0x21 lib/libstm32.a(cortexm3_macro.o)
- .ARM.attributes
- 0x0000019f 0x31 lib/libstm32.a(stm32f10x_vector.o)
- .ARM.attributes
- 0x000001d0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- .ARM.attributes
- 0x00000200 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- .ARM.attributes
- 0x00000230 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .ARM.attributes
- 0x00000260 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- .ARM.attributes
- 0x00000290 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- .ARM.attributes
- 0x000002c0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .ARM.attributes
- 0x000002f0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- .ARM.attributes
- 0x00000320 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- .ARM.attributes
- 0x00000350 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- .ARM.attributes
- 0x00000380 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- .ARM.attributes
- 0x000003b0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- .ARM.attributes
- 0x000003e0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- .ARM.attributes
- 0x00000410 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- .ARM.attributes
- 0x00000440 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- .ARM.attributes
- 0x00000470 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- .ARM.attributes
- 0x000004a0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- .ARM.attributes
- 0x000004d0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- .ARM.attributes
- 0x00000500 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- .ARM.attributes
- 0x00000530 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- .ARM.attributes
- 0x00000560 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- .ARM.attributes
- 0x00000590 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- .ARM.attributes
- 0x000005c0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- .ARM.attributes
- 0x000005f0 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-readr.o)
- .ARM.attributes
- 0x00000620 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- .ARM.attributes
- 0x00000650 0x30 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
- .ARM.attributes
- 0x00000680 0x16 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtn.o
-
-.comment 0x00000000 0x11
- *(.comment)
- .comment 0x00000000 0x11 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtbegin.o
- 0x12 (size before relaxing)
- .comment 0x00000000 0x12 main.o
- .comment 0x00000000 0x12 stm32f10x_it.o
- .comment 0x00000000 0x12 lib/libstm32.a(stm32f10x_flash.o)
- .comment 0x00000000 0x12 lib/libstm32.a(stm32f10x_gpio.o)
- .comment 0x00000000 0x12 lib/libstm32.a(stm32f10x_nvic.o)
- .comment 0x00000000 0x12 lib/libstm32.a(stm32f10x_rcc.o)
- .comment 0x00000000 0x12 lib/libstm32.a(stm32f10x_vector.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-impure.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-readr.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-reent.o)
- .comment 0x00000000 0x12 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crtend.o
-
-.debug
- *(.debug)
-
-.line
- *(.line)
-
-.debug_srcinfo
- *(.debug_srcinfo)
-
-.debug_sfnames
- *(.debug_sfnames)
-
-.debug_aranges 0x00000000 0x450
- *(.debug_aranges)
- .debug_aranges
- 0x00000000 0x28 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/crti.o
- .debug_aranges
- 0x00000028 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/crt0.o
- .debug_aranges
- 0x00000048 0x20 main.o
- .debug_aranges
- 0x00000068 0x20 stm32f10x_it.o
- .debug_aranges
- 0x00000088 0x20 lib/libstm32.a(stm32f10x_flash.o)
- .debug_aranges
- 0x000000a8 0x20 lib/libstm32.a(stm32f10x_gpio.o)
- .debug_aranges
- 0x000000c8 0x20 lib/libstm32.a(stm32f10x_nvic.o)
- .debug_aranges
- 0x000000e8 0x20 lib/libstm32.a(stm32f10x_rcc.o)
- .debug_aranges
- 0x00000108 0x20 lib/libstm32.a(cortexm3_macro.o)
- .debug_aranges
- 0x00000128 0x20 lib/libstm32.a(stm32f10x_vector.o)
- .debug_aranges
- 0x00000148 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-atexit.o)
- .debug_aranges
- 0x00000168 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-exit.o)
- .debug_aranges
- 0x00000188 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-init.o)
- .debug_aranges
- 0x000001a8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-memset.o)
- .debug_aranges
- 0x000001c8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-syscalls.o)
- .debug_aranges
- 0x000001e8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__atexit.o)
- .debug_aranges
- 0x00000208 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-__call_atexit.o)
- .debug_aranges
- 0x00000228 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-errno.o)
- .debug_aranges
- 0x00000248 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-findfp.o)
- .debug_aranges
- 0x00000268 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fwalk.o)
- .debug_aranges
- 0x00000288 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mallocr.o)
- .debug_aranges
- 0x000002a8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-mlock.o)
- .debug_aranges
- 0x000002c8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-sbrkr.o)
- .debug_aranges
- 0x000002e8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-stdio.o)
- .debug_aranges
- 0x00000308 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-strlen.o)
- .debug_aranges
- 0x00000328 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-writer.o)
- .debug_aranges
- 0x00000348 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-closer.o)
- .debug_aranges
- 0x00000368 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fclose.o)
- .debug_aranges
- 0x00000388 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-fflush.o)
- .debug_aranges
- 0x000003a8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-freer.o)
- .debug_aranges
- 0x000003c8 0x20 /home/lxir/opt/arm/lib/gcc/arm-none-eabi/4.5.0/../../../../arm-none-eabi/lib/libc.a(lib_a-lseekr.o)
- .debug_aranges
- 0x0...
[truncated message content] |
|
From: Xavier L. <Sup...@us...> - 2010-04-17 14:54:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 1f9606b5d51a8dce38491bf562793497196dd2f5 (commit)
from 71889e232097e5870459effdc465bb904ebd04fa (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1f9606b5d51a8dce38491bf562793497196dd2f5
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Apr 17 16:50:05 2010 +0200
Added a project template for the STM32 ARM processor
* It uses ST libraries
* It will blink the LED on the Olimex STM32-P103 developpement board
* It contains openocd configuration to flash the previously mentioned board
usage :
* clean : make clean
* compile : make all
* flash : make flash
-----------------------------------------------------------------------
Changes:
diff --git a/arm/STM32/template/jtag/flash.cfg b/arm/STM32/template/jtag/flash.cfg
new file mode 100644
index 0000000..75d09b1
--- /dev/null
+++ b/arm/STM32/template/jtag/flash.cfg
@@ -0,0 +1,7 @@
+init
+reset halt
+stm32x mass_erase 0
+flash write_bank 0 main.bin 0
+reset init
+reset run
+shutdown
\ No newline at end of file
diff --git a/arm/STM32/template/jtag/openocd.cfg b/arm/STM32/template/jtag/openocd.cfg
new file mode 100644
index 0000000..0f3a9a2
--- /dev/null
+++ b/arm/STM32/template/jtag/openocd.cfg
@@ -0,0 +1,84 @@
+#
+# Olimex ARM-USB-OCD
+#
+# http://www.olimex.com/dev/arm-usb-ocd.html
+#
+
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003
+
+# script for stm32
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# Use the correct size for the card
+set WORKAREASIZE 0x5000
+
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ # FIXME this never gets used to override defaults...
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0008
+ # Section 29.6.2
+ # Low density devices, Rev A
+ set _BSTAPID1 0x06412041
+ # Medium density devices, Rev A
+ set _BSTAPID2 0x06410041
+ # Medium density devices, Rev B and Rev Z
+ set _BSTAPID3 0x16410041
+ # High density devices, Rev A
+ set _BSTAPID4 0x06414041
+ # Connectivity line devices, Rev A and Rev Z
+ set _BSTAPID5 0x06418041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+ -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+ -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
+
diff --git a/arm/STM32/template/jtag/target.ini b/arm/STM32/template/jtag/target.ini
new file mode 100644
index 0000000..da18158
--- /dev/null
+++ b/arm/STM32/template/jtag/target.ini
@@ -0,0 +1,93 @@
+#
+# GDB init file for STM32x family
+#
+
+set complaints 1
+set output-radix 16
+set input-radix 16
+
+# GDB must be set to big endian mode first if needed.
+#set endian little
+
+# add str9lib src to gdb search path
+#dir /cygdrive/c/progra~1/anglia/idealist/examples/stm32/libstr32x/src
+#dir C:/Progra~1/Anglia/IDEaliST/examples/stm32/libstm32x/src
+
+# change gdb prompt
+set prompt (arm-gdb)
+
+# You will need to change this to reflect the address of your jtag interface.
+#target remote localhost:2000
+
+# The libremote daemon must be set to big endian before the
+# executable is loaded.
+#monitor endian little
+
+# Increase the packet size to improve download speed.
+# to view current setting use:
+# show remote memory-write-packet-size
+
+set remote memory-write-packet-size 1024
+set remote memory-write-packet-size fixed
+
+set remote memory-read-packet-size 1024
+set remote memory-read-packet-size fixed
+set remote hardware-watchpoint-limit 6
+set remote hardware-breakpoint-limit 6
+
+# Load the program executable (ram only)
+#load
+
+# Set a breakpoint at main().
+#b main
+
+# Run to the breakpoint.
+#c
+
+#
+# GDB command helpers
+#
+
+#
+# reset and map 0 to internal ram
+#
+
+define ramreset
+reset
+set *(int*)0xE000ED08 = 0x20000000
+echo Internal RAM set to address 0x0.
+end
+
+#
+# reset and map 0 to flash
+#
+
+define flashreset
+reset
+thb main
+echo Internal Flash set to address 0x0.
+end
+
+#
+# reset target
+#
+
+define reset
+monitor reset
+end
+
+document ramreset
+ramreset
+Causes a target reset, remaps Internal RAM to address 0x0.
+end
+
+document flashreset
+flashreset
+Causes a target reset, remaps Internal Flash to address 0x0.
+A temporary breakpoint is set at start of function main
+end
+
+document reset
+reset
+Causes a target reset.
+end
diff --git a/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld b/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld
new file mode 100644
index 0000000..5e4ce87
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_128K_20K_FLASH.ld
@@ -0,0 +1,29 @@
+/*
+Linker script for STM32F10x
+Copyright RAISONANCE 2007 (modified by Lanchon 1-Feb-2008)
+You can use, copy and distribute this file freely, but without any waranty.
+Configure memory sizes, end of stack and boot mode for your project here.
+*/
+
+
+/* include the common STM32F10x sub-script */
+INCLUDE "STM32_COMMON.ld"
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K /* also change _estack below */
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
+ FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+ EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+}
+
+/* highest address of the user mode stack */
+_estack = 0x20005000;
+
+/* include the section management sub-script */
+/* (either "STM32_SEC_FLASH.ld" or "STM32_SEC_RAM.ld") */
+INCLUDE "STM32_SEC_FLASH.ld"
diff --git a/arm/STM32/template/lib/STM32_COMMON.ld b/arm/STM32/template/lib/STM32_COMMON.ld
new file mode 100644
index 0000000..6794c70
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_COMMON.ld
@@ -0,0 +1,164 @@
+/*
+Common part of the linker scripts for STR32 devices
+Copyright RAISONANCE 2007
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+
+/* default stack sizes.
+
+These are used by the startup in order to allocate stacks for the different modes.
+*/
+
+__Stack_Size = 1024 ;
+
+PROVIDE ( _Stack_Size = __Stack_Size ) ;
+
+__Stack_Init = _estack - __Stack_Size ;
+
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
+PROVIDE ( _Stack_Init = __Stack_Init ) ;
+
+/*
+There will be a link error if there is not this amount of RAM free at the end.
+*/
+_Minimum_Stack_Size = 0x100 ;
+
+
+
+/*
+this sends all unreferenced IRQHandlers to reset
+*/
+
+
+PROVIDE ( Undefined_Handler = 0 ) ;
+PROVIDE ( SWI_Handler = 0 ) ;
+PROVIDE ( IRQ_Handler = 0 ) ;
+PROVIDE ( Prefetch_Handler = 0 ) ;
+PROVIDE ( Abort_Handler = 0 ) ;
+PROVIDE ( FIQ_Handler = 0 ) ;
+
+PROVIDE ( NMIException = 0 ) ;
+PROVIDE ( HardFaultException = 0 ) ;
+PROVIDE ( MemManageException = 0 ) ;
+PROVIDE ( BusFaultException = 0 ) ;
+PROVIDE ( UsageFaultException = 0 ) ;
+PROVIDE ( SVCHandler = 0 ) ;
+PROVIDE ( DebugMonitor = 0 ) ;
+PROVIDE ( PendSVC = 0 ) ;
+PROVIDE ( SysTickHandler = 0 ) ;
+PROVIDE ( WWDG_IRQHandler = 0 ) ;
+PROVIDE ( PVD_IRQHandler = 0 ) ;
+PROVIDE ( TAMPER_IRQHandler = 0 ) ;
+PROVIDE ( RTC_IRQHandler = 0 ) ;
+PROVIDE ( FLASH_IRQHandler = 0 ) ;
+PROVIDE ( RCC_IRQHandler = 0 ) ;
+PROVIDE ( EXTI0_IRQHandler = 0 ) ;
+PROVIDE ( EXTI1_IRQHandler = 0 ) ;
+PROVIDE ( EXTI2_IRQHandler = 0 ) ;
+PROVIDE ( EXTI3_IRQHandler = 0 ) ;
+PROVIDE ( EXTI4_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel1_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel2_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel3_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel4_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel5_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel6_IRQHandler = 0 ) ;
+PROVIDE ( DMAChannel7_IRQHandler = 0 ) ;
+PROVIDE ( ADC_IRQHandler = 0 ) ;
+PROVIDE ( USB_HP_CAN_TX_IRQHandler = 0 ) ;
+PROVIDE ( USB_LP_CAN_RX0_IRQHandler = 0 ) ;
+PROVIDE ( CAN_RX1_IRQHandler = 0 ) ;
+PROVIDE ( CAN_SCE_IRQHandler = 0 ) ;
+PROVIDE ( EXTI9_5_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_BRK_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_UP_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_TRG_COM_IRQHandler = 0 ) ;
+PROVIDE ( TIM1_CC_IRQHandler = 0 ) ;
+PROVIDE ( TIM2_IRQHandler = 0 ) ;
+PROVIDE ( TIM3_IRQHandler = 0 ) ;
+PROVIDE ( TIM4_IRQHandler = 0 ) ;
+PROVIDE ( I2C1_EV_IRQHandler = 0 ) ;
+PROVIDE ( I2C1_ER_IRQHandler = 0 ) ;
+PROVIDE ( I2C2_EV_IRQHandler = 0 ) ;
+PROVIDE ( I2C2_ER_IRQHandler = 0 ) ;
+PROVIDE ( SPI1_IRQHandler = 0 ) ;
+PROVIDE ( SPI2_IRQHandler = 0 ) ;
+PROVIDE ( USART1_IRQHandler = 0 ) ;
+PROVIDE ( USART2_IRQHandler = 0 ) ;
+PROVIDE ( USART3_IRQHandler = 0 ) ;
+PROVIDE ( EXTI15_10_IRQHandler = 0 ) ;
+PROVIDE ( RTCAlarm_IRQHandler = 0 ) ;
+PROVIDE ( USBWakeUp_IRQHandler = 0 ) ;
+
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/*this allows to compile the ST lib in "non-debug" mode*/
+
+
+/* Peripheral and SRAM base address in the alias region */
+PERIPH_BB_BASE = 0x42000000;
+SRAM_BB_BASE = 0x22000000;
+
+/* Peripheral and SRAM base address in the bit-band region */
+SRAM_BASE = 0x20000000;
+PERIPH_BASE = 0x40000000;
+
+/* Flash registers base address */
+PROVIDE ( FLASH_BASE = 0x40022000);
+/* Flash Option Bytes base address */
+PROVIDE ( OB_BASE = 0x1FFFF800);
+
+/* Peripheral memory map */
+APB1PERIPH_BASE = PERIPH_BASE ;
+APB2PERIPH_BASE = (PERIPH_BASE + 0x10000) ;
+AHBPERIPH_BASE = (PERIPH_BASE + 0x20000) ;
+
+PROVIDE ( TIM2 = (APB1PERIPH_BASE + 0x0000) ) ;
+PROVIDE ( TIM3 = (APB1PERIPH_BASE + 0x0400) ) ;
+PROVIDE ( TIM4 = (APB1PERIPH_BASE + 0x0800) ) ;
+PROVIDE ( RTC = (APB1PERIPH_BASE + 0x2800) ) ;
+PROVIDE ( WWDG = (APB1PERIPH_BASE + 0x2C00) ) ;
+PROVIDE ( IWDG = (APB1PERIPH_BASE + 0x3000) ) ;
+PROVIDE ( SPI2 = (APB1PERIPH_BASE + 0x3800) ) ;
+PROVIDE ( USART2 = (APB1PERIPH_BASE + 0x4400) ) ;
+PROVIDE ( USART3 = (APB1PERIPH_BASE + 0x4800) ) ;
+PROVIDE ( I2C1 = (APB1PERIPH_BASE + 0x5400) ) ;
+PROVIDE ( I2C2 = (APB1PERIPH_BASE + 0x5800) ) ;
+PROVIDE ( CAN = (APB1PERIPH_BASE + 0x6400) ) ;
+PROVIDE ( BKP = (APB1PERIPH_BASE + 0x6C00) ) ;
+PROVIDE ( PWR = (APB1PERIPH_BASE + 0x7000) ) ;
+
+PROVIDE ( AFIO = (APB2PERIPH_BASE + 0x0000) ) ;
+PROVIDE ( EXTI = (APB2PERIPH_BASE + 0x0400) ) ;
+PROVIDE ( GPIOA = (APB2PERIPH_BASE + 0x0800) ) ;
+PROVIDE ( GPIOB = (APB2PERIPH_BASE + 0x0C00) ) ;
+PROVIDE ( GPIOC = (APB2PERIPH_BASE + 0x1000) ) ;
+PROVIDE ( GPIOD = (APB2PERIPH_BASE + 0x1400) ) ;
+PROVIDE ( GPIOE = (APB2PERIPH_BASE + 0x1800) ) ;
+PROVIDE ( ADC1 = (APB2PERIPH_BASE + 0x2400) ) ;
+PROVIDE ( ADC2 = (APB2PERIPH_BASE + 0x2800) ) ;
+PROVIDE ( TIM1 = (APB2PERIPH_BASE + 0x2C00) ) ;
+PROVIDE ( SPI1 = (APB2PERIPH_BASE + 0x3000) ) ;
+PROVIDE ( USART1 = (APB2PERIPH_BASE + 0x3800) ) ;
+
+PROVIDE ( DMA = (AHBPERIPH_BASE + 0x0000) ) ;
+PROVIDE ( DMA_Channel1 = (AHBPERIPH_BASE + 0x0008) ) ;
+PROVIDE ( DMA_Channel2 = (AHBPERIPH_BASE + 0x001C) ) ;
+PROVIDE ( DMA_Channel3 = (AHBPERIPH_BASE + 0x0030) ) ;
+PROVIDE ( DMA_Channel4 = (AHBPERIPH_BASE + 0x0044) ) ;
+PROVIDE ( DMA_Channel5 = (AHBPERIPH_BASE + 0x0058) ) ;
+PROVIDE ( DMA_Channel6 = (AHBPERIPH_BASE + 0x006C) ) ;
+PROVIDE ( DMA_Channel7 = (AHBPERIPH_BASE + 0x0080) ) ;
+PROVIDE ( RCC = (AHBPERIPH_BASE + 0x1000) ) ;
+
+/* System Control Space memory map */
+SCS_BASE = 0xE000E000;
+
+PROVIDE ( SysTick = (SCS_BASE + 0x0010) ) ;
+PROVIDE ( NVIC = (SCS_BASE + 0x0100) ) ;
+PROVIDE ( SCB = (SCS_BASE + 0x0D00) ) ;
+
diff --git a/arm/STM32/template/lib/STM32_SEC_EXT.ld b/arm/STM32/template/lib/STM32_SEC_EXT.ld
new file mode 100644
index 0000000..3623d06
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_EXT.ld
@@ -0,0 +1,181 @@
+/*
+Common part of the linker scripts for STR71x devices in EXT mode
+(that is, the EXT is seen at 0)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+ /* the program code is stored in the .text section */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *crt0*.o (.text) /* Startup code */
+ *startup.o (.text) /* Startup code */
+ *(.text) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ _etext = .;
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = _etext ;
+ } >EXTMEMB0
+
+
+
+ /* This is the initialized data section
+ The program executes knowing that the data is in the RAM
+ but the loader puts the initial values in the EXTMEM.
+ It is one task of the startup to copy the initial values from EXTMEMB0 to RAM. */
+ .data : AT ( _etext )
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+
+
+ /* This is the uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ } >RAM
+
+ PROVIDE ( end = _ebss );
+ PROVIDE ( _end = _ebss );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ _eusrstack = ALIGN(4) ;
+ . = .;
+ } >RAM
+
+
+ /* this is the FLASH Bank0 */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+ .fb0text :
+ {
+ *(.fb0text) /* remaining code */
+ *(.fb0rodata) /* read-only data (constants) */
+ *(.fb0rodata*)
+ } >FLASH
+
+ /* this is the FLASH Bank1 */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+ .fb1text :
+ {
+ *(.fb1text) /* remaining code */
+ *(.fb1rodata) /* read-only data (constants) */
+ *(.fb1rodata*)
+ } >FLASHB1
+
+ /* EXTMEM Bank1 */
+ .eb1text :
+ {
+ *(.b1text) /* remaining code */
+ *(.b1rodata) /* read-only data (constants) */
+ *(.b1rodata*)
+ } >EXTMEMB1
+
+ /* EXTMEM Bank2 */
+ .eb2text :
+ {
+ *(.b2text) /* remaining code */
+ *(.b2rodata) /* read-only data (constants) */
+ *(.b2rodata*)
+ } >EXTMEMB2
+
+ /* EXTMEM Bank0 */
+ .eb3text :
+ {
+ *(.b3text) /* remaining code */
+ *(.b3rodata) /* read-only data (constants) */
+ *(.b3rodata*)
+ } >EXTMEMB3
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/STM32_SEC_FLASH.ld b/arm/STM32/template/lib/STM32_SEC_FLASH.ld
new file mode 100644
index 0000000..cd8c4fa
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_FLASH.ld
@@ -0,0 +1,201 @@
+/*
+Common part of the linker scripts for STR71x devices in FLASH mode
+(that is, the FLASH is seen at 0)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
+ .flashtext :
+ {
+ . = ALIGN(4);
+ *(.flashtext) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+
+ /* the program code is stored in the .text section, which goes to Flash */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ _etext = .;
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = _etext;
+ } >FLASH
+
+
+
+ /* This is the initialized data section
+ The program executes knowing that the data is in the RAM
+ but the loader puts the initial values in the FLASH (inidata).
+ It is one task of the startup to copy the initial values from FLASH to RAM. */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >RAM
+
+
+
+ /* This is the uninitialized data section */
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+ } >RAM
+
+ PROVIDE ( end = _ebss );
+ PROVIDE ( _end = _ebss );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ . = ALIGN(4);
+ _eusrstack = . ;
+ } >RAM
+
+
+
+ /* this is the FLASH Bank1 */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+ .b1text :
+ {
+ *(.b1text) /* remaining code */
+ *(.b1rodata) /* read-only data (constants) */
+ *(.b1rodata*)
+ } >FLASHB1
+
+ /* this is the EXTMEM */
+ /* the C or assembly source must explicitly place the code or data there
+ using the "section" attribute */
+
+ /* EXTMEM Bank0 */
+ .eb0text :
+ {
+ *(.eb0text) /* remaining code */
+ *(.eb0rodata) /* read-only data (constants) */
+ *(.eb0rodata*)
+ } >EXTMEMB0
+
+ /* EXTMEM Bank1 */
+ .eb1text :
+ {
+ *(.eb1text) /* remaining code */
+ *(.eb1rodata) /* read-only data (constants) */
+ *(.eb1rodata*)
+ } >EXTMEMB1
+
+ /* EXTMEM Bank2 */
+ .eb2text :
+ {
+ *(.eb2text) /* remaining code */
+ *(.eb2rodata) /* read-only data (constants) */
+ *(.eb2rodata*)
+ } >EXTMEMB2
+
+ /* EXTMEM Bank0 */
+ .eb3text :
+ {
+ *(.eb3text) /* remaining code */
+ *(.eb3rodata) /* read-only data (constants) */
+ *(.eb3rodata*)
+ } >EXTMEMB3
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/STM32_SEC_RAM.ld b/arm/STM32/template/lib/STM32_SEC_RAM.ld
new file mode 100644
index 0000000..4b44bb2
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_RAM.ld
@@ -0,0 +1,156 @@
+/*
+Common part of the linker scripts for STR71x devices in RAM mode
+(that is, the RAM is seen at 0 and we assume that the loader initializes it)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+/* Sections Definitions */
+
+SECTIONS
+{
+
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to start of RAM */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+ /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
+ .flashtext :
+ {
+ . = ALIGN(4);
+ *(.flashtext) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* the program code is stored in the .text section, which goes to RAM */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *(.text ) /* remaining code */
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ } >RAM
+
+ /* This is the uninitialized data section. */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = . ;
+ _etext = _ebss ;
+
+ } >RAM
+
+
+ /* read-only data (constants) */
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .idata :
+ {
+ _sidata = . ;
+ } > FLASH
+
+
+ /* This is the initialized data section. */
+ .data : AT ( _sidata )
+ {
+ . = ALIGN(4);
+ _sdata = .;
+ *(.data)
+ . = ALIGN(4);
+ _edata = . ;
+ } >RAM
+
+
+
+ PROVIDE ( end = _edata );
+ PROVIDE ( _end = _edata );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ . = ALIGN(4);
+ _eusrstack = . ;
+ } >RAM
+
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+/* .debug_info 0 : { * ( EXCLUDE_FILE ( *libc.a *libm.a ) .debug_info .gnu.linkonce.wi.*) }*/
+ .debug_info 0 : { * ( .debug_info .gnu.linkonce.wi.*) }
+/* .debug_abbrev 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_abbrev) }*/
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+/* .debug_line 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_line) }*/
+ .debug_line 0 : { *( .debug_line) }
+ /* (*(EXCLUDE_FILE (*crtend.o *otherfile.o) .ctors)) */
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/STM32_SEC_RAMonly.ld b/arm/STM32/template/lib/STM32_SEC_RAMonly.ld
new file mode 100644
index 0000000..fa90799
--- /dev/null
+++ b/arm/STM32/template/lib/STM32_SEC_RAMonly.ld
@@ -0,0 +1,157 @@
+/*
+Common part of the linker scripts for STR71x devices in RAM mode
+(that is, the RAM is seen at 0 and we assume that the loader initializes it)
+Copyright RAISONANCE 2005
+You can use, modify and distribute thisfile freely, but without any waranty.
+*/
+
+/* Sections Definitions */
+
+SECTIONS
+{
+
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to start of RAM */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ *(.isr_vector) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+
+ /* the beginning of the startup code is stored in the .flashtext section */
+ .flashtext :
+ {
+ . = ALIGN(4);
+
+ *crt0*.o (.flashtext) /* Startup code */
+ *startup.o (.flashtext) /* Startup code */
+ *(.flashtext) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+ /* the program code is stored in the .text section */
+ .text :
+ {
+ . = ALIGN(4);
+
+ *crt0*.o (.text) /* Startup code */
+ *startup.o (.text) /* Startup code */
+ *(.text ) /* remaining code */
+ *(.glue_7)
+ *(.glue_7t)
+
+ . = ALIGN(4);
+ } >RAM
+
+ /* This is the uninitialized data section. */
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+
+ *(.bss)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = . ;
+ _etext = _ebss ;
+
+ } >RAM
+
+
+ /* read-only data (constants) */
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } > RAM
+
+
+ /* This is the initialized data section. */
+ .data :
+ {
+ . = ALIGN(4);
+ _sidata = . ; /*this is useless but allows the same startup as for the other modes to be used.*/
+ _sdata = .;
+ *(.data)
+ . = ALIGN(4);
+ _edata = . ;
+ } >RAM
+
+
+
+ PROVIDE ( end = _edata );
+ PROVIDE ( _end = _edata );
+
+ /* This is the user stack section
+ This is just to check that there is enough RAM left for the User mode stack
+ It should generate an error if it's full.
+ */
+ ._usrstack :
+ {
+ . = ALIGN(4);
+ _susrstack = . ;
+
+ . = . + _Minimum_Stack_Size ;
+
+ . = ALIGN(4);
+ _eusrstack = . ;
+ } >RAM
+
+
+ __exidx_start = .;
+ __exidx_end = .;
+
+ /* after that it's only debugging information. */
+
+ /* remove the debugging information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+/* .debug_info 0 : { * ( EXCLUDE_FILE ( *libc.a *libm.a ) .debug_info .gnu.linkonce.wi.*) }*/
+ .debug_info 0 : { * ( .debug_info .gnu.linkonce.wi.*) }
+/* .debug_abbrev 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_abbrev) }*/
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+/* .debug_line 0 : { *(EXCLUDE_FILE ( *libc.a *libm.a ) .debug_line) }*/
+ .debug_line 0 : { *( .debug_line) }
+ /* (*(EXCLUDE_FILE (*crtend.o *otherfile.o) .ctors)) */
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
+
+
+
diff --git a/arm/STM32/template/lib/inc/cortexm3_macro.h b/arm/STM32/template/lib/inc/cortexm3_macro.h
new file mode 100644
index 0000000..822d019
--- /dev/null
+++ b/arm/STM32/template/lib/inc/cortexm3_macro.h
@@ -0,0 +1,51 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : cortexm3_macro.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : Header file for cortexm3_macro.s.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void __WFI(void);
+void __WFE(void);
+void __SEV(void);
+void __ISB(void);
+void __DSB(void);
+void __DMB(void);
+void __SVC(void);
+u32 __MRS_CONTROL(void);
+void __MSR_CONTROL(u32 Control);
+u32 __MRS_PSP(void);
+void __MSR_PSP(u32 TopOfProcessStack);
+u32 __MRS_MSP(void);
+void __MSR_MSP(u32 TopOfMainStack);
+void __SETPRIMASK(void);
+void __RESETPRIMASK(void);
+void __SETFAULTMASK(void);
+void __RESETFAULTMASK(void);
+void __BASEPRICONFIG(u32 NewPriority);
+u32 __GetBASEPRI(void);
+u16 __REV_HalfWord(u16 Data);
+u32 __REV_Word(u32 Data);
+
+#endif /* __CORTEXM3_MACRO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_adc.h b/arm/STM32/template/lib/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..452d04e
--- /dev/null
+++ b/arm/STM32/template/lib/inc/stm32f10x_adc.h
@@ -0,0 +1,265 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_adc.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the functions prototypes for the
+* ADC firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* ADC Init structure definition */
+typedef struct
+{
+ u32 ADC_Mode;
+ FunctionalState ADC_ScanConvMode;
+ FunctionalState ADC_ContinuousConvMode;
+ u32 ADC_ExternalTrigConv;
+ u32 ADC_DataAlign;
+ u8 ADC_NbrOfChannel;
+}ADC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* ADC dual mode -------------------------------------------------------------*/
+#define ADC_Mode_Independent ((u32)0x00000000)
+#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
+#define ADC_Mode_InjecSimult ((u32)0x00050000)
+#define ADC_Mode_RegSimult ((u32)0x00060000)
+#define ADC_Mode_FastInterl ((u32)0x00070000)
+#define ADC_Mode_SlowInterl ((u32)0x00080000)
+#define ADC_Mode_AlterTrig ((u32)0x00090000)
+
+#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \
+ (MODE == ADC_Mode_RegInjecSimult) || \
+ (MODE == ADC_Mode_RegSimult_AlterTrig) || \
+ (MODE == ADC_Mode_InjecSimult_FastInterl) || \
+ (MODE == ADC_Mode_InjecSimult_SlowInterl) || \
+ (MODE == ADC_Mode_InjecSimult) || \
+ (MODE == ADC_Mode_RegSimult) || \
+ (MODE == ADC_Mode_FastInterl) || \
+ (MODE == ADC_Mode_SlowInterl) || \
+ (MODE == ADC_Mode_AlterTrig))
+
+/* ADC extrenal trigger sources for regular channels conversion --------------*/
+#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
+#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
+#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)
+#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
+
+#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \
+ (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \
+ (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \
+ (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \
+ (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \
+ (TRIG1 == ADC_ExternalTrigConv_None))
+
+/* ADC data align ------------------------------------------------------------*/
+#define ADC_DataAlign_Right ((u32)0x00000000)
+#define ADC_DataAlign_Left ((u32)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \
+ (ALIGN == ADC_DataAlign_Left))
+
+/* ADC channels --------------------------------------------------------------*/
+#define ADC_Channel_0 ((u8)0x00)
+#define ADC_Channel_1 ((u8)0x01)
+#define ADC_Channel_2 ((u8)0x02)
+#define ADC_Channel_3 ((u8)0x03)
+#define ADC_Channel_4 ((u8)0x04)
+#define ADC_Channel_5 ((u8)0x05)
+#define ADC_Channel_6 ((u8)0x06)
+#define ADC_Channel_7 ((u8)0x07)
+#define ADC_Channel_8 ((u8)0x08)
+#define ADC_Channel_9 ((u8)0x09)
+#define ADC_Channel_10 ((u8)0x0A)
+#define ADC_Channel_11 ((u8)0x0B)
+#define ADC_Channel_12 ((u8)0x0C)
+#define ADC_Channel_13 ((u8)0x0D)
+#define ADC_Channel_14 ((u8)0x0E)
+#define ADC_Channel_15 ((u8)0x0F)
+#define ADC_Channel_16 ((u8)0x10)
+#define ADC_Channel_17 ((u8)0x11)
+
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \
+ (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \
+ (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \
+ (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \
+ (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \
+ (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \
+ (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \
+ (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \
+ (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))
+
+/* ADC sampling times --------------------------------------------------------*/
+#define ADC_SampleTime_1Cycles5 ((u8)0x00)
+#define ADC_SampleTime_7Cycles5 ((u8)0x01)
+#define ADC_SampleTime_13Cycles5 ((u8)0x02)
+#define ADC_SampleTime_28Cycles5 ((u8)0x03)
+#define ADC_SampleTime_41Cycles5 ((u8)0x04)
+#define ADC_SampleTime_55Cycles5 ((u8)0x05)
+#define ADC_SampleTime_71Cycles5 ((u8)0x06)
+#define ADC_SampleTime_239Cycles5 ((u8)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \
+ (TIME == ADC_SampleTime_7Cycles5) || \
+ (TIME == ADC_SampleTime_13Cycles5) || \
+ (TIME == ADC_SampleTime_28Cycles5) || \
+ (TIME == ADC_SampleTime_41Cycles5) || \
+ (TIME == ADC_SampleTime_55Cycles5) || \
+ (TIME == ADC_SampleTime_71Cycles5) || \
+ (TIME == ADC_SampleTime_239Cycles5))
+
+/* ADC extrenal trigger sources for injected channels conversion -------------*/
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)
+#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
+
+#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \
+ (TRIG == ADC_ExternalTrigInjecConv_None))
+
+/* ADC injected channel selection --------------------------------------------*/
+#define ADC_InjectedChannel_1 ((u8)0x14)
+#define ADC_InjectedChannel_2 ((u8)0x18)
+#define ADC_InjectedChannel_3 ((u8)0x1C)
+#define ADC_InjectedChannel_4 ((u8)0x20)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \
+ (CHANNEL == ADC_InjectedChannel_2) || \
+ (CHANNEL == ADC_InjectedChannel_3) || \
+ (CHANNEL == ADC_InjectedChannel_4))
+
+/* ADC analog watchdog selection ---------------------------------------------*/
+#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
+#define ADC_AnalogWatchdog_None ((u32)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ (WATCHDOG == ADC_AnalogWatchdog_None))
+
+/* ADC interrupts definition -------------------------------------------------*/
+#define ADC_IT_EOC ((u16)0x0220)
+#define ADC_IT_AWD ((u16)0x0140)
+#define ADC_IT_JEOC ((u16)0x0480)
+
+#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))
+#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \
+ (IT == ADC_IT_JEOC))
+
+/* ADC flags definition ------------------------------------------------------*/
+#define ADC_FLAG_AWD ((u8)0x01)
+#define ADC_FLAG_EOC ((u8)0x02)
+#define ADC_FLAG_JEOC ((u8)0x04)
+#define ADC_FLAG_JSTRT ((u8)0x08)
+#define ADC_FLAG_STRT ((u8)0x10)
+
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \
+ (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \
+ (FLAG == ADC_FLAG_STRT))
+
+/* ADC thresholds ------------------------------------------------------------*/
+#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)
+
+/* ADC injected offset -------------------------------------------------------*/
+#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)
+
+/* ADC injected length -------------------------------------------------------*/
+#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))
+
+/* ADC injected rank ---------------------------------------------------------*/
+#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))
+
+/* ADC regular length --------------------------------------------------------*/
+#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))
+
+/* ADC regular rank ----------------------------------------------------------*/
+#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))
+
+/* ADC regular discontinuous mode number -------------------------------------*/
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
+u32 ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
+
+#endif /*__STM32F10x_ADC_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_bkp.h b/arm/STM32/template/lib/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..79e702f
--- /dev/null
+++ b/arm/STM32/template/lib/inc/stm32f10x_bkp.h
@@ -0,0 +1,80 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_bkp.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the functions prototypes for the
+* BKP firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Tamper Pin active level */
+#define BKP_TamperPinLevel_High ((u16)0x0000)
+#define BKP_TamperPinLevel_Low ((u16)0x0001)
+
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \
+ (LEVEL == BKP_TamperPinLevel_Low))
+
+/* RTC output source to output on the Tamper pin */
+#define BKP_RTCOutputSource_None ((u16)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)
+#define BKP_RTCOutputSource_Alarm ((u16)0x0100)
+#define BKP_RTCOutputSource_Second ((u16)0x0300)
+
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) ((SOURCE == BKP_RTCOutputSource_None) || \
+ (SOURCE == BKP_RTCOutputSource_CalibClock) || \
+ (SOURCE == BKP_RTCOutputSource_Alarm) || \
+ (SOURCE == BKP_RTCOutputSource_Second))
+
+/* Data Backup Register */
+#define BKP_DR1 ((u16)0x0004)
+#define BKP_DR2 ((u16)0x0008)
+#define BKP_DR3 ((u16)0x000C)
+#define BKP_DR4 ((u16)0x0010)
+#define BKP_DR5 ((u16)0x0014)
+#define BKP_DR6 ((u16)0x0018)
+#define BKP_DR7 ((u16)0x001C)
+#define BKP_DR8 ((u16)0x0020)
+#define BKP_DR9 ((u16)0x0024)
+#define BKP_DR10 ((u16)0x0028)
+
+#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \
+ (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \
+ (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \
+ (DR == BKP_DR10))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);
+u16 BKP_ReadBackupRegister(u16 BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#endif /* __STM32F10x_BKP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/arm/STM32/template/lib/inc/stm32f10x_can.h b/arm/STM32/template/lib/inc/stm32f10x_can.h
new file mode 100644
index 0000000..a8c170d
--- /dev/null
+++ b/arm/STM32/template/lib/inc/stm32f10x_can.h
@@ -0,0 +1,263 @@
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_can.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the functions prototypes for the
+* CAN firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_map.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* CAN init structure definition */
+typedef struct
+{
+ FunctionalState CAN_TTCM;
+ FunctionalState CAN_ABOM;
+ FunctionalState CAN_AWUM;
+ FunctionalState CAN_NART;
+ FunctionalState CAN_RFLM;
+ FunctionalState ...
[truncated message content] |
|
From: Pierre C. <Sup...@us...> - 2010-01-31 18:05:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 71889e232097e5870459effdc465bb904ebd04fa (commit)
via d9aeea08f2e273be6e743427a0dd6a543b27da40 (commit)
from 1e545ef9f7ae38acea030fec3f15b1c1a9fb5e58 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 71889e232097e5870459effdc465bb904ebd04fa
Author: chambart <cha...@cr...>
Date: Sun Jan 31 19:05:07 2010 +0100
pong is still useless but working !
commit d9aeea08f2e273be6e743427a0dd6a543b27da40
Author: chambart <cha...@cr...>
Date: Thu Jan 28 23:26:57 2010 +0100
draw more things on pong
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/examples/pong/draw.vhd b/fpga/examples/pong/draw.vhd
index 57fe679..7fbe3b3 100644
--- a/fpga/examples/pong/draw.vhd
+++ b/fpga/examples/pong/draw.vhd
@@ -6,94 +6,70 @@ use ieee.std_logic_arith.all;
entity draw is
generic (
size_x : positive := 400;
- size_y : positive := 400
+ size_y : positive := 400;
+ palet_width : positive := 5;
+ palet_height : positive := 20
);
port (
- update : in std_logic;
- x_pos : in integer range 0 to 639;
- y_pos : in integer range 0 to 479;
+ x_pixel : in integer range 0 to 639;
+ y_pixel : in integer range 0 to 479;
ball_x : in integer range 0 to size_x - 1;
ball_y : in integer range 0 to size_y - 1;
-
+ palet_l : in integer range 0 to size_y - 1;
+ palet_r : in integer range 0 to size_y - 1;
color : out std_logic_vector (7 downto 0));
end draw;
architecture draw of draw is
type rom_type is array (0 to 3, 0 to 3) of integer range 0 to 3;
+
+ constant left_empty : natural := palet_width * 2;
+ constant up_empty : natural := 20;
+ constant ball_radius : natural := 3;
+ constant width_border : natural := 2;
+
+ signal current_x : integer;
+ signal current_y : integer;
+
signal px : integer;
signal py : integer;
- signal locx : integer range 0 to 3;
- signal locy : integer range 0 to 3;
signal tmpx : natural;
signal tmpy : natural;
- constant rom : rom_type :=
- ((1,3,0,0),
- (2,1,3,0),
- (0,2,1,3),
- (0,0,0,1));
+
+ signal in_ball : std_logic;
+ signal in_palet_l : std_logic;
+ signal in_palet_r : std_logic;
+ signal in_border : std_logic;
begin
+ current_x <= x_pixel - left_empty;
+ current_y <= y_pixel - up_empty;
+
px <= ball_x;
py <= ball_y;
- tmpx <= abs (x_pos - px);
- tmpy <= abs (y_pos - py);
+ tmpx <= abs (current_x - px);
+ tmpy <= abs (current_y - py);
-
- --locx <= tmpx when tmpx <= 3 else 3;
- --locy <= tmpy when tmpy <= 3 else 0;
+ in_ball <= '1' when (tmpx*tmpx + tmpy*tmpy <= ball_radius*ball_radius)
+ else '0';
- --with rom(locx,locy) select
- -- color <=
- -- "00000000" when 0,
- -- "11100000" when 1,
- -- "00011100" when 2,
- -- "00000011" when 3;
+ in_palet_l <= '1' when current_x <= 0
+ and current_x >= -palet_width
+ and abs ( current_y - palet_l ) <= palet_height / 2
+ else '0';
+ in_palet_r <= '1' when current_x >= size_x
+ and current_x <= size_x + palet_width
+ and abs ( current_y - palet_r ) <= palet_height / 2
+ else '0';
- color <= "11111111" when (tmpx <= 3) and (tmpy <= 3)
- else "00000000";
-
---update_process: process (update)
--- variable x : integer := 100;
--- variable y : integer := 100;
--- variable direction_x : std_logic := '1';
--- variable direction_y : std_logic := '1';
---begin
--- if rising_edge(update) then
--- if x >= 639 and direction_x = '1'
--- then
--- direction_x := '0';
--- end if;
--- if x <= 0 and direction_x = '0'
--- then
--- direction_x := '1';
--- end if;
--- if y >= 479 and direction_y = '1'
--- then
--- direction_y := '0';
--- end if;
--- if y <= 0 and direction_y = '0'
--- then
--- direction_y := '1';
--- end if;
-
--- if direction_x = '0' then
--- x := x - 1;
--- else
--- x := x + 1;
--- end if;
--- if direction_y = '0' then
--- y := y - 1;
--- else
--- y := y + 1;
--- end if;
+ in_border <= '1' when current_x >= 0 and current_x < size_x
+ and ( ( current_y <= 0 and current_y > -width_border )
+ or ( current_y > size_y and current_y < size_y + width_border ) )
+ else '0';
--- end if;
-
--- px <= x;
--- py <= y;
-
---end process update_process;
+ color <= "00111000" when in_ball = '1' or in_palet_l = '1' or in_palet_r = '1' or in_border = '1'
+ else "00000000";
end draw;
diff --git a/fpga/examples/pong/game.vhd b/fpga/examples/pong/game.vhd
index d3da725..1655583 100644
--- a/fpga/examples/pong/game.vhd
+++ b/fpga/examples/pong/game.vhd
@@ -6,73 +6,83 @@ use ieee.std_logic_arith.all;
entity game is
generic (
size_x : positive := 400;
- size_y : positive := 400);
+ size_y : positive := 400;
+ palet_width : positive := 5;
+ palet_height : positive := 20);
port (
clk : in std_logic;
- scan_code : in std_logic_vector ( 7 downto 0 );
- up_key : in std_logic;
- extended_key : in std_logic;
- key_int : in std_logic;
+ key_up_l : in std_logic;
+ key_down_l : in std_logic;
+ key_up_r : in std_logic;
+ key_down_r : in std_logic;
ball_x : out integer range 0 to size_x - 1;
ball_y : out integer range 0 to size_y - 1;
- keys : out std_logic_vector ( 3 downto 0 )
+ palet_l : out integer range 0 to size_y - 1;
+ palet_r : out integer range 0 to size_y - 1;
+ score_l : out integer range 0 to 255;
+ score_r : out integer range 0 to 255
+-- keys : out std_logic_vector ( 3 downto 0 )
);
end entity game;
architecture game of game is
+
+ constant init_x : integer := size_x / 2;
+ constant init_y : integer := size_y / 3;
+
signal game_clk : std_logic;
- signal key_up : std_logic;
- signal key_down : std_logic;
- signal key_left : std_logic;
- signal key_right : std_logic;
- signal px : integer;
- signal py : integer;
+ --signal key_up : std_logic;
+ --signal key_down : std_logic;
+ --signal key_left : std_logic;
+ --signal key_right : std_logic;
+ signal px : integer range 0 to size_x - 1;
+ signal py : integer range 0 to size_y - 1;
begin
- keys <= key_up & key_down & key_left & key_right;
+-- keys <= key_up & key_down & key_left & key_right;
ball_x <= px;
ball_y <= py;
- process (key_int)
- variable up : std_logic := '0';
- variable down : std_logic := '0';
- variable left_dir : std_logic := '0';
- variable right_dir : std_logic := '0';
- begin
- if rising_edge(key_int) then
- if (up_key = '0' and scan_code = "0111"&"0101" ) then
- up := '1';
- end if;
- if (up_key = '1' and scan_code = "0111"&"0101" ) then
- up := '0';
- end if;
- if (up_key = '0' and scan_code = "0111"&"0010" ) then
- down := '1';
- end if;
- if (up_key = '1' and scan_code = "0111"&"0010" ) then
- down := '0';
- end if;
- if (up_key = '0' and scan_code = "0111"&"0100" ) then
- right_dir := '1';
- end if;
- if (up_key = '1' and scan_code = "0111"&"0100" ) then
- right_dir := '0';
- end if;
- if (up_key = '0' and scan_code = "0110"&"1011" ) then
- left_dir := '1';
- end if;
- if (up_key = '1' and scan_code = "0110"&"1011" ) then
- left_dir := '0';
- end if;
- end if;
+ --process (key_int)
+ -- variable up : std_logic := '0';
+ -- variable down : std_logic := '0';
+ -- variable left_dir : std_logic := '0';
+ -- variable right_dir : std_logic := '0';
+ --begin
+ -- if rising_edge(key_int) then
+ -- if (up_key = '0' and scan_code = "0111"&"0101" ) then
+ -- up := '1';
+ -- end if;
+ -- if (up_key = '1' and scan_code = "0111"&"0101" ) then
+ -- up := '0';
+ -- end if;
+ -- if (up_key = '0' and scan_code = "0111"&"0010" ) then
+ -- down := '1';
+ -- end if;
+ -- if (up_key = '1' and scan_code = "0111"&"0010" ) then
+ -- down := '0';
+ -- end if;
+ -- if (up_key = '0' and scan_code = "0111"&"0100" ) then
+ -- right_dir := '1';
+ -- end if;
+ -- if (up_key = '1' and scan_code = "0111"&"0100" ) then
+ -- right_dir := '0';
+ -- end if;
+ -- if (up_key = '0' and scan_code = "0110"&"1011" ) then
+ -- left_dir := '1';
+ -- end if;
+ -- if (up_key = '1' and scan_code = "0110"&"1011" ) then
+ -- left_dir := '0';
+ -- end if;
+ -- end if;
- key_up <= up;
- key_down <= down;
- key_left <= left_dir;
- key_right <= right_dir;
+ -- key_up <= up;
+ -- key_down <= down;
+ -- key_left <= left_dir;
+ -- key_right <= right_dir;
- end process;
+ --end process;
process (clk)
@@ -91,29 +101,88 @@ begin
end process;
update_process: process (game_clk)
- variable x : integer := 100;
+ variable x : integer := 50;
variable y : integer := 100;
+ variable v_x : integer := 2;
+ variable v_y : integer := 2;
+ variable y_l : integer := 100;
+ variable y_r : integer := 100;
+ variable v_score_l : integer range 0 to 255 := 0;
+ variable v_score_r : integer range 0 to 255 := 0;
+
begin
if rising_edge(game_clk) then
- if key_up = '1' and y > 0 then
- y := y - 1;
+ -- begin bounce on palet
+ if x >= size_x-1
+ and v_x > 0
+ and abs ( y - y_r ) < palet_height
+ then
+ v_x := -v_x;
end if;
- if key_down = '1' and y < size_y then
- y := y + 1;
+ if x <= 0
+ and v_x < 0
+ and abs ( y - y_l ) < palet_height
+ then
+ v_x := -v_x;
end if;
- if key_left = '1' and x > 0 then
- x := x - 1;
+ -- end bounce on palet
+
+ -- begin bounce on up wall
+ if ( (y >= size_y-1 and v_y > 0)
+ or (y <= 0 and v_y < 0) )
+ then
+ v_y := -v_y;
end if;
- if key_right = '1' and x < size_x then
- x := x + 1;
+ -- end bounce on up wall
+
+ -- begin move ball
+ x := x + v_x;
+ y := y + v_y;
+ -- end move ball
+
+ -- begin loose
+ if x >= size_x + palet_width
+ then
+ v_score_l := 1 + v_score_l;
+ x := init_x;
+ y := init_y;
end if;
+ if x < 0 - palet_width
+ then
+ v_score_r := 1 + v_score_r;
+ x := init_x;
+ y := init_y;
+ end if;
+ -- end loose
+
+
+ -- begin move palet
+ if key_up_l = '1' and y_l > palet_height then
+ y_l := y_l - 1;
+ end if;
+ if key_down_l = '1' and y_l < size_y - palet_height then
+ y_l := y_l + 1;
+ end if;
+ if key_up_r = '1' and y_r > palet_height then
+ y_r := y_r - 1;
+ end if;
+ if key_down_r = '1' and y_r < size_y - palet_height then
+ y_r := y_r + 1;
+ end if;
+ -- end move palet
end if;
+ palet_l <= y_l;
+ palet_r <= y_r;
+
px <= x;
py <= y;
+ score_l <= v_score_l;
+ score_r <= v_score_r;
+
end process update_process;
diff --git a/fpga/examples/pong/pong.ucf b/fpga/examples/pong/pong.ucf
index 785eb95..e53079a 100644
--- a/fpga/examples/pong/pong.ucf
+++ b/fpga/examples/pong/pong.ucf
@@ -7,10 +7,10 @@
# NET "sw<6>" LOC= "N17";
# NET "sw<7>" LOC= "R17";
-# NET "btn<0>" LOC= "B18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN0
-# NET "btn<1>" LOC= "D18"; # Bank = 1 , Pin name = IP/VREF_1 , Type = VREF , Sch name = BTN1
-# NET "btn<2>" LOC= "E18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN2
-# NET "btn<3>" LOC= "H13"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN3
+NET "btn<0>" LOC= "B18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN0
+NET "btn<1>" LOC= "D18"; # Bank = 1 , Pin name = IP/VREF_1 , Type = VREF , Sch name = BTN1
+NET "btn<2>" LOC= "E18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN2
+NET "btn<3>" LOC= "H13"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN3
# Pin assignment for Leds
# Connected to Nexys 2
diff --git a/fpga/examples/pong/pong.vhd b/fpga/examples/pong/pong.vhd
index e41641e..dbe0db6 100644
--- a/fpga/examples/pong/pong.vhd
+++ b/fpga/examples/pong/pong.vhd
@@ -7,7 +7,7 @@ entity pong is
port (
clk : in std_logic;
--- btn : in std_logic_vector(3 downto 0);
+ btn : in std_logic_vector(3 downto 0);
Led : out std_logic_vector(7 downto 0);
-- usb : in std_logic;
-- sw : in std_logic_vector(7 downto 0);
@@ -30,14 +30,18 @@ architecture pong of pong is
component draw is
generic (
size_x : positive := 400;
- size_y : positive := 400
+ size_y : positive := 400;
+ palet_width : positive := 5;
+ palet_height : positive := 20
);
port (
- update : in std_logic;
- x_pos : in integer range 0 to 639;
- y_pos : in integer range 0 to 479;
+-- update : in std_logic;
+ x_pixel : in integer range 0 to 639;
+ y_pixel : in integer range 0 to 479;
ball_x : in integer range 0 to size_x - 1;
ball_y : in integer range 0 to size_y - 1;
+ palet_l : in integer range 0 to size_y - 1;
+ palet_r : in integer range 0 to size_y - 1;
color : out std_logic_vector (7 downto 0));
end component;
@@ -82,21 +86,29 @@ architecture pong of pong is
component game is
generic (
size_x : positive := 400;
- size_y : positive := 400);
+ size_y : positive := 400;
+ palet_width : positive := 5;
+ palet_height : positive := 20);
port (
clk : in std_logic;
- scan_code : in std_logic_vector ( 7 downto 0 );
- up_key : in std_logic;
- extended_key : in std_logic;
- key_int : in std_logic;
+ key_up_l : in std_logic;
+ key_down_l : in std_logic;
+ key_up_r : in std_logic;
+ key_down_r : in std_logic;
ball_x : out integer range 0 to size_x - 1;
ball_y : out integer range 0 to size_y - 1;
- keys : out std_logic_vector ( 3 downto 0 )
+ palet_l : out integer range 0 to size_y - 1;
+ palet_r : out integer range 0 to size_y - 1;
+ score_l : out integer range 0 to 255;
+ score_r : out integer range 0 to 255
+-- keys : out std_logic_vector ( 3 downto 0 )
);
end component;
constant size_x : integer := 400;
constant size_y : integer := 400;
+ constant palet_width : positive := 5;
+ constant palet_height : positive := 20;
signal vga_color : std_logic_vector ( 7 downto 0 );
signal internal_vsync : std_logic;
@@ -114,6 +126,11 @@ architecture pong of pong is
signal key_extended : std_logic;
signal key_int : std_logic;
+ signal key_up_l : std_logic;
+ signal key_down_l : std_logic;
+ signal key_up_r : std_logic;
+ signal key_down_r : std_logic;
+
signal slow_clk : std_logic;
signal value_7seg : std_logic_vector ( 15 downto 0 );
signal point_7seg : std_logic_vector ( 3 downto 0 );
@@ -121,42 +138,70 @@ architecture pong of pong is
-- game data
signal ball_x : integer range 0 to size_x - 1;
signal ball_y : integer range 0 to size_y - 1;
+
+ signal palet_l : integer range 0 to size_y - 1;
+ signal palet_r : integer range 0 to size_y - 1;
+
+ signal score_l : integer range 0 to 255 := 0;
+ signal score_r : integer range 0 to 255 := 0;
+ signal score_l_vector : std_logic_vector ( 7 downto 0 );
+ signal score_r_vector : std_logic_vector ( 7 downto 0 );
+
begin
vsync <= internal_vsync;
- vga_out <= vga_color;
-
+ vga_out <= vga_color when active_output = '1' else "00000000";
+
+ score_l_vector <= (conv_std_logic_vector(score_l,8));
+ score_r_vector <= (conv_std_logic_vector(score_r,8));
+ value_7seg <= (score_l_vector(3 downto 0)) & (score_l_vector(7 downto 4))
+ & (score_r_vector(3 downto 0)) & (score_r_vector(7 downto 4));
+ key_up_l <= btn(0);
+ key_down_l <= btn(1);
+ key_up_r <= btn(2);
+ key_down_r <= btn(3);
+
draw_1 : draw
generic map
(
size_x,
- size_y
+ size_y,
+ palet_width,
+ palet_height
)
port map
- ( internal_vsync,
+ ( -- internal_vsync,
vga_x,
vga_y,
ball_x,
ball_y,
+ palet_l,
+ palet_r,
vga_color
);
game_1 : game
generic map (
size_x,
- size_y)
+ size_y,
+ palet_width,
+ palet_height)
port map (
clk,
- scan_code,
- key_up,
- key_extended,
- key_int,
+ key_up_l,
+ key_down_l,
+ key_up_r,
+ key_down_r,
ball_x,
ball_y,
- led ( 3 downto 0 )
+ palet_l,
+ palet_r,
+ score_l,
+ score_r
+-- led ( 3 downto 0 )
);
- led ( 7 downto 4 ) <= "0000";
+ led ( 7 downto 0 ) <= "00000000";
vga_1 : vga port map
( clk,
@@ -195,7 +240,6 @@ begin
an
);
-
process (clk)
variable count : integer range 0 to 65535 := 0;
variable tmp_std : std_logic_vector ( 15 downto 0 );
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2010-01-25 23:12:32
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 1e545ef9f7ae38acea030fec3f15b1c1a9fb5e58 (commit)
from 32e007d2e96e6c74fb68e0e935756940639e23e9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1e545ef9f7ae38acea030fec3f15b1c1a9fb5e58
Author: chambart <cha...@cr...>
Date: Tue Jan 26 00:11:47 2010 +0100
add a begining of a pong game example
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/examples/pong/Makefile b/fpga/examples/pong/Makefile
new file mode 100644
index 0000000..73a6756
--- /dev/null
+++ b/fpga/examples/pong/Makefile
@@ -0,0 +1,35 @@
+PART=xc3s1200e-fg320-5
+
+XST=xst
+NGDBUILD=ngdbuild
+PAR=par
+BITGEN=bitgen
+MAP=map
+
+FILE=truc2
+UCF=pong.ucf
+
+.PHONY: all clean
+all: out.bit
+
+%.ngc : %.vhd
+ echo "run -ifn " $< " -p " $(PART) " -ofn " $@ " -opt_mode AREA -opt_level 0 -ifmt VHDL" | $(XST)
+
+pong.ngc : vga.ngc keyboard.ngc ps2.ngc draw.ngc simple_7seg.ngc game.ngc
+
+pong.ngd : pong.ngc
+ $(NGDBUILD) -p $(PART) -uc $(UCF) $<
+
+tmp.ncd : pong.ngd
+ $(MAP) -p $(PART) -o $@ $<
+
+out.ncd : tmp.ncd
+ $(PAR) -w $< $@
+
+out.bit: out.ncd
+ $(BITGEN) -w out.ncd
+
+clean:
+ rm -fr *.ncd *.ngc *.ngd *.bit *.pcf *.map *.mrp \
+ *.lso *.xml *.xrpt *.bgn *.drc *.bld *.ngm *.lst \
+ xst out* *.log *.twr xlnx_auto*
diff --git a/fpga/examples/pong/draw.vhd b/fpga/examples/pong/draw.vhd
new file mode 100644
index 0000000..57fe679
--- /dev/null
+++ b/fpga/examples/pong/draw.vhd
@@ -0,0 +1,99 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity draw is
+ generic (
+ size_x : positive := 400;
+ size_y : positive := 400
+ );
+ port (
+ update : in std_logic;
+ x_pos : in integer range 0 to 639;
+ y_pos : in integer range 0 to 479;
+ ball_x : in integer range 0 to size_x - 1;
+ ball_y : in integer range 0 to size_y - 1;
+
+ color : out std_logic_vector (7 downto 0));
+
+end draw;
+
+architecture draw of draw is
+ type rom_type is array (0 to 3, 0 to 3) of integer range 0 to 3;
+ signal px : integer;
+ signal py : integer;
+ signal locx : integer range 0 to 3;
+ signal locy : integer range 0 to 3;
+ signal tmpx : natural;
+ signal tmpy : natural;
+ constant rom : rom_type :=
+ ((1,3,0,0),
+ (2,1,3,0),
+ (0,2,1,3),
+ (0,0,0,1));
+begin
+
+ px <= ball_x;
+ py <= ball_y;
+
+ tmpx <= abs (x_pos - px);
+ tmpy <= abs (y_pos - py);
+
+
+ --locx <= tmpx when tmpx <= 3 else 3;
+ --locy <= tmpy when tmpy <= 3 else 0;
+
+ --with rom(locx,locy) select
+ -- color <=
+ -- "00000000" when 0,
+ -- "11100000" when 1,
+ -- "00011100" when 2,
+ -- "00000011" when 3;
+
+ color <= "11111111" when (tmpx <= 3) and (tmpy <= 3)
+ else "00000000";
+
+--update_process: process (update)
+-- variable x : integer := 100;
+-- variable y : integer := 100;
+-- variable direction_x : std_logic := '1';
+-- variable direction_y : std_logic := '1';
+--begin
+-- if rising_edge(update) then
+-- if x >= 639 and direction_x = '1'
+-- then
+-- direction_x := '0';
+-- end if;
+-- if x <= 0 and direction_x = '0'
+-- then
+-- direction_x := '1';
+-- end if;
+-- if y >= 479 and direction_y = '1'
+-- then
+-- direction_y := '0';
+-- end if;
+-- if y <= 0 and direction_y = '0'
+-- then
+-- direction_y := '1';
+-- end if;
+
+-- if direction_x = '0' then
+-- x := x - 1;
+-- else
+-- x := x + 1;
+-- end if;
+-- if direction_y = '0' then
+-- y := y - 1;
+-- else
+-- y := y + 1;
+-- end if;
+
+-- end if;
+
+-- px <= x;
+-- py <= y;
+
+--end process update_process;
+
+end draw;
diff --git a/fpga/examples/pong/game.vhd b/fpga/examples/pong/game.vhd
new file mode 100644
index 0000000..d3da725
--- /dev/null
+++ b/fpga/examples/pong/game.vhd
@@ -0,0 +1,120 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity game is
+ generic (
+ size_x : positive := 400;
+ size_y : positive := 400);
+ port (
+ clk : in std_logic;
+ scan_code : in std_logic_vector ( 7 downto 0 );
+ up_key : in std_logic;
+ extended_key : in std_logic;
+ key_int : in std_logic;
+ ball_x : out integer range 0 to size_x - 1;
+ ball_y : out integer range 0 to size_y - 1;
+ keys : out std_logic_vector ( 3 downto 0 )
+ );
+end entity game;
+
+architecture game of game is
+ signal game_clk : std_logic;
+ signal key_up : std_logic;
+ signal key_down : std_logic;
+ signal key_left : std_logic;
+ signal key_right : std_logic;
+ signal px : integer;
+ signal py : integer;
+begin
+
+ keys <= key_up & key_down & key_left & key_right;
+
+ ball_x <= px;
+ ball_y <= py;
+
+ process (key_int)
+ variable up : std_logic := '0';
+ variable down : std_logic := '0';
+ variable left_dir : std_logic := '0';
+ variable right_dir : std_logic := '0';
+ begin
+ if rising_edge(key_int) then
+ if (up_key = '0' and scan_code = "0111"&"0101" ) then
+ up := '1';
+ end if;
+ if (up_key = '1' and scan_code = "0111"&"0101" ) then
+ up := '0';
+ end if;
+ if (up_key = '0' and scan_code = "0111"&"0010" ) then
+ down := '1';
+ end if;
+ if (up_key = '1' and scan_code = "0111"&"0010" ) then
+ down := '0';
+ end if;
+ if (up_key = '0' and scan_code = "0111"&"0100" ) then
+ right_dir := '1';
+ end if;
+ if (up_key = '1' and scan_code = "0111"&"0100" ) then
+ right_dir := '0';
+ end if;
+ if (up_key = '0' and scan_code = "0110"&"1011" ) then
+ left_dir := '1';
+ end if;
+ if (up_key = '1' and scan_code = "0110"&"1011" ) then
+ left_dir := '0';
+ end if;
+ end if;
+
+ key_up <= up;
+ key_down <= down;
+ key_left <= left_dir;
+ key_right <= right_dir;
+
+ end process;
+
+
+ process (clk)
+ constant length : integer := 1_000_000;
+ variable counter : integer range 0 to length:= 0;
+ variable tmp : std_logic := '0';
+ begin
+ if rising_edge(clk) then
+ counter := counter + 1;
+ if counter = length / 2 then
+ tmp := not tmp;
+ counter := 0;
+ end if;
+ end if;
+ game_clk <= tmp;
+ end process;
+
+ update_process: process (game_clk)
+ variable x : integer := 100;
+ variable y : integer := 100;
+ begin
+ if rising_edge(game_clk) then
+
+ if key_up = '1' and y > 0 then
+ y := y - 1;
+ end if;
+ if key_down = '1' and y < size_y then
+ y := y + 1;
+ end if;
+ if key_left = '1' and x > 0 then
+ x := x - 1;
+ end if;
+ if key_right = '1' and x < size_x then
+ x := x + 1;
+ end if;
+
+ end if;
+
+ px <= x;
+ py <= y;
+
+ end process update_process;
+
+
+end architecture;
diff --git a/fpga/examples/pong/keyboard.vhd b/fpga/examples/pong/keyboard.vhd
new file mode 100644
index 0000000..88a8882
--- /dev/null
+++ b/fpga/examples/pong/keyboard.vhd
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity keyboard is
+ port (clk : in std_logic;
+ data_in : in std_logic_vector ( 0 to 7 );
+ int_in : in std_logic;
+
+ extended : out std_logic;
+ up : out std_logic;
+ code : out std_logic_vector ( 0 to 7 );
+ int : out std_logic );
+end entity keyboard;
+
+architecture keyboard of keyboard is
+ type state_type is ( waiting, end_state );
+ signal tmp_extended, tmp_up : std_logic;
+begin
+
+process (clk)
+ variable state : state_type := end_state;
+ variable old_int_in : std_logic := '0';
+begin
+ if(rising_edge(clk))
+ then
+ case state is
+ when end_state =>
+ state := waiting;
+ int <= '0';
+ tmp_extended <= '0';
+ tmp_up <= '0';
+ when waiting =>
+ if(int_in = '1' and old_int_in = '0')
+ then
+ case data_in is
+ when "11100000" =>
+ tmp_extended <= '1';
+ state := waiting;
+ when "11110000" =>
+ tmp_up <= '1';
+ state := waiting;
+ when others =>
+ code <= data_in;
+ extended <= tmp_extended;
+ up <= tmp_up;
+ state := end_state;
+ int <= '1';
+ end case;
+ end if;
+ end case;
+
+ old_int_in := int_in;
+ end if;
+end process;
+
+end keyboard;
diff --git a/fpga/examples/pong/nexys2prog b/fpga/examples/pong/nexys2prog
new file mode 100755
index 0000000..89eb742
--- /dev/null
+++ b/fpga/examples/pong/nexys2prog
@@ -0,0 +1,345 @@
+#!/usr/bin/perl -w
+# Copyright 2009, Andrew Ross <an...@pl...>
+# Distributable under the terms of the GNU GPL licence version 2 or later.
+use strict;
+use POSIX qw(isatty);
+use Time::HiRes qw(usleep);
+
+# nexys2prog - program a Digilent Nexys 2 FPGA board over USB
+#
+# Usage: nexys2prog [-v|--verbose] <Bitstream File>
+#
+# This script automatically finds an attached Nexys 2 board and loads
+# it with the specified Xilinx bitstream with a minimum of fuss,
+# configuration, and external dependencies. Specifically, the
+# hacked/patched firmware for the Cypress FX2 chip is stored inline.
+# The user only needs user-level software installed and a single local
+# configuration change (optional, for the USB device files -- the lazy
+# can just run the script as root).
+#
+# Prerequisites:
+#
+# 1. A working Xilinx ISE installation. This was tested against 10.1,
+# but I believe older versions share the same iMPACT syntax and
+# BSDL file locations.
+#
+# 2. The "fxload" utility is required to reprogram the board's FX2 USB
+# chip, available in Debian and Ubuntu via "apt-get install
+# fxload". Note that fxload requires write access to the raw USB
+# device files under /dev/bus/usb, and that these are by default
+# read-only on Ubuntu Intrepid. You can either run the script as
+# root, or else set the files to be owned by the "plugdev" group by
+# adding the GROUP field to this line in
+# /etc/udev/rules.d/40-basic-permissions.rules:
+# SUBSYSTEM=="usb", ENV{DEVTYPE}=="usb_device", MODE="0664", GROUP="plugdev"
+#
+# 3. UrJTAG, available from http://urjtag.org. UrJTAG is an active
+# fork of the moribund openwince-jtag project. Note that
+# openwince-jtag is still an available Debian/Ubuntu package, that
+# it shares the same "jtag" binary name and most of its syntax, and
+# that IT DOES NOT WORK with the firmware in this script. You need
+# to install UrJTAG. Also note that you will need libftdi
+# installed for the protocol handler, again available on
+# Debian/Ubuntu via "apt-get install libftdi1". UrJTAG will build
+# without this, but you won't be able to program the Nexys 2
+# without libftdi.
+#
+# Note that this script contains a binary firmware blob built from
+# free software sources. See the note above it for source
+# information.
+
+
+# TODO:
+# + Figure out the JTAG interface for the boot PROM, so it can be
+# flashed with the bitstream instead of (or in addition to) doing a
+# direct load to the FPGA.
+# + Pull down and parse the JTAG chain from the device to verify that
+# it's actually a Nexys 2 and not another device sharing the same
+# firmware family and bus ID. Kolja's firmware runs on other
+# devices too...
+# + Extend the script to recognize arbitrary JTAG chains and find the
+# appropriate part number automatically. So you'd just specify a
+# .bit file (which contains the FPGA type) and it would crawl the
+# JTAG bus looking for a matching FPGA to program.
+
+my $USBID_KOLJA = "16c0:06ad";
+my $USBID_DIGILENT = "1443:0005";
+my $XILINX;
+my $TMPID = sprintf("/tmp/nexys2prog-%8.8X-%4.4X", time(), $$);
+
+my $verbose = 0;
+my $filebase;
+my $bit;
+
+# Parse the command line
+while(@ARGV) {
+ my $arg = shift;
+ if($arg eq "-v" or $arg eq "--verbose") { $verbose = 1; }
+ elsif(!defined $bit and -f $arg and -R $arg) {
+ $bit = $arg;
+ $filebase = $bit;
+ $filebase =~ s/\.bit$//i;
+ } else { usage(); }
+}
+usage() if !defined $bit;
+
+# Find the tools
+check_tools();
+find_xilinx();
+
+# If needed, convert the .bit file to .svf using Xilinx's iMPACT tool.
+update_svf();
+
+# Locate and configure the board's USB interface
+find_board();
+
+# Do it
+play_svf();
+
+########################################################################
+
+sub usage { die "Usage:\n $0 [-v|--verbose] <Bitstream File>\n"; }
+sub vlog { print join("", @_) if $verbose; }
+
+# Idiot-proofing, to help mitigate the Rube Goldbergisms inherent in
+# this process.
+sub check_tools {
+ system("which impact >/dev/null") == 0 or die
+ ("Cannot find iMPACT executable. The Xilinx ISE development kit\n".
+ "must be installed and its settings32.sh script sourced in the\n".
+ "current shell.\n");
+ system("which jtag >/dev/null") == 0 or die
+ ("Cannot find jtag executable. The UrJTAG tools (http://urjtag.org)\n".
+ "must be built, installed, and on the PATH. You will also need to\n".
+ "install libftdi as a prerequisite: \"apt-get install libftdi-dev\" if\n".
+ "needed.\n");
+ system("jtag --version | grep UrJTAG >/dev/null") == 0 or die
+ ("Installed jtag executable is the wrong version. You probably have the\n".
+ "openwince-jtag tools installed. The Nexys2 loader requires UrJTAG\n".
+ "(http://urjtag.org) instead, which is a fork that, sadly, shares the\n".
+ "same command names. Uninstall the existing software, or (carefully!)\n".
+ "install UrJTAG such that it lives before the old tool on your PATH.\n");
+}
+
+sub find_board {
+ my $nx = find_nexys2();
+ die "Cannot find a Nexys 2 board on the USB bus. Plug it in?\n"
+ if(!defined $nx);
+ my ($bus, $dev, $id) = @$nx;
+ if($id ne $USBID_KOLJA) {
+ $dev = blasterize($bus, $dev);
+ } else {
+ vlog("Found already-configured board on bus $bus dev $dev\n");
+ }
+}
+
+sub update_svf {
+ my $svf = "$filebase.svf";
+ if((!-f $svf) or (stat($svf))[9] <= (stat($bit))[9]) {
+ vlog("Generating SVF file...\n");
+ my $impactrc = "$TMPID.impact";
+ open RC, ">$impactrc" or die "can't write to $TMPID.impact";
+ print RC "setMode -bs\n";
+ print RC "setCable -port svf -file $svf\n";
+ print RC "addDevice -p 1 -file $XILINX/xcf/data/xcf04s.bsd\n";
+ print RC "addDevice -p 2 -file $bit\n";
+ print RC "program -p 2\n";
+ print RC "closeCable\n";
+ print RC "quit\n";
+ close RC;
+ if($verbose) { system("sed 's/^/ /' $impactrc"); }
+ run("impact -batch $impactrc");
+ die "iMPACT failed to generate $svf" if ! -f $svf;
+ } else {
+ vlog("$svf is current, not regenerating.\n");
+ }
+}
+
+sub find_xilinx {
+ my $ise = `which impact`;
+ $ise = qx(cd `dirname $ise`; /bin/pwd);
+ chomp $ise;
+ die "Cannot find Xilinx ISE installation directory.\n"
+ if $ise !~ /ISE\/bin\/lin$/;
+ $ise =~ s/\/bin\/lin$//;
+ die "Cannot understand Xilinx ISE installation tree.\n"
+ if !-d "$ise/spartan3e/data" or !-f "$ise/xcf/data/xcf04s.bsd";
+ $XILINX = $ise;
+ vlog("Located Xilinx ISE installation in $XILINX.\n");
+}
+
+# Run an external tool, emitting the output only if it fails. iMPACT
+# and UrJTAG are annoyingly verbose...
+sub run {
+ my $cmd = shift;
+ print($cmd, "\n") if $verbose;
+ open CMD, "$cmd 2>&1|" or die;
+ # FIXME: if the subprocess crashes (as jtag does without a cable),
+ # we get incomplete output...
+ my $out = join "", <CMD>;
+ close CMD;
+ die "Command failure:\n $cmd\n\n$out" if $?;
+}
+
+sub find_nexys2 {
+ my ($bus, $dev, $id);
+ open LSUSB, "lsusb|" or die "Cannot run lsusb";
+ while(<LSUSB>) {
+ next if ! /Bus (\d+) Device (\d+): ID ([0-9a-f]{4}:[0-9a-f]{4})/;
+ next if !($3 eq $USBID_DIGILENT or $3 eq $USBID_KOLJA);
+ ($bus, $dev, $id) = ($1, $2, $3);
+ }
+ close LSUSB;
+ if(defined $bus) {
+ vlog("Found USB device $id on bus $bus device $dev\n");
+ return [$bus, $dev, $id];
+ }
+ return undef;
+}
+
+# Reprogram a connected FX2 device with Kolja Waschk's usb_jtag
+# firmware, patched to support the Nexys 2 pin assignments and FPGA
+# bitstream sizes as per Morgan Delahaye's instructions at
+# http://m-del.net/info.html. Uses the fxload tool from the
+# linux-hotplug project. The end result is an interface compatible
+# with the FTDI-based Altera USBBlaster product.
+sub blasterize {
+ my ($bus, $dev) = @_;
+ my $usbfile = "/dev/bus/usb/$bus/$dev";
+ if(!-w $usbfile) {
+ die ("Cannot write to $usbfile.\n\n" .
+ "Either run this tool as root or modify your udev settings to\n" .
+ "allow write access to USB device files.\n");
+ }
+ my $firmware = gen_fx2();
+ vlog("Loading 8051 firmware into board...\n");
+ run("/sbin/fxload -t fx2 -D $usbfile -I $firmware");
+ my $nx;
+ # Wait for it to reboot, renumerate and appear on the bus.
+ for(my $i=0; $i<20; $i++) {
+ usleep 10000;
+ last if defined($nx = find_nexys2()) and $nx->[2] eq $USBID_KOLJA;
+ }
+ if(!defined $nx or $nx->[2] ne $USBID_KOLJA) {
+ die ("Reprogrammed FX2 device not found on USB bus.\n",
+ "fxload failure? device unplugged? ... !?\n");
+ }
+ return $nx->[1];
+}
+
+sub play_svf {
+ open JTAG, ">$TMPID.jtag" or die "cannot write to $TMPID.jtag";
+ # Just the BSDL directories needed for the 2 chips on the Nexys2...
+ print JTAG "bsdl path $XILINX/spartan3e/data;$XILINX/xcf/data\n";
+ print JTAG "cable usbblaster\n";
+ print JTAG "detect\n";
+ print JTAG "part 1\n";
+ print JTAG "svf $filebase.svf\n";
+ print JTAG "quit\n";
+ close JTAG;
+ run("jtag $TMPID.jtag");
+}
+
+
+# Firmware for the FX2 chip
+# Original source (GPLv2) -- http://www.ixo.de/info/usb_jtag
+# Modifications:
+# hw_nexys.c -- http://www.m-del.net/files/nexys/hw_nexys2.c
+# bit_fpga.patch -- http://www.m-del.net/files/nexys/big_fpga.patch
+# It was built with the sdcc-nf ("non-free") compiler from Ubuntu 8.10
+# multiverse, and the resulting Intel hex file was filtered through
+# bzip2 and then base64 to produce the string below.
+sub gen_fx2 {
+ my $filename = "$TMPID.fx2";
+ vlog("Unpacking FX2 firmware to $filename\n");
+ open FX2, "|base64 -d | bzip2 -d > $filename"
+ or die "cannot write to $filename";
+ print FX2 <<__EOF__
+QlpoOTFBWSZTWf0aqD8AEcBMAHgQf/A/AGAXntpC7s763WvY+8vm9nz3qlzNDNk233a769fb5976
+Ou+tbH3O7fbp9vd77h9775nr7u9eN7vp3t699fdet77uXr59977K+3u5L217WhqniZGAqkANNRgE
+JKhphqegamgmqQA0xEATUlRgZqRkTTRpKTIJEQAJKmhpbwNpo/yUJ9/267v2VMV/cR/ynknP0f3R
+1fdtf5u/wbXhJJJJDrXInDOUu+63nN/y1aap/T7i8g38pZ56fMwVuRkDzKfmr3MZ8nM7J6TCCE9i
+VYLTR8Wdru4+GXyteWPVvW177DMK7nSv3kxnPnqFzCbViSSSSSzyNNr5T6fiw7OdVYmK3Y9PYdc1
+qTywpRBCfZWHS01+5ReZrllLmH5r4ZtiqRcd9Whl0PcW44EXnaipK8gF1+U9s9mft0jhZRPa/r3a
+Wi4V9F2Ztjc6qN7Z9Yyi6Sx3rTyBqhIHemLlT7ms7h/Y+Jp3Hrgx90AIlZunfkTdV6e497oAIjEA
+IhGzN2rkgkkkkkkkgp/vL3OLUz3eQM+Dhx/krG+H4U393qm2tgAAA/d13GPc4NQqq9lpew2MIBCb
+7w8mvrZxazzDx5sETd+2gCUU7T853RnkTuOZPAzkU2CbJTVLR9GswM4/D4hud+dFzan62e6scyX4
+z7SA0TYN3IlIKKjVp9L1c6tzvOW7prOlhXhICYgVAa8IYaQVxJiYeU3Aq12XMeIO5h7OumDBCumz
+mN6YeGcKkCtIBBup3lhspb30rzWBst1Cgbf64MB17zduoiGgmNJmfN3c45WUKkVkvWMXUtdoLjbc
+VZzqIgJREgSM93h0Pe08VGXt+3k7jFOT2ppwECn8x+OtMYoU9jGRnkJ9YjWZN30RIgKZ2IY6RE97
+J8wAUgeOybvbTe/jAWG4R2dEZdXKzvueVe+dmLZqQfqHCH5D1C7A2eQqY8K95S3WStt3lsKQMGo4
+m95VZb5Q+YgM7jiVizSiVN3xSrczoXp17TQDCNXSAUtltBrKpjyTkEWvZ7rrqFGG+l2ddNRjy+Kg
+c+rgfO7qq7i136n0jREaMHW+Jb6p3bcxg/qRKjbIURkS+Na1ZUYJjk2sC+BCSgT9EkoF3KgHYaKB
+uEoQMA9UQj76PG7+fdSPzFla1rcNypbdI5l/qURPsI5iqRPih8R5ggt+3s1f1SnMmSCXDPzvmEf6
+MK2aDy/RBMBpDBjHEdiLRBTsIVtlVo+zaAbbEj6Hj53syoraj2zhcz4fakkqcm8qMLy8PLdfFQE5
+z+ihARTNZEpqlnzxxJQJI6URx85FOxhhhlWH7zCO+jYFYiYvSsisxjZLSqeoj1aywbQjLRLJaPYn
+GaSWpA7xG68qfM3w50XGI/7Y+eYWFfW28tqDTbkpXJoXX56nSrQ4w3Q5+koxAw0UsgFRvG6pB6fi
+9/VcDS37Bwl2AtKfpFBrnJYqagMwYMAgxEqIBO1SXx9yhz3zoiPKjjxkChtgpGomqMTQQD9TgmSG
+pf5o/vUJFH6SbliTF+t/XatiqujGKrlX8Ih6Q4FtDSWh3V9FdWZ7C7yXTnbMkbfLUF7fXYeS9eIg
+BtBEHvo8zP52aoaSgSCEQAdZCJ5qMQT+25mM+Toa6mFQrmTiicpuD6ZqFJ2QNaz5pLQJnxkiLphS
+A7IQD84e772VsdanRCBtG6wmTChh6YEXZT6YX2kyEn6SWSQFOFfKbyP2GWPfihRw9amBc5IXPzA0
+BvLriF5mYkflbklFndW+8k8bpRVBhqCySgTFihFohQLIk1DBIHiLDswYmmGohoaIwfuU+QQV79xT
+gD9b7EUCXqxmXlAUs0lITLTfXP0mEYEMGAPiAF+14OCea65Ozr71jIvHF5KYhtyEhGcoANoViLve
+G+dgqx5+cO/37EMwL5QFm/F1+X1aOp8L5atOeyHSpIWGfOtV2TDGs2hJFaZ7o/YpX2PxIEv8zIht
+JfhgVaUni0FHWYI9v1NDS7fueOf1s8otpcRrPSmOuutROBX2s2+Qkpr5r4B0hQLCwX4VDCOz2eAs
+5OHdzHTf8OY66+Q2/15s0EcuZyxdP6BHTEXyUjAEDw4iYh1g2vNkrghAQ4dcjSIF4jY1CEzEAMQg
+AABgwbBMG0DY0JIQ2gbTAWOuESxXZmPqIJ+xKt8eSmjnV/PEFSTVW2Wez4feG7LH7cYdMQGYAMBE
+EjxhG8NeGCmmhchtQMwZAnMeVZW+uu81uejk+WxNBZK5Cp00k1j10sO+59XLIFzuLfdvBuBcITyP
+iPp48eL4/hebHmiGg2404Ms+GrMKXRC4KAnM3aBZm1VfvWNyd2S4dIQ2OQ6cI20FGv0DI8zEUn0e
+kONEHN1NVisamGbkaf2+fYu/xWngcfKRiTA21GgMZdppvdsS85l4MNWWUNvucx897/JFnhHCryzi
+vz2NeryUExJCPqQcAE4so1OGB8wEO9WcK8TrdvytwnQzA1lVX05kxcH1YaGdDG98JwjknVOdQqGT
+5zeUugHG1XQhIZLCUReUYE8dGyznDBQ4HTtPpB0A6IRiH+NobDyoyvCnZfVvIm/bwj4m+v4n7vf1
+rL9hBCDs71X9/cgfAXMGZfn6/c8xtdcqF0rMheEHcKAVDcCuKDAoTZaIcCUNiG0hgMaTQDB/yH8L
+7X7uf5lRP5S8SNjTSYm3PsUCjUmIO8ihu2HR7lwNnTuXYhAiJNyxSjRWFLJKsQVlgJ2e6jLRZYGD
+hoLAbfyGyOAgJNctDwjAoimoKPOKRI8fZC4bBkkWPOUKgTnstmlMiV8+G9rFNhpH5QTsxkgRogUc
+Y3IkMBIZRbgMNFroLPdWd7pkFpwbGfsZEm8IWi8vGKoSUhef5lpKpSuIBsGhJWi0sWKKXZEBmLGF
+FZRX8wzj5fjHGhgKIhAYMWe9XJLsIcCUe9ijxiHFyidFCe+ZqHKQm2I1EbKgjSe3+ijfjbrmM8/t
+DB336846DZ/FO8gwwtMEtF82rrmPXt737vDowyyEMbS+KMQAMAPLirG2pVsalmxU6TzNENkMxery
+FLUnMEDbRl8rRSEj3adWtAzDJ99IZy0kDJ5Sn1JWa1MQ17qEBU3pUG1IAMAheaxGJdZGGFCQQi1Y
+QkeupiOhMXpOdqBeCMa43mqIgEx7Kh2dEAYogJC4tZJV9HLTbDe6UUVPslJzyu85NXtKXu3977I+
+gMb16p/wPr13DtHHbtB6n8tj2Nrnw1++sAmQaFUeQDg0FpJJba81A7uKwX+ICgN0YavesukaigUI
+0EbchvNnj1uV169fuRt1zahQ6kogORpQnNMM7+GMBZJLWPx76aeJfdb/41g7tymkoHSMyUJsG7E+
+iEoH4zBZ4GkwkmQ5VqZc3eEsxSYEaYE2I+3zfFXIog/Yyp8wquVOGVFGQ4w2msATbjMR9mdFUnVX
+UYJwwCKwvngQzsBkCARhBlWmLogRYG+vN1NHpeRG6qF7DGJ569u8PE/nZ4m78sN679a+989vWuPK
+0rSyAKMDvEdBIgmCQJLaFinxiNEAmJmwynbGXdDX/mO2xj4qoy2lH4ztBGPRZEqQZ3zlZrqKPQSD
+MW6m1hqpwW7yi+6LCf2rKvCqSBBbf4TpcUfV56gU/Ocr0SSiGEjkEJw2KGwExnzFLEqFXO6bt6Cx
+NJC+cT8oplJaTF5ZGVl06MkMhqEsLshgGNESG+y2ZRrjuCXcve8LtJA0R3nocvVDENmqu34QuVZF
+xIOnCNq4HsrPujhn6KkT0+tHM7muc2vv7XKnORAxYYbQ09clI7SzJSzenaFRsKxAUxNvbnrMPzjc
+LLWUnv9Wf319eRVjaDThlN9r7lkXReIqzV5l0FCghEQ4E2BacTDCjGrT+2wKqWECvZjH1H5g0DTG
+05aENDY2kCSEK9/rrRP1rddD+Bt2z99CBMkT1DLrcoj6cf251WO/rPu/FtPi+rDAx/dyJ4fu/cv0
+9aGCzpP9BRHIAJvV732kQxVtTN4qu1CBH51qjHMSzjZIw0hiScH4iuW462eMTAJwalemimCWdja+
+FVVDdnSgffzo9PfXm8uV6pE6rq54WE0tc49dimQRnCCrbpqIj7+74zH4if04kZ/KGkh+BR3G66+j
+NU32CCXbMzDWfRpgdBiwPPJDqnZsYInmzmo33TgWMRJAMRpq4Pqcr4HvjKqjE9T29dm7GFXoOa7V
+Mt85WbKDSLpfNEopHTcuE4BMc8xezkxo01UPorZFEDCGSPnZoOzV8dPozIRTLicNKiYwaJYnRTJh
+SDFURSmRSqprzwdFxc7RKKKQgExoaBRNSVTroSsUhSIY6C/MgTByxUmDz1gh91bFAIGCIlRAwCAx
+TWvymcVJ5i1s1adLW0zagrHF/ix0yYwLGxYv+UOC6Q6ggPmq0gFP5gMxoR8v3PVswKjeFJvSA68r
+vKwDgkwCP1txkEX5/zCRwIeHkU6aO71z0MijwI6mZT88722nnM+pTWZVi68XkU8NRDzRl4tb0H2M
+v6hyaFfvcpejbo0dpHmQ0fxhL0y1tyBhtrfUN2MDb0J/hLf6Pht+kjpaI/Z35jIqR54a4wLMn0d1
+Aq0gNMPzozqu2EW977deJtl/85EuU2DRFoiPbk4znSEuWL613uNVgIFTP+XAcaQhZza7187+Vzq9
+HijadUThfm4urKlDGjPzEXajiUAW01aXw42sHE/SB2htZoXn3sRPmUX/iBIXM8zN/Yzz8fsUz8/1
+fY/Fu6qZiTovp4/n8TQHT7KReIn5KpLMWleba1Fs6AyBMebQxhpv0Q0pGRENhhkNJU8O9vXG1JDu
+ejvVY2ZtnVgE0CQoUTCFYDFnKGRC6tTdm3ODbcTBHYZ3xkEztxad1AT3nw5KpsWYyhbV8XtzKt5R
+scN4nD4CEIMKw6e628K/jA4XnlrhQeSBe6vWFJBFkpB7n0zylynVpGDTsvVHbG/j3qpuN2JQt1WI
+LIdJR8ElRJVD03iAadNIHUqUaRIThfDEBgPw/oFTBp01riMyJVbdauH3jVW0/L2iIPclq+iECDt4
+NYd/W42kkLrVYrdlvs+4d7PAPuKGGUaORWTozloMVeZpm8lDFokfncjJ9zDR4sMYNnWuLCkFHAKv
+iuQCUi2AASAFhKB1Z3m+hnmeyFWBX3mqFRUrkA7lm8GBDEEkBYyWzSFGhToItqH7UMCGLwC/28Gn
+3EjNxAQxZaw5ZSuQIOPJ4toLRi+YqFCuoAgB5fEuUhSIVZi/bBvVW2xSFmFpWtUG9b3bbT4Dzr8m
+ilLuPN7y11QbKLtz3HHaVKpFF3Eajv1OAnKiE/AICeD4CBKjAHIjgXJFMAz6T77PeUd53rdsLQkg
+ICNWOgRwWgQ0l0hWibRuc+S+Mny8fizYnd7jrW5c7hv5iQeXtE/TkrqD7tVU9nDq3E616cwSJDXy
+oCxLGml8nt1QFGiEo5EcZho2t39696217ud1VLPZfj4HaAAQcPIczUyI50yQKp2Q3l9Ez3l15qYb
+u+CTMFtUVTB3qd1TRnE3WN8z8aDjGVUhsyM7mkRHbFvqDjrnmXudJHsiEQNAwzyNBCIwRZhX6LKo
+kgQLIHCyVdcOYiDJD2EFPzu95kc4h26FnHzuMy77gV/iH8bk25soWnVlNRl2Yvd9KXcbnFJTdDU4
+gjbEj5Zsvt1fL09jJPwZXgsbr38Q33evuLFcV60J3m+xLvSC0BBBJgzqEHGFmks3hDYjA1TcJIje
+7Hdb4ldLJB3nVzgGyhUqXcL5qE6sOJ6y91lYL3xqnlWVbnDwwrxzO+TgDeHDSjKUZ8oCA5mnPwIW
+VvGAUIlpCRteCLjtsvZUuHN1drtKIvjXcRAc+mdrGgyL6VU97abQcre3zQQIib9la1MRHaUFK/Mj
+ehPatzvs57Z34DIGE2Ga31CORF8N9KCgGXl+J+bTu7IDtwJfCPqgze1yHIjVPOxh7bgh0Txq/Rhv
+19y2ApB8OK8XseNWkotsOCbvtxJ2VQRIrE4hEQKk1Bwib5Qre5Avokp48/szNYeujzfp3jNRjHJA
+4QZviLMlD8MaqlPpAqNoZD/Egg2QSUMPO6Er7CEqETbQuYxK2JybwiyJZrr9cTWdBPfsfUJn6y+a
+0+tBdxdkAv2e7oKccksQBSTRGobY7OtFKcOo/ZPD2B+EviHPlddrJjiNCU/ntfimWdiIaD4cMDTy
+5j1rTWrSyGaEh4DCx5QahT8KkOrQdTcfBR/Bz+roHaUDl85KIJN2vQMIV6cqf0XckU4UJD9Gqg/A
+__EOF__
+;
+ close FX2;
+ return $filename;
+}
+
diff --git a/fpga/examples/pong/pong.ucf b/fpga/examples/pong/pong.ucf
new file mode 100644
index 0000000..785eb95
--- /dev/null
+++ b/fpga/examples/pong/pong.ucf
@@ -0,0 +1,56 @@
+# NET "sw<0>" LOC= "G18";
+# NET "sw<1>" LOC= "H18";
+# NET "sw<2>" LOC= "K18";
+# NET "sw<3>" LOC= "K17";
+# NET "sw<4>" LOC= "L14";
+# NET "sw<5>" LOC= "L13";
+# NET "sw<6>" LOC= "N17";
+# NET "sw<7>" LOC= "R17";
+
+# NET "btn<0>" LOC= "B18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN0
+# NET "btn<1>" LOC= "D18"; # Bank = 1 , Pin name = IP/VREF_1 , Type = VREF , Sch name = BTN1
+# NET "btn<2>" LOC= "E18"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN2
+# NET "btn<3>" LOC= "H13"; # Bank = 1 , Pin name = IP , Type = INPUT , Sch name = BTN3
+
+# Pin assignment for Leds
+# Connected to Nexys 2
+NET "Led<0>" LOC= "J14"; # Bank = 1 , Pin name = IO_L14N_1/A3/RHCLK7 , Type = RHCLK/DUAL , Sch name = JD10/LD0
+NET "Led<1>" LOC= "J15"; # Bank = 1 , Pin name = IO_L14P_1/A4/RHCLK6 , Type = RHCLK/DUAL , Sch name = JD9/LD1
+NET "Led<2>" LOC= "K15"; # Bank = 1 , Pin name = IO_L12P_1/A8/RHCLK2 , Type = RHCLK/DUAL , Sch name = JD8/LD2
+NET "Led<3>" LOC= "K14"; # Bank = 1 , Pin name = IO_L12N_1/A7/RHCLK3/TRDY1 , Type = RHCLK/DUAL , Sch name = JD7/LD3
+NET "Led<4>" LOC= "E16"; # Bank = 1 , Pin name = N.C. , Type = N.C. , Sch name = LD4? other than s3e500
+NET "Led<5>" LOC= "P16"; # Bank = 1 , Pin name = N.C. , Type = N.C. , Sch name = LD5? other than s3e500
+NET "Led<6>" LOC= "E4"; # Bank = 3 , Pin name = N.C. , Type = N.C. , Sch name = LD6? other than s3e500
+NET "Led<7>" LOC= "P4"; # Bank = 3 , Pin name = N.C. , Type = N.C. , Sch name = LD7? other than s3e500
+
+ NET "seg<0>" LOC= "L18"; # Bank = 1 , Pin name = IO_L10P_1 , Type = I/O , Sch name = CA
+ NET "seg<1>" LOC= "F18"; # Bank = 1 , Pin name = IO_L19P_1 , Type = I/O , Sch name = CB
+ NET "seg<2>" LOC= "D17"; # Bank = 1 , Pin name = IO_L23P_1/HDC , Type = DUAL , Sch name = CC
+ NET "seg<3>" LOC= "D16"; # Bank = 1 , Pin name = IO_L23N_1/LDC0 , Type = DUAL , Sch name = CD
+ NET "seg<4>" LOC= "G14"; # Bank = 1 , Pin name = IO_L20P_1 , Type = I/O , Sch name = CE
+ NET "seg<5>" LOC= "J17"; # Bank = 1 , Pin name = IO_L13P_1/A6/RHCLK4/IRDY1 , Type = RHCLK/DUAL , Sch name = CF
+ NET "seg<6>" LOC= "H14"; # Bank = 1 , Pin name = IO_L17P_1 , Type = I/O , Sch name = CG
+ NET "dp" LOC= "C17"; # Bank = 1 , Pin name = IO_L24N_1/LDC2 , Type = DUAL , Sch name = DP
+
+ NET "an<0>" LOC= "F17"; # Bank = 1 , Pin name = IO_L19N_1 , Type = I/O , Sch name = AN0
+ NET "an<1>" LOC= "H17"; # Bank = 1 , Pin name = IO_L16N_1/A0 , Type = DUAL , Sch name = AN1
+ NET "an<2>" LOC= "C18"; # Bank = 1 , Pin name = IO_L24P_1/LDC1 , Type = DUAL , Sch name = AN2
+ NET "an<3>" LOC= "F15"; # Bank = 1 , Pin name = IO_L21P_1 , Type = I/O , Sch name = AN3
+
+NET "clk" LOC= "B8"; # Bank = 0 , Pin name = IP_L13P_0/GCLK8 , Type = GCLK , Sch name = GCLK0
+
+NET "PS2C" LOC= "R12" | PULLUP; # Bank = 2 , Pin name = IO_L20N_2 , Type = I/O , Sch name = PS2C
+NET "PS2D" LOC= "P11" | PULLUP; # Bank = 2 , Pin name = IO_L18P_2 , Type = I/O , Sch name = PS2D
+
+ NET "vga_out<0>" LOC= "R9"; # Bank = 2 , Pin name = IO/D5 , Type = DUAL , Sch name = RED0
+ NET "vga_out<1>" LOC= "T8"; # Bank = 2 , Pin name = IO_L10N_2 , Type = I/O , Sch name = RED1
+ NET "vga_out<2>" LOC= "R8"; # Bank = 2 , Pin name = IO_L10P_2 , Type = I/O , Sch name = RED2
+ NET "vga_out<3>" LOC= "N8"; # Bank = 2 , Pin name = IO_L09N_2 , Type = I/O , Sch name = GRN0
+ NET "vga_out<4>" LOC= "P8"; # Bank = 2 , Pin name = IO_L09P_2 , Type = I/O , Sch name = GRN1
+ NET "vga_out<5>" LOC= "P6"; # Bank = 2 , Pin name = IO_L05N_2 , Type = I/O , Sch name = GRN2
+ NET "vga_out<6>" LOC= "U5"; # Bank = 2 , Pin name = IO/VREF_2 , Type = VREF , Sch name = BLU1
+ NET "vga_out<7>" LOC= "U4"; # Bank = 2 , Pin name = IO_L03P_2/DOUT/BUSY , Type = DUAL , Sch name = BLU2
+
+ NET "Hsync" LOC= "T4" | PULLUP; # Bank = 2 , Pin name = IO_L03N_2/MOSI/CSI_B , Type = DUAL , Sch name = HSYNC
+ NET "Vsync" LOC= "U3" | PULLUP; # Bank = 2 , Pin name = IO_L01P_2/CSO_B , Type = DUAL , Sch name = VSYNC
+
diff --git a/fpga/examples/pong/pong.vhd b/fpga/examples/pong/pong.vhd
new file mode 100644
index 0000000..e41641e
--- /dev/null
+++ b/fpga/examples/pong/pong.vhd
@@ -0,0 +1,211 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity pong is
+ port (
+ clk : in std_logic;
+
+-- btn : in std_logic_vector(3 downto 0);
+ Led : out std_logic_vector(7 downto 0);
+-- usb : in std_logic;
+-- sw : in std_logic_vector(7 downto 0);
+
+ seg : out std_logic_vector(6 downto 0);
+ dp : out std_logic;
+ an : out std_logic_vector(3 downto 0);
+
+ ps2c : in std_logic;
+ ps2d : in std_logic;
+
+ vga_out : out std_logic_vector(7 downto 0);
+ hsync : out std_logic;
+ vsync : out std_logic
+ );
+end entity pong;
+
+architecture pong of pong is
+
+ component draw is
+ generic (
+ size_x : positive := 400;
+ size_y : positive := 400
+ );
+ port (
+ update : in std_logic;
+ x_pos : in integer range 0 to 639;
+ y_pos : in integer range 0 to 479;
+ ball_x : in integer range 0 to size_x - 1;
+ ball_y : in integer range 0 to size_y - 1;
+ color : out std_logic_vector (7 downto 0));
+ end component;
+
+ component vga is
+ port(clk : in std_logic;
+ hsync : out std_logic;
+ vsync : out std_logic;
+ active : out std_logic;
+ pixel_clk : out std_logic;
+ x_pos : out integer range 0 to 639;
+ y_pos : out integer range 0 to 479
+ );
+ end component;
+
+ component driver_ps2 is
+ port (clk : in std_logic;
+ ps2d : in std_logic;
+ ps2c : in std_logic;
+ data : out std_logic_vector ( 0 to 7 );
+ int : out std_logic );
+ end component;
+
+ component keyboard is
+ port (clk : in std_logic;
+ data_in : in std_logic_vector ( 0 to 7 );
+ int_in : in std_logic;
+ extended : out std_logic;
+ up : out std_logic;
+ code : out std_logic_vector ( 0 to 7 );
+ int : out std_logic );
+ end component;
+
+ component simple_7seg is
+ port(clk : in std_logic;
+ value : in std_logic_vector (15 downto 0);
+ pti : in std_logic_vector(3 downto 0);
+ seg : out std_logic_vector(6 downto 0);
+ pto : out std_logic;
+ an : out std_logic_vector(3 downto 0) );
+ end component;
+
+ component game is
+ generic (
+ size_x : positive := 400;
+ size_y : positive := 400);
+ port (
+ clk : in std_logic;
+ scan_code : in std_logic_vector ( 7 downto 0 );
+ up_key : in std_logic;
+ extended_key : in std_logic;
+ key_int : in std_logic;
+ ball_x : out integer range 0 to size_x - 1;
+ ball_y : out integer range 0 to size_y - 1;
+ keys : out std_logic_vector ( 3 downto 0 )
+ );
+ end component;
+
+ constant size_x : integer := 400;
+ constant size_y : integer := 400;
+
+ signal vga_color : std_logic_vector ( 7 downto 0 );
+ signal internal_vsync : std_logic;
+ signal vga_x : integer range 0 to 639;
+ signal vga_y : integer range 0 to 479;
+
+ signal active_output : std_logic;
+ signal pixel_clk : std_logic;
+
+-- ps2 keyboard signals
+ signal ps2_data : std_logic_vector ( 7 downto 0 );
+ signal scan_code : std_logic_vector ( 7 downto 0 );
+ signal ps2_int : std_logic;
+ signal key_up : std_logic;
+ signal key_extended : std_logic;
+ signal key_int : std_logic;
+
+ signal slow_clk : std_logic;
+ signal value_7seg : std_logic_vector ( 15 downto 0 );
+ signal point_7seg : std_logic_vector ( 3 downto 0 );
+
+-- game data
+ signal ball_x : integer range 0 to size_x - 1;
+ signal ball_y : integer range 0 to size_y - 1;
+begin
+
+ vsync <= internal_vsync;
+ vga_out <= vga_color;
+
+ draw_1 : draw
+ generic map
+ (
+ size_x,
+ size_y
+ )
+ port map
+ ( internal_vsync,
+ vga_x,
+ vga_y,
+ ball_x,
+ ball_y,
+ vga_color
+ );
+
+ game_1 : game
+ generic map (
+ size_x,
+ size_y)
+ port map (
+ clk,
+ scan_code,
+ key_up,
+ key_extended,
+ key_int,
+ ball_x,
+ ball_y,
+ led ( 3 downto 0 )
+ );
+
+ led ( 7 downto 4 ) <= "0000";
+
+ vga_1 : vga port map
+ ( clk,
+ hsync,
+ internal_vsync,
+ active_output,
+ pixel_clk,
+ vga_x,
+ vga_y
+ );
+
+ driver_ps2_1 : driver_ps2 port map
+ ( clk,
+ ps2d,
+ ps2c,
+ ps2_data,
+ ps2_int
+ );
+
+ keyboard_1 : keyboard port map
+ ( clk,
+ ps2_data,
+ ps2_int,
+ key_extended,
+ key_up,
+ scan_code,
+ key_int
+ );
+
+ simple_7seg_1 : simple_7seg port map
+ ( slow_clk,
+ value_7seg,
+ point_7seg,
+ seg,
+ dp,
+ an
+ );
+
+
+ process (clk)
+ variable count : integer range 0 to 65535 := 0;
+ variable tmp_std : std_logic_vector ( 15 downto 0 );
+ begin
+ if rising_edge(clk) then
+ count := count + 1;
+ end if;
+ tmp_std := conv_std_logic_vector(count,16);
+ slow_clk <= tmp_std(15);
+ end process;
+
+end architecture;
+
diff --git a/fpga/examples/pong/ps2.vhd b/fpga/examples/pong/ps2.vhd
new file mode 100644
index 0000000..1981c56
--- /dev/null
+++ b/fpga/examples/pong/ps2.vhd
@@ -0,0 +1,95 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity driver_ps2 is
+ port (clk : in std_logic;
+ ps2d : in std_logic;
+ ps2c : in std_logic;
+ data : out std_logic_vector ( 0 to 7 );
+ int : out std_logic );
+end entity driver_ps2;
+
+architecture driver_ps2 of driver_ps2 is
+type state_type is ( bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7,
+ bit8, bit9, end_state, error_state );
+signal tmp : std_logic_vector ( 8 downto 1 ) := "00000000";
+signal state : state_type := bit0;
+signal int_l : std_logic := '0';
+signal data_l : std_logic_vector ( 0 to 7 ) := "00000000";
+signal ps2_clk : std_logic := '1';
+signal ps2_data : std_logic := '1';
+begin
+
+process (clk)
+begin
+ if (rising_edge(clk)) then
+ ps2_clk <= ps2c;
+ end if;
+end process;
+
+process (clk)
+begin
+ if (rising_edge(clk)) then
+ ps2_data <= ps2d;
+ end if;
+end process;
+
+int <= int_l;
+data <= data_l;
+
+process (ps2_clk)
+begin
+ if (falling_edge(ps2_clk))
+ then
+ case state is
+ when bit0 =>
+ if ps2_data = '0'
+ then state <= bit1;
+ else state <= error_state;
+ end if;
+ when bit1 =>
+ state <= bit2;
+ tmp(1) <= ps2_data;
+ when bit2 =>
+ state <= bit3;
+ tmp(2) <= ps2_data;
+ when bit3 =>
+ state <= bit4;
+ tmp(3) <= ps2_data;
+ when bit4 =>
+ state <= bit5;
+ tmp(4) <= ps2_data;
+ when bit5 =>
+ state <= bit6;
+ tmp(5) <= ps2_data;
+ when bit6 =>
+ state <= bit7;
+ tmp(6) <= ps2_data;
+ when bit7 =>
+ state <= bit8;
+ tmp(7) <= ps2_data;
+ when bit8 =>
+ state <= bit9;
+ tmp(8) <= ps2_data;
+ when bit9 =>
+ state <= end_state;
+ -- tmp(9) <= ps2_data;
+ -- should verify parity
+ int_l <= '1';
+ data_l <= tmp(8 downto 1);
+ when end_state =>
+ int_l <= '0';
+ if ps2_data = '1'
+ then state <= bit0;
+ else state <= error_state;
+ end if;
+ when error_state =>
+ state <= error_state;
+ -- should make something to recover
+ end case;
+
+ end if;
+end process;
+
+end driver_ps2;
diff --git a/fpga/examples/pong/simple_7seg.vhd b/fpga/examples/pong/simple_7seg.vhd
new file mode 100644
index 0000000..32bdc6d
--- /dev/null
+++ b/fpga/examples/pong/simple_7seg.vhd
@@ -0,0 +1,97 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package decoder is
+
+ function decoder (
+ signal val : std_logic_vector (3 downto 0))
+ return std_logic_vector;
+
+end decoder;
+
+package body decoder is
+
+ function decoder (signal val : std_logic_vector(3 downto 0))
+ return std_logic_vector is
+ variable tmp : std_logic_vector ( 6 downto 0 );
+ begin
+ case val is
+ when "0000" => tmp := "0111111";
+ when "0001" => tmp := "0000110";
+ when "0010" => tmp := "1011011";
+ when "0011" => tmp := "1001111";
+ when "0100" => tmp := "1100110";
+ when "0101" => tmp := "1101101";
+ when "0110" => tmp := "1111101";
+ when "0111" => tmp := "0000111";
+ when "1000" => tmp := "1111111";
+ when "1001" => tmp := "1101111";
+ when "1010" => tmp := "1110111";
+ when "1011" => tmp := "1111100";
+ when "1100" => tmp := "0111001";
+ when "1101" => tmp := "1011110";
+ when "1110" => tmp := "1111001";
+ when "1111" => tmp := "1110001";
+ when others => tmp := "0000000"; -- shouldn't happen
+ end case;
+ return (not tmp);
+ end function decoder;
+
+end decoder;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.decoder.ALL;
+
+entity simple_7seg is
+ port(clk : in std_logic;
+ value : in std_logic_vector (15 downto 0);
+ pti : in std_logic_vector(3 downto 0);
+ seg : out std_logic_vector(6 downto 0);
+ pto : out std_logic;
+ an : out std_logic_vector(3 downto 0) );
+end simple_7seg;
+
+architecture simple_7seg of simple_7seg is
+signal selected_value : std_logic_vector ( 3 downto 0 );
+begin
+
+seg <= decoder(selected_value);
+
+process (clk)
+ variable state : std_logic_vector (3 downto 0) := "0111";
+ variable out_value : std_logic_vector (3 downto 0) := "0000";
+ variable out_pt : std_logic;
+begin
+ if rising_edge(clk) then
+ case state is
+ when "0111" =>
+ state := "1011";
+ out_value := value (15 downto 12);
+ out_pt := pti(3);
+ when "1011" =>
+ state := "1101";
+ out_value := value (11 downto 8);
+ out_pt := pti(2);
+ when "1101" =>
+ state := "1110";
+ out_value := value (7 downto 4);
+ out_pt := pti(1);
+ when others =>
+ state := "0111";
+ out_value := value (3 downto 0);
+ out_pt := pti(0);
+ end case;
+ end if;
+ an <= state;
+ selected_value <= out_value;
+ pto <= not out_pt;
+end process;
+
+end simple_7seg;
diff --git a/fpga/examples/pong/vga.vhd b/fpga/examples/pong/vga.vhd
new file mode 100644
index 0000000..9d6a2f8
--- /dev/null
+++ b/fpga/examples/pong/vga.vhd
@@ -0,0 +1,124 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity vga is
+ port(clk : in std_logic;
+ hsync : out std_logic;
+ vsync : out std_logic;
+ active : out std_logic;
+ pixel_clk : out std_logic;
+ x_pos : out integer range 0 to 639;
+ y_pos : out integer range 0 to 479
+ );
+end vga;
+
+architecture vga of vga is
+ signal internal_hsync : std_logic;
+ signal internal_vsync : std_logic;
+ signal internal_pixel_clk : std_logic;
+ signal h_active : std_logic;
+ signal v_active : std_logic;
+
+begin
+
+ pixel_clk <= internal_pixel_clk;
+ hsync <= internal_hsync;
+ vsync <= internal_vsync;
+ active <= '1' when ( h_active = '1' ) and ( v_active = '1' ) else '0';
+
+ pixel_clock: process (clk)
+ variable tmp : std_logic := '0';
+ begin
+ if rising_edge(clk) then
+ tmp := not tmp;
+ end if;
+ internal_pixel_clk <= tmp;
+ end process pixel_clock;
+
+ h_pixel_counter : process (internal_pixel_clk)
+ constant line_length : integer := 800;
+ constant pulse_length : integer := 96;
+ constant front_porch : integer := 16;
+ constant back_porch : integer := 48;
+ variable counter : integer range 0 to line_length + 1 := 0;
+ variable sync_state : std_logic := '1';
+ variable h_state : std_logic := '0';
+ variable x_pos_v : integer range 0 to 640 := 0;
+ begin
+ if (rising_edge(internal_pixel_clk))
+ then
+ if counter = 0 then
+ sync_state := '0';
+ x_pos_v := 0;
+ end if;
+ if counter = pulse_length then
+ sync_state := '1';
+ end if;
+
+ if h_state = '1' then
+ x_pos_v := x_pos_v + 1;
+ end if;
+
+ if counter = front_porch + pulse_length then
+ h_state := '1';
+ end if;
+ if counter = line_length - back_porch then
+ h_state := '0';
+ end if;
+
+ counter := counter + 1;
+ if counter = line_length then
+ counter := 0;
+ end if;
+ end if;
+
+ internal_hsync <= sync_state;
+ h_active <= h_state;
+ x_pos <= x_pos_v;
+ end process h_pixel_counter;
+
+ v_pixel_counter : process (internal_hsync)
+ constant line_length : integer := 521;
+ constant pulse_length : integer := 2;
+ constant front_porch : integer := 10;
+ constant back_porch : integer := 29;
+ variable counter : integer range 0 to line_length + 1 := 0;
+ variable sync_state : std_logic := '1';
+ variable v_state : std_logic := '0';
+ variable y_pos_v : integer range 0 to 480 := 0;
+ begin
+ if (falling_edge(internal_hsync))
+ then
+ if counter = 0 then
+ sync_state := '0';
+ y_pos_v := 0;
+ end if;
+ if counter = pulse_length then
+ sync_state := '1';
+ end if;
+
+ if v_state = '1' then
+ y_pos_v := y_pos_v + 1;
+ end if;
+
+ if counter = pulse_length + front_porch then
+ v_state := '1';
+ end if;
+ if counter = line_length - back_porch then
+ v_state := '0';
+ end if;
+
+ counter := counter + 1;
+ if counter = line_length then
+ counter := 0;
+ end if;
+ end if;
+
+ internal_vsync <= sync_state;
+ v_active <= v_state;
+ y_pos <= y_pos_v;
+ end process v_pixel_counter;
+
+end vga;
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2010-01-23 00:04:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 32e007d2e96e6c74fb68e0e935756940639e23e9 (commit)
from 2ed5b75bc97dc9f10baf67f6f9a199a514e992b5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 32e007d2e96e6c74fb68e0e935756940639e23e9
Author: chambart <cha...@cr...>
Date: Sat Jan 23 01:03:25 2010 +0100
add toy vga handling and ( bugged ) mouse
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/mouse.vhd b/fpga/components/mouse.vhd
new file mode 100644
index 0000000..9d9b7e1
--- /dev/null
+++ b/fpga/components/mouse.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity mouse is
+ port (clk : in std_logic;
+ data_in : in std_logic_vector ( 0 to 7 );
+ int_in : in std_logic;
+
+ left_button : out std_logic;
+ right_button : out std_logic;
+ x_pos : out std_logic_vector ( 8 downto 0 );
+ y_pos : out std_logic_vector ( 8 downto 0 );
+ int : out std_logic );
+end entity mouse;
+
+architecture mouse of mouse is
+ type state_type is ( waiting, bit1, bit2, end_state );
+begin
+
+process (clk)
+ variable state : state_type := end_state;
+ variable x_pos_v : std_logic_vector ( 7 downto 0 );
+ variable y_pos_v : std_logic_vector ( 7 downto 0 );
+ variable data_v : std_logic_vector ( 7 downto 0 );
+ variable old_int_in : std_logic := '0';
+begin
+ if(rising_edge(clk))
+ then
+ case state is
+ when end_state =>
+ state := waiting;
+ int <= '0';
+ when waiting =>
+ if(int_in = '1' and old_int_in = '0')
+ then
+ state := bit1;
+ data_v := data_in;
+ end if;
+ when bit1 =>
+ if(int_in = '1' and old_int_in = '0')
+ then
+ state := bit2;
+ x_pos_v := data_in;
+ end if;
+ when bit2 =>
+ if(int_in = '1' and old_int_in = '0')
+ then
+ state := end_state;
+ y_pos_v := data_in;
+ int <= '1';
+ end if;
+ end case;
+
+ old_int_in := int_in;
+ end if;
+
+ -- I should handle overflow and the bits seams to be in the wrong order
+ x_pos <= data_v(4)&x_pos_v; -- that should be converted to signed integer
+ y_pos <= data_v(5)&y_pos_v;
+ left_button <= data_v(0);
+ right_button <= data_v(1);
+end process;
+
+end mouse;
diff --git a/fpga/components/vga.vhd b/fpga/components/vga.vhd
new file mode 100644
index 0000000..4e3086f
--- /dev/null
+++ b/fpga/components/vga.vhd
@@ -0,0 +1,127 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity vga is
+ port(clk : in std_logic;
+ color : in std_logic_vector( 7 downto 0 );
+ vga_data : out std_logic_vector( 7 downto 0 );
+ hsync : out std_logic;
+ vsync : out std_logic
+ );
+end vga;
+
+architecture vga of vga is
+ signal internal_hsync : std_logic;
+ signal internal_vsync : std_logic;
+ signal pixel_clk : std_logic := '0';
+ signal h_active : std_logic;
+ signal v_active : std_logic;
+ signal x_pos : integer range 0 to 639 := 0;
+ signal y_pos : integer range 0 to 479 := 0;
+ signal x_vec : std_logic_vector ( 5 downto 0 );
+ signal y_vec : std_logic_vector ( 5 downto 0 );
+begin
+
+ pixel_clock: process (clk)
+ variable tmp : std_logic := '0';
+ begin
+ if rising_edge(clk) then
+ tmp := not tmp;
+ end if;
+ pixel_clk <= tmp;
+ end process pixel_clock;
+
+ hsync <= internal_hsync;
+ vsync <= internal_vsync;
+ x_vec <= conv_std_logic_vector(x_pos,6);
+ y_vec <= conv_std_logic_vector(y_pos,6);
+ vga_data <= color when (h_active = '1' and v_active = '1'
+ and (x_vec(5) = '1' xor y_vec(5) = '1')) else "00000000";
+
+ h_pixel_counter : process (pixel_clk)
+ constant line_length : integer := 800;
+ constant pulse_length : integer := 96;
+ constant front_porch : integer := 16;
+ constant back_porch : integer := 48;
+ variable counter : integer range 0 to line_length + 1 := 0;
+ variable sync_state : std_logic := '1';
+ variable h_state : std_logic := '0';
+ variable x_pos_v : integer range 0 to 640 := 0;
+ begin
+ if (rising_edge(pixel_clk))
+ then
+ if counter = 0 then
+ sync_state := '0';
+ x_pos_v := 0;
+ end if;
+ if counter = pulse_length then
+ sync_state := '1';
+ end if;
+
+ if h_state = '1' then
+ x_pos_v := x_pos_v + 1;
+ end if;
+
+ if counter = front_porch + pulse_length then
+ h_state := '1';
+ end if;
+ if counter = line_length - back_porch then
+ h_state := '0';
+ end if;
+
+ counter := counter + 1;
+ if counter = line_length then
+ counter := 0;
+ end if;
+ end if;
+
+ internal_hsync <= sync_state;
+ h_active <= h_state;
+ x_pos <= x_pos_v;
+ end process h_pixel_counter;
+
+ v_pixel_counter : process (internal_hsync)
+ constant line_length : integer := 521;
+ constant pulse_length : integer := 2;
+ constant front_porch : integer := 10;
+ constant back_porch : integer := 29;
+ variable counter : integer range 0 to line_length + 1 := 0;
+ variable sync_state : std_logic := '1';
+ variable v_state : std_logic := '0';
+ variable y_pos_v : integer range 0 to 480 := 0;
+ begin
+ if (falling_edge(internal_hsync))
+ then
+ if counter = 0 then
+ sync_state := '0';
+ y_pos_v := 0;
+ end if;
+ if counter = pulse_length then
+ sync_state := '1';
+ end if;
+
+ if v_state = '1' then
+ y_pos_v := y_pos_v + 1;
+ end if;
+
+ if counter = pulse_length + front_porch then
+ v_state := '1';
+ end if;
+ if counter = line_length - back_porch then
+ v_state := '0';
+ end if;
+
+ counter := counter + 1;
+ if counter = line_length then
+ counter := 0;
+ end if;
+ end if;
+
+ internal_vsync <= sync_state;
+ v_active <= v_state;
+ y_pos <= y_pos_v;
+ end process v_pixel_counter;
+
+end vga;
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2010-01-21 08:43:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 2ed5b75bc97dc9f10baf67f6f9a199a514e992b5 (commit)
from 53d3fd5f24468a828638064afc10bcbc691c4959 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2ed5b75bc97dc9f10baf67f6f9a199a514e992b5
Author: chambart <cha...@cr...>
Date: Thu Jan 21 09:20:14 2010 +0100
Add componnent keyboard
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/keyboard.vhd b/fpga/components/keyboard.vhd
new file mode 100644
index 0000000..88a8882
--- /dev/null
+++ b/fpga/components/keyboard.vhd
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity keyboard is
+ port (clk : in std_logic;
+ data_in : in std_logic_vector ( 0 to 7 );
+ int_in : in std_logic;
+
+ extended : out std_logic;
+ up : out std_logic;
+ code : out std_logic_vector ( 0 to 7 );
+ int : out std_logic );
+end entity keyboard;
+
+architecture keyboard of keyboard is
+ type state_type is ( waiting, end_state );
+ signal tmp_extended, tmp_up : std_logic;
+begin
+
+process (clk)
+ variable state : state_type := end_state;
+ variable old_int_in : std_logic := '0';
+begin
+ if(rising_edge(clk))
+ then
+ case state is
+ when end_state =>
+ state := waiting;
+ int <= '0';
+ tmp_extended <= '0';
+ tmp_up <= '0';
+ when waiting =>
+ if(int_in = '1' and old_int_in = '0')
+ then
+ case data_in is
+ when "11100000" =>
+ tmp_extended <= '1';
+ state := waiting;
+ when "11110000" =>
+ tmp_up <= '1';
+ state := waiting;
+ when others =>
+ code <= data_in;
+ extended <= tmp_extended;
+ up <= tmp_up;
+ state := end_state;
+ int <= '1';
+ end case;
+ end if;
+ end case;
+
+ old_int_in := int_in;
+ end if;
+end process;
+
+end keyboard;
hooks/post-receive
--
krobot-resources
|
|
From: Xavier L. <Sup...@us...> - 2010-01-19 20:24:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 53d3fd5f24468a828638064afc10bcbc691c4959 (commit)
from 86ffd07f121410283a1413532a0660ba535e0cd3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 53d3fd5f24468a828638064afc10bcbc691c4959
Author: Xavier Lagorce <Xav...@cr...>
Date: Tue Jan 19 19:32:58 2010 +0100
Comments in .ucf files are '#' and not '--'...
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/examples/example_driver_7segs.ucf b/fpga/examples/example_driver_7segs.ucf
index b125f1a..36def0f 100644
--- a/fpga/examples/example_driver_7segs.ucf
+++ b/fpga/examples/example_driver_7segs.ucf
@@ -1,10 +1,10 @@
--- UCF file for the Nexys 2 board
--- This file is associated to the example_driver_7segs.vhd design
+# UCF file for the Nexys 2 board
+# This file is associated to the example_driver_7segs.vhd design
--- Clock input
+# Clock input
NET "clk" LOC = "B8";
--- LEDs
+# LEDs
NET "Led<0>" LOC = "J14";
NET "Led<1>" LOC = "J15";
NET "Led<2>" LOC = "K15";
@@ -14,7 +14,7 @@ NET "Led<5>" LOC = "P16";
NET "Led<6>" LOC = "E4";
NET "Led<7>" LOC = "P4";
--- 7 segments display
+# 7 segments display
NET "a" LOC = "L18";
NET "b" LOC = "F18";
NET "c" LOC = "D17";
@@ -29,7 +29,7 @@ NET "an1" LOC = "H17";
NET "an2" LOC = "C18";
NET "an3" LOC = "F15";
--- Switches
+# Switches
NET "sw<0>" LOC = "G18";
NET "sw<1>" LOC = "H18";
NET "sw<2>" LOC = "K18";
@@ -39,7 +39,7 @@ NET "sw<5>" LOC = "L13";
NET "sw<6>" LOC = "N17";
NET "sw<7>" LOC = "R17";
--- Buttons
+# Buttons
NET "btn<0>" LOC = "B18";
NET "btn<1>" LOC = "D18";
NET "btn<2>" LOC = "E18";
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2010-01-19 17:24:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 86ffd07f121410283a1413532a0660ba535e0cd3 (commit)
from 4e73c71039b1931729e4f364c68d8ad0301064ac (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 86ffd07f121410283a1413532a0660ba535e0cd3
Author: chambart <cha...@cr...>
Date: Tue Jan 19 18:23:42 2010 +0100
Working and clean basic ps2 component ( mouahahahahah )
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/ps2_ugly.vhd b/fpga/components/ps2_ugly.vhd
deleted file mode 100644
index 402af96..0000000
--- a/fpga/components/ps2_ugly.vhd
+++ /dev/null
@@ -1,75 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity driver_ps2 is
- port (clk : in std_logic;
- ps2d : in std_logic;
- ps2c : in std_logic;
- data : out std_logic_vector ( 0 to 7 );
- int : out std_logic;
- -- only for debugging purpose
- st : out std_logic_vector ( 4 downto 0 ) );
-end entity driver_ps2;
-
-architecture driver_ps2 of driver_ps2 is
-type state_type is ( bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7,
- bit8, bit9, end_state );
-signal tmp : std_logic_vector ( 9 downto 0 ) := "0000000000";
-signal state : state_type := bit0;
-signal got : std_logic := '0';
-signal int_l : std_logic := '0';
-signal data_l : std_logic_vector ( 0 to 7 ) := "00000000";
-signal ps2c_old : std_logic := '1';
-begin
-
-int <= int_l;
-data <= data_l;
-
-process (ps2c)
-begin
- if (falling_edge(ps2c))
- then
- case state is
- when bit0 =>
- state <= bit1;
- tmp(0) <= ps2d;
- when bit1 =>
- state <= bit2;
- tmp(1) <= ps2d;
- when bit2 =>
- state <= bit3;
- tmp(2) <= ps2d;
- when bit3 =>
- state <= bit4;
- tmp(3) <= ps2d;
- when bit4 =>
- state <= bit5;
- tmp(4) <= ps2d;
- when bit5 =>
- state <= bit6;
- tmp(5) <= ps2d;
- when bit6 =>
- state <= bit7;
- tmp(6) <= ps2d;
- when bit7 =>
- state <= bit8;
- tmp(7) <= ps2d;
- when bit8 =>
- state <= bit9;
- tmp(8) <= ps2d;
- when bit9 =>
- state <= end_state;
- tmp(9) <= ps2d;
- int_l <= '1';
- data_l <= tmp(8 downto 1);
- when end_state =>
- state <= bit0;
- int_l <= '0';
- end case;
-
- st <= "00000";
- end if;
-end process;
-
-end driver_ps2;
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2010-01-18 19:13:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 4e73c71039b1931729e4f364c68d8ad0301064ac (commit)
from 2d18070871a5b76a7a2dc20c9371a4f77b9588e2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4e73c71039b1931729e4f364c68d8ad0301064ac
Author: chambart <cha...@cr...>
Date: Mon Jan 18 20:13:09 2010 +0100
add an ugly (but working) version of ps2.vh2
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/ps2_ugly.vhd b/fpga/components/ps2_ugly.vhd
new file mode 100644
index 0000000..402af96
--- /dev/null
+++ b/fpga/components/ps2_ugly.vhd
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity driver_ps2 is
+ port (clk : in std_logic;
+ ps2d : in std_logic;
+ ps2c : in std_logic;
+ data : out std_logic_vector ( 0 to 7 );
+ int : out std_logic;
+ -- only for debugging purpose
+ st : out std_logic_vector ( 4 downto 0 ) );
+end entity driver_ps2;
+
+architecture driver_ps2 of driver_ps2 is
+type state_type is ( bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7,
+ bit8, bit9, end_state );
+signal tmp : std_logic_vector ( 9 downto 0 ) := "0000000000";
+signal state : state_type := bit0;
+signal got : std_logic := '0';
+signal int_l : std_logic := '0';
+signal data_l : std_logic_vector ( 0 to 7 ) := "00000000";
+signal ps2c_old : std_logic := '1';
+begin
+
+int <= int_l;
+data <= data_l;
+
+process (ps2c)
+begin
+ if (falling_edge(ps2c))
+ then
+ case state is
+ when bit0 =>
+ state <= bit1;
+ tmp(0) <= ps2d;
+ when bit1 =>
+ state <= bit2;
+ tmp(1) <= ps2d;
+ when bit2 =>
+ state <= bit3;
+ tmp(2) <= ps2d;
+ when bit3 =>
+ state <= bit4;
+ tmp(3) <= ps2d;
+ when bit4 =>
+ state <= bit5;
+ tmp(4) <= ps2d;
+ when bit5 =>
+ state <= bit6;
+ tmp(5) <= ps2d;
+ when bit6 =>
+ state <= bit7;
+ tmp(6) <= ps2d;
+ when bit7 =>
+ state <= bit8;
+ tmp(7) <= ps2d;
+ when bit8 =>
+ state <= bit9;
+ tmp(8) <= ps2d;
+ when bit9 =>
+ state <= end_state;
+ tmp(9) <= ps2d;
+ int_l <= '1';
+ data_l <= tmp(8 downto 1);
+ when end_state =>
+ state <= bit0;
+ int_l <= '0';
+ end case;
+
+ st <= "00000";
+ end if;
+end process;
+
+end driver_ps2;
hooks/post-receive
--
krobot-resources
|
|
From: Olivier B. <Sup...@us...> - 2010-01-18 18:44:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 2d18070871a5b76a7a2dc20c9371a4f77b9588e2 (commit)
from ba642d9142f0b7a05347e682bb0f3add311919ea (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2d18070871a5b76a7a2dc20c9371a4f77b9588e2
Author: unknown <Olivier@.(none)>
Date: Mon Jan 18 19:43:02 2010 +0100
Ajout d'un registre (pour le registre file d'un processeur SMIPS par exemple)
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/reg_file.vhd b/fpga/components/reg_file.vhd
new file mode 100644
index 0000000..e8ff18c
--- /dev/null
+++ b/fpga/components/reg_file.vhd
@@ -0,0 +1,60 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer: O. Bichler
+--
+-- Create Date: 18:27:15 01/18/2010
+-- Design Name:
+-- Module Name: reg_file - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity reg_file is
+ Port ( clk : in STD_LOGIC;
+ raddr0 : in STD_LOGIC_VECTOR (4 downto 0);
+ rdata0 : out STD_LOGIC_VECTOR (31 downto 0);
+ raddr1 : in STD_LOGIC_VECTOR (4 downto 0);
+ rdata1 : out STD_LOGIC_VECTOR (31 downto 0);
+ wen_p : in STD_LOGIC;
+ waddr_p : in STD_LOGIC_VECTOR (4 downto 0);
+ wdata_p : in STD_LOGIC_VECTOR (31 downto 0));
+end reg_file;
+
+architecture Behavioral of reg_file is
+ type reg_array is array(integer range <>) of STD_LOGIC_VECTOR (wdata_p'range);
+ signal reg: reg_array(0 to 2**waddr_p'length-1);
+
+begin
+ -- Combinational read ports
+ rdata0 <= reg(TO_INTEGER(UNSIGNED(raddr0)));
+ rdata1 <= reg(TO_INTEGER(UNSIGNED(raddr1)));
+
+ -- Write port is active only when wen_p is asserted
+ process(clk)
+ begin
+ if clk'event and clk='1' then
+ if wen_p='1' then
+ reg(TO_INTEGER(UNSIGNED(waddr_p))) <= wdata_p;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
+
hooks/post-receive
--
krobot-resources
|
|
From: Xavier L. <Sup...@us...> - 2010-01-16 20:57:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via ba642d9142f0b7a05347e682bb0f3add311919ea (commit)
via be079913ec09e057766a1a94f70f3faeaf5be832 (commit)
from 3a7f79075458193293d3d99381f0ec25fa56b3a2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ba642d9142f0b7a05347e682bb0f3add311919ea
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 21:52:10 2010 +0100
Adding an usage example of the driver_7seg and decoder_7seg components
commit be079913ec09e057766a1a94f70f3faeaf5be832
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 21:48:05 2010 +0100
Added comments in the files and corrected some errors in the design.
This version of the driver is operational
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/decoder_7seg.vhd b/fpga/components/decoder_7seg.vhd
index dcf698b..b39ea79 100644
--- a/fpga/components/decoder_7seg.vhd
+++ b/fpga/components/decoder_7seg.vhd
@@ -19,16 +19,16 @@ use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_7seg is
- port(val : in std_logic_vector(3 downto 0);
- pti : in std_logic;
- a : out std_logic;
- b : out std_logic;
- c : out std_logic;
- d : out std_logic;
- e : out std_logic;
- f : out std_logic;
- g : out std_logic;
- pt : out std_logic
+ port(val : in std_logic_vector(3 downto 0); -- BCD value to decode
+ pti : in std_logic; -- Decimal point
+ a : out std_logic; -- Decoded segment
+ b : out std_logic; -- "
+ c : out std_logic; -- "
+ d : out std_logic; -- "
+ e : out std_logic; -- "
+ f : out std_logic; -- "
+ g : out std_logic; -- "
+ pt : out std_logic -- "
);
end decoder_7seg;
@@ -37,126 +37,126 @@ begin
process(val, pti)
begin
case val is
- when "0000" => a <= '1'; -- 0
- b <= '1';
- c <= '1';
- d <= '1';
- e <= '1';
- f <= '1';
- g <= '0';
- when "0001" => a <= '0'; -- 1
- b <= '1';
- c <= '1';
+ when "0000" => a <= '0'; -- 0
+ b <= '0';
+ c <= '0';
d <= '0';
e <= '0';
f <= '0';
- g <= '0';
- when "0010" => a <= '1'; -- 2
- b <= '1';
+ g <= '1';
+ when "0001" => a <= '1'; -- 1
+ b <= '0';
c <= '0';
d <= '1';
e <= '1';
- f <= '0';
- g <= '1';
- when "0011" => a <= '1'; -- 3
- b <= '1';
- c <= '1';
- d <= '1';
- e <= '0';
- f <= '0';
+ f <= '1';
g <= '1';
- when "0100" => a <= '0'; -- 4
- b <= '1';
+ when "0010" => a <= '0'; -- 2
+ b <= '0';
c <= '1';
d <= '0';
e <= '0';
f <= '1';
- g <= '1';
- when "0101" => a <= '1'; -- 5
+ g <= '0';
+ when "0011" => a <= '0'; -- 3
b <= '0';
- c <= '1';
- d <= '1';
- e <= '0';
+ c <= '0';
+ d <= '0';
+ e <= '1';
f <= '1';
- g <= '1';
- when "0110" => a <= '1'; -- 6
+ g <= '0';
+ when "0100" => a <= '1'; -- 4
b <= '0';
- c <= '1';
+ c <= '0';
d <= '1';
e <= '1';
- f <= '1';
- g <= '1';
- when "0111" => a <= '1'; -- 7
- b <= '1';
- c <= '1';
- d <= '0';
- e <= '0';
f <= '0';
g <= '0';
- when "1000" => a <= '1'; -- 8
+ when "0101" => a <= '0'; -- 5
b <= '1';
- c <= '1';
- d <= '1';
+ c <= '0';
+ d <= '0';
e <= '1';
- f <= '1';
- g <= '1';
- when "1001" => a <= '1'; -- 9
- b <= '1';
- c <= '1';
- d <= '1';
- e <= '0';
- f <= '1';
- g <= '1';
- when "1010" => a <= '1'; -- A
+ f <= '0';
+ g <= '0';
+ when "0110" => a <= '0'; -- 6
b <= '1';
- c <= '1';
+ c <= '0';
d <= '0';
- e <= '1';
- f <= '1';
- g <= '1';
- when "1011" => a <= '0'; -- B
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "0111" => a <= '0'; -- 7
b <= '0';
- c <= '1';
+ c <= '0';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
- when "1100" => a <= '1'; -- C
+ when "1000" => a <= '0'; -- 8
b <= '0';
c <= '0';
- d <= '1';
- e <= '1';
- f <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
g <= '0';
- when "1101" => a <= '0'; -- D
- b <= '1';
- c <= '1';
- d <= '1';
+ when "1001" => a <= '0'; -- 9
+ b <= '0';
+ c <= '0';
+ d <= '0';
e <= '1';
f <= '0';
- g <= '1';
- when "1110" => a <= '1'; -- E
+ g <= '0';
+ when "1010" => a <= '0'; -- A
b <= '0';
c <= '0';
d <= '1';
- e <= '1';
- f <= '1';
- g <= '1';
- when "1111" => a <= '1'; -- F
- b <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1011" => a <= '1'; -- B
+ b <= '1';
c <= '0';
d <= '0';
- e <= '1';
- f <= '1';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1100" => a <= '0'; -- C
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
g <= '1';
- when others => a <= '0'; -- shouldn't happen
+ when "1101" => a <= '1'; -- D
b <= '0';
c <= '0';
d <= '0';
e <= '0';
+ f <= '1';
+ g <= '0';
+ when "1110" => a <= '0'; -- E
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1111" => a <= '0'; -- F
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '0';
f <= '0';
g <= '0';
+ when others => a <= '1'; -- shouldn't happen
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '1';
end case;
end process;
- pt <= pti;
+ pt <= pti; -- don't need to decode the decimal point
end hexa_dec;
diff --git a/fpga/components/driver_7seg.vhd b/fpga/components/driver_7seg.vhd
index 4f1a551..b2293f5 100644
--- a/fpga/components/driver_7seg.vhd
+++ b/fpga/components/driver_7seg.vhd
@@ -24,17 +24,17 @@ entity driver_7seg is
dok : in STD_LOGIC; -- data OK
oe : in STD_LOGIC; -- output enable
a : out STD_LOGIC; -- segments
- b : out STD_LOGIC; -- ...
- c : out STD_LOGIC; -- ...
- d : out STD_LOGIC; -- ...
- e : out STD_LOGIC; -- ...
- f : out STD_LOGIC; -- ...
- g : out STD_LOGIC; -- ...
+ b : out STD_LOGIC; -- "
+ c : out STD_LOGIC; -- "
+ d : out STD_LOGIC; -- "
+ e : out STD_LOGIC; -- "
+ f : out STD_LOGIC; -- "
+ g : out STD_LOGIC; -- "
dp : out STD_LOGIC; -- decimal point
an0 : out STD_LOGIC; -- number selection
- an1 : out STD_LOGIC; -- ...
- an2 : out STD_LOGIC; -- ...
- an3 : out STD_LOGIC -- ...
+ an1 : out STD_LOGIC; -- "
+ an2 : out STD_LOGIC; -- "
+ an3 : out STD_LOGIC -- "
);
end driver_7seg;
@@ -58,22 +58,22 @@ signal display_state : std_logic_vector(1 downto 0);
signal output : std_logic_vector(7 downto 0);
-- Description
begin
- -- Multiplex to link the internal memories to the display
+ -- Multiplexer to link the internal memories to the display
display_mux : mux8_4 port map(display_state, val1, val2, val3, val4, output);
-- Link output of the multiplexer to the output lines going to the display
- a <= output(0);
- b <= output(1);
- c <= output(2);
- d <= output(3);
- e <= output(4);
- f <= output(5);
- g <= output(6);
- dp <= output(7);
+ a <= output(7);
+ b <= output(6);
+ c <= output(5);
+ d <= output(4);
+ e <= output(3);
+ f <= output(2);
+ g <= output(1);
+ dp <= output(0);
-- Display scanning
process (clk)
begin
if (clk'event and clk = '1') then
- if (oe = '1') then
+ if (oe = '1') then -- let's refresh if output is enabled
case display_state is
when "00" => display_state <= "01";
an0 <= '1';
@@ -102,7 +102,7 @@ begin
an3 <= '1';
end case;
else
- an0 <= '1';
+ an0 <= '1'; -- don't refresh if output disabled
an1 <= '1';
an2 <= '1';
an3 <= '1';
@@ -118,7 +118,7 @@ begin
when "01" => val2 <= data;
when "10" => val3 <= data;
when "11" => val4 <= data;
- when others => null;
+ when others => val1 <= data; -- shouldn't happen
end case;
end if;
end process;
diff --git a/fpga/examples/example_driver_7segs.ucf b/fpga/examples/example_driver_7segs.ucf
new file mode 100644
index 0000000..b125f1a
--- /dev/null
+++ b/fpga/examples/example_driver_7segs.ucf
@@ -0,0 +1,46 @@
+-- UCF file for the Nexys 2 board
+-- This file is associated to the example_driver_7segs.vhd design
+
+-- Clock input
+NET "clk" LOC = "B8";
+
+-- LEDs
+NET "Led<0>" LOC = "J14";
+NET "Led<1>" LOC = "J15";
+NET "Led<2>" LOC = "K15";
+NET "Led<3>" LOC = "K14";
+NET "Led<4>" LOC = "E16";
+NET "Led<5>" LOC = "P16";
+NET "Led<6>" LOC = "E4";
+NET "Led<7>" LOC = "P4";
+
+-- 7 segments display
+NET "a" LOC = "L18";
+NET "b" LOC = "F18";
+NET "c" LOC = "D17";
+NET "d" LOC = "D16";
+NET "e" LOC = "G14";
+NET "f" LOC = "J17";
+NET "g" LOC = "H14";
+NET "dp" LOC = "C17";
+
+NET "an0" LOC = "F17";
+NET "an1" LOC = "H17";
+NET "an2" LOC = "C18";
+NET "an3" LOC = "F15";
+
+-- Switches
+NET "sw<0>" LOC = "G18";
+NET "sw<1>" LOC = "H18";
+NET "sw<2>" LOC = "K18";
+NET "sw<3>" LOC = "K17";
+NET "sw<4>" LOC = "L14";
+NET "sw<5>" LOC = "L13";
+NET "sw<6>" LOC = "N17";
+NET "sw<7>" LOC = "R17";
+
+-- Buttons
+NET "btn<0>" LOC = "B18";
+NET "btn<1>" LOC = "D18";
+NET "btn<2>" LOC = "E18";
+NET "btn<3>" LOC = "H13";
diff --git a/fpga/examples/example_driver_7segs.vhd b/fpga/examples/example_driver_7segs.vhd
new file mode 100644
index 0000000..4e826fc
--- /dev/null
+++ b/fpga/examples/example_driver_7segs.vhd
@@ -0,0 +1,143 @@
+----------------------------------------------------------------------------------
+-- Create Date: 16/01/2010
+-- Module Name: example_driver_7segs
+-- Authors : X. Lagorce
+-- Description: Example for the 7 segments display
+-- This file shows the use of the driver_7seg and decoder_7seg
+-- components.
+--
+-- Dependencies: driver_7seg, decoder_7seg, div_clk
+--
+-- Revision:
+-- Revision 0.1 : First implementation
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity example_driver_7segs is
+ port( clk : in STD_LOGIC; -- refresh clock
+ a : out STD_LOGIC; -- segments
+ b : out STD_LOGIC; -- "
+ c : out STD_LOGIC; -- "
+ d : out STD_LOGIC; -- "
+ e : out STD_LOGIC; -- "
+ f : out STD_LOGIC; -- "
+ g : out STD_LOGIC; -- "
+ dp : out STD_LOGIC; -- decimal point
+ an0 : out STD_LOGIC; -- number selection
+ an1 : out STD_LOGIC; -- "
+ an2 : out STD_LOGIC; -- "
+ an3 : out STD_LOGIC; -- "
+ btn : in STD_LOGIC_VECTOR(3 downto 0);
+ sw : in STD_LOGIC_VECTOR(7 downto 0);
+ led : out STD_LOGIC_VECTOR(7 downto 0)
+ );
+end example_driver_7segs;
+
+architecture Behavioral of example_driver_7segs is
+-- Components declarations
+ component driver_7seg is
+ port( clk : in STD_LOGIC; -- refresh clock
+ data : in STD_LOGIC_VECTOR(7 downto 0); -- segments + decimal point
+ add : in STD_LOGIC_VECTOR(1 downto 0); -- segment address
+ dok : in STD_LOGIC; -- data OK
+ oe : in STD_LOGIC; -- output enable
+ a : out STD_LOGIC; -- segments
+ b : out STD_LOGIC; -- "
+ c : out STD_LOGIC; -- "
+ d : out STD_LOGIC; -- "
+ e : out STD_LOGIC; -- "
+ f : out STD_LOGIC; -- "
+ g : out STD_LOGIC; -- "
+ dp : out STD_LOGIC; -- decimal point
+ an0 : out STD_LOGIC; -- number selection
+ an1 : out STD_LOGIC; -- "
+ an2 : out STD_LOGIC; -- "
+ an3 : out STD_LOGIC -- "
+ );
+ end component;
+ component div_clk is
+ Port (clkin : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ clkout1 : out STD_LOGIC; -- 1.49 Hz
+ clkout2 : out STD_LOGIC; -- 763 Hz
+ clkout3 : out STD_LOGIC; -- 98 kHz
+ clkout4 : out STD_LOGIC); -- 1.56 MHz
+ end component;
+ component decoder_7seg is
+ port(val : in std_logic_vector(3 downto 0);
+ pti : in std_logic;
+ a : out std_logic;
+ b : out std_logic;
+ c : out std_logic;
+ d : out std_logic;
+ e : out std_logic;
+ f : out std_logic;
+ g : out std_logic;
+ pt : out std_logic
+ );
+ end component;
+ for all : driver_7seg use entity work.driver_7seg(Behavioral);
+ for all : div_clk use entity work.div_clk(Behavioral);
+ for all : decoder_7seg use entity work.decoder_7seg(hexa_dec);
+-- Signals declarations
+ signal data : std_logic_vector(7 downto 0);
+ signal add : std_logic_vector(1 downto 0);
+ signal val : std_logic_vector(3 downto 0);
+ signal dok, oe, reset, clk1, clk2, clk3, clk4 : std_logic;
+ signal ad, bd, cd, dd, ed, ffd, gd, ptd, pti : std_logic;
+-- Description
+begin
+ -- Components declarations
+ -- Let's get some slower clocks
+ div : div_clk port map (clk, reset, clk1, clk2, clk3, clk4);
+ -- The display driver
+ driver : driver_7seg port map (clk2, data, add, dok, oe, a, b, c,
+ d, e, f, g, dp, an0, an1, an2, an3);
+ -- component to decode BCD to 7 segments pattern
+ decoder : decoder_7seg port map (val, pti, ad, bd, cd, dd, ed,
+ ffd, gd, ptd);
+ -- Internal signals assignations
+ data(7) <= ad; -- vectorisation of the segments signals
+ data(6) <= bd;
+ data(5) <= cd;
+ data(4) <= dd;
+ data(3) <= ed;
+ data(2) <= ffd; -- fd is a keywork to add a Verilog
+ -- component in a VHDL design
+ data(1) <= gd;
+ data(0) <= ptd;
+
+ val <= sw(3 downto 0); -- enter a value on these switches
+ oe <= sw(4); -- this switch enables the output
+ pti <= sw(5); -- Decimal point
+
+ led(3 downto 0) <= val; -- display the value on LEDs
+ led(4) <= clk1; -- "I'm alive !" blinky
+ led(5) <= dok; -- Data OK signal
+ led(7 downto 6) <= add; -- Addressed display
+
+ reset <= '0'; -- Never reset the clock divider
+
+ -- Loading values into the driver
+ -- This process generates the address accordingly to the switch pressed
+ process (btn)
+ begin
+ case btn is
+ when "0001" => add <= "00";
+ dok <= '1';
+ when "0010" => add <= "01";
+ dok <= '1';
+ when "0100" => add <= "10";
+ dok <= '1';
+ when "1000" => add <= "11";
+ dok <= '1';
+ when others => add <= "00";
+ dok <= '0';
+ end case;
+ end process;
+end Behavioral;
hooks/post-receive
--
krobot-resources
|
|
From: Pierre C. <Sup...@us...> - 2010-01-16 19:52:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 3a7f79075458193293d3d99381f0ec25fa56b3a2 (commit)
via cc020eaa61c1655a5795790cf15d4f5123008f48 (commit)
from 2e229261d5a68ff1f8867bee6d279d8d9276fa27 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3a7f79075458193293d3d99381f0ec25fa56b3a2
Merge: cc020eaa61c1655a5795790cf15d4f5123008f48 2e229261d5a68ff1f8867bee6d279d8d9276fa27
Author: chambart <cha...@cr...>
Date: Sat Jan 16 20:52:17 2010 +0100
Merge branch 'master' of ssh://krobot.git.sourceforge.net/gitroot/krobot/krobot-resources
commit cc020eaa61c1655a5795790cf15d4f5123008f48
Author: chambart <cha...@cr...>
Date: Sat Jan 16 20:51:11 2010 +0100
Add a preliminary and buggy ps2 component
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/ps2.vhd b/fpga/components/ps2.vhd
new file mode 100644
index 0000000..a1630f9
--- /dev/null
+++ b/fpga/components/ps2.vhd
@@ -0,0 +1,108 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity driver_ps2 is
+ port (clk : in std_logic;
+ ps2d : in std_logic;
+ ps2c : in std_logic;
+ data : out std_logic_vector ( 0 to 7 );
+ int : out std_logic;
+ -- only for debugging purpose
+ st : out std_logic_vector ( 4 downto 0 ) );
+end entity driver_ps2;
+
+architecture driver_ps2 of driver_ps2 is
+type state_type is ( idle, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7,
+ bit8, bit9, end_state );
+signal tmp : std_logic_vector ( 9 downto 0 ) := "0000000000";
+signal state : state_type := idle;
+signal got : std_logic := '0';
+signal int_l : std_logic := '0';
+signal data_l : std_logic_vector ( 0 to 7 ) := "00000000";
+signal ps2c_old : std_logic := '1';
+begin
+
+int <= int_l;
+data <= data_l;
+
+process (clk)
+begin
+ if (rising_edge(clk))
+ then
+ ps2c_old <= ps2c;
+ if (( state = idle ) and ( ps2d = '0' ))
+ then
+ state <= bit0;
+ end if;
+ if (( ps2c_old = '1' ) and ( ps2c = '0' ))
+ then
+ case state is
+ when bit0 =>
+ state <= bit1;
+ tmp(0) <= ps2d;
+ when bit1 =>
+ state <= bit2;
+ tmp(1) <= ps2d;
+ when bit2 =>
+ state <= bit3;
+ tmp(2) <= ps2d;
+ when bit3 =>
+ state <= bit4;
+ tmp(3) <= ps2d;
+ when bit4 =>
+ state <= bit5;
+ tmp(4) <= ps2d;
+ when bit5 =>
+ state <= bit6;
+ tmp(5) <= ps2d;
+ when bit6 =>
+ state <= bit7;
+ tmp(6) <= ps2d;
+ when bit7 =>
+ state <= bit8;
+ tmp(7) <= ps2d;
+ when bit8 =>
+ state <= bit9;
+ tmp(8) <= ps2d;
+ when bit9 =>
+ state <= end_state;
+ tmp(9) <= ps2d;
+ int_l <= '1';
+ data_l <= tmp(8 downto 1);
+ when others =>
+ state <= idle;
+ int_l <= '0';
+ end case;
+ end if;
+
+ case state is
+ when idle =>
+ st <= ps2c&"0001";
+ when bit0 =>
+ st <= ps2c&"0010";
+ when bit1 =>
+ st <= ps2c&"0011";
+ when bit2 =>
+ st <= ps2c&"0100";
+ when bit3 =>
+ st <= ps2c&"0101";
+ when bit4 =>
+ st <= ps2c&"0111";
+ when bit5 =>
+ st <= ps2c&"1000";
+ when bit6 =>
+ st <= ps2c&"1001";
+ when bit7 =>
+ st <= ps2c&"1010";
+ when bit8 =>
+ st <= ps2c&"1011";
+ when bit9 =>
+ st <= ps2c&"1100";
+ when others =>
+ st <= ps2c&"1101";
+ end case;
+ end if;
+end process;
+
+end driver_ps2;
hooks/post-receive
--
krobot-resources
|
|
From: Stephane G. <Sup...@us...> - 2010-01-16 19:20:34
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 2e229261d5a68ff1f8867bee6d279d8d9276fa27 (commit)
from 39a9f01750a2a5da1e6b085fcac4fb4a4d12b509 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2e229261d5a68ff1f8867bee6d279d8d9276fa27
Author: Stephane Glondu <st...@gl...>
Date: Sat Jan 16 20:19:05 2010 +0100
Give permission 666 to nexys2 device node
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/usb_jtag/udev/92-fpga.rules b/fpga/usb_jtag/udev/92-fpga.rules
index a5cf00a..308bfd3 100644
--- a/fpga/usb_jtag/udev/92-fpga.rules
+++ b/fpga/usb_jtag/udev/92-fpga.rules
@@ -1,3 +1,3 @@
SUBSYSTEM=="usb" ATTR{idVendor}=="1443" ATTR{idProduct}="0005" RUN+="/usr/local/lib/udev/fpga-nexys2.sh %k"
-SUBSYSTEM=="usb" ATTR{idVendor}=="16c0" ATTR{idProduct}="06ad" SYMLINK+="nexys2"
+SUBSYSTEM=="usb" ATTR{idVendor}=="16c0" ATTR{idProduct}="06ad" SYMLINK+="nexys2" MODE="0666"
hooks/post-receive
--
krobot-resources
|
|
From: Xavier L. <Sup...@us...> - 2010-01-16 16:32:46
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 39a9f01750a2a5da1e6b085fcac4fb4a4d12b509 (commit)
from 314f306d809db32407da4872556f04e3f31a377c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 39a9f01750a2a5da1e6b085fcac4fb4a4d12b509
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 17:32:03 2010 +0100
Modification des coefficients de division pour prendre en compte l'horloge
réelle de la carte
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/div_clk.vhd b/fpga/components/div_clk.vhd
index 355d385..59d09e4 100644
--- a/fpga/components/div_clk.vhd
+++ b/fpga/components/div_clk.vhd
@@ -19,25 +19,25 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div_clk is
Port (clkin : in STD_LOGIC;
reset : in STD_LOGIC;
- clkout1 : out STD_LOGIC; -- 1.19 Hz
- clkout2 : out STD_LOGIC; -- 153 Hz
- clkout3 : out STD_LOGIC; -- 78 kHz
- clkout4 : out STD_LOGIC); -- 1.25 MHz
+ clkout1 : out STD_LOGIC; -- 1.49 Hz
+ clkout2 : out STD_LOGIC; -- 763 Hz
+ clkout3 : out STD_LOGIC; -- 98 kHz
+ clkout4 : out STD_LOGIC); -- 1.56 MHz
end div_clk;
architecture Behavioral of div_clk is
- signal compt : std_logic_vector(23 downto 0);
+ signal compt : std_logic_vector(26 downto 0);
begin
process (clkin, reset)
begin
if (reset = '1') then
- compt <= "000000000000000000000000";
+ compt <= "000000000000000000000000000";
elsif (clkin'event and clkin = '1') then
compt <= compt + 1;
end if;
end process;
- clkout1 <= compt(23);
- clkout2 <= compt(16);
- clkout3 <= compt(7);
- clkout4 <= compt(4);
+ clkout1 <= compt(26);
+ clkout2 <= compt(17);
+ clkout3 <= compt(11);
+ clkout4 <= compt(6);
end Behavioral;
hooks/post-receive
--
krobot-resources
|
|
From: Xavier L. <Sup...@us...> - 2010-01-16 16:31:01
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "krobot-resources".
The branch, master has been updated
via 314f306d809db32407da4872556f04e3f31a377c (commit)
from 42a764ec6bb089a794a4a4cd2a88e8af5ca67fb6 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 314f306d809db32407da4872556f04e3f31a377c
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 17:30:34 2010 +0100
Première version du driver pour l'afficheur 7 segments
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/driver_7seg.vhd b/fpga/components/driver_7seg.vhd
new file mode 100644
index 0000000..4f1a551
--- /dev/null
+++ b/fpga/components/driver_7seg.vhd
@@ -0,0 +1,125 @@
+----------------------------------------------------------------------------------
+-- Create Date: 15/01/2010
+-- Module Name: driver_7seg
+-- Authors : X. Lagorce
+-- Description: Driver for an output composed of four 7 segments displays
+-- multiplexed
+--
+-- Dependencies: mux8_4
+--
+-- Revision:
+-- Revision 0.1 : First implementation
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity driver_7seg is
+ port( clk : in STD_LOGIC; -- refresh clock
+ data : in STD_LOGIC_VECTOR(7 downto 0); -- segments + decimal point
+ add : in STD_LOGIC_VECTOR(1 downto 0); -- segment address
+ dok : in STD_LOGIC; -- data OK
+ oe : in STD_LOGIC; -- output enable
+ a : out STD_LOGIC; -- segments
+ b : out STD_LOGIC; -- ...
+ c : out STD_LOGIC; -- ...
+ d : out STD_LOGIC; -- ...
+ e : out STD_LOGIC; -- ...
+ f : out STD_LOGIC; -- ...
+ g : out STD_LOGIC; -- ...
+ dp : out STD_LOGIC; -- decimal point
+ an0 : out STD_LOGIC; -- number selection
+ an1 : out STD_LOGIC; -- ...
+ an2 : out STD_LOGIC; -- ...
+ an3 : out STD_LOGIC -- ...
+ );
+end driver_7seg;
+
+architecture Behavioral of driver_7seg is
+-- Components declarations
+component mux8_4 is
+ Port ( c : in STD_LOGIC_VECTOR (1 downto 0);
+ e0 : in STD_LOGIC_VECTOR (7 downto 0);
+ e1 : in STD_LOGIC_VECTOR (7 downto 0);
+ e2 : in STD_LOGIC_VECTOR (7 downto 0);
+ e3 : in STD_LOGIC_VECTOR (7 downto 0);
+ s : out STD_LOGIC_VECTOR (7 downto 0));
+end component;
+for all : mux8_4 use entity work.mux8_4(Behavioral);
+-- Signals declarations
+signal val1 : std_logic_vector(7 downto 0);
+signal val2 : std_logic_vector(7 downto 0);
+signal val3 : std_logic_vector(7 downto 0);
+signal val4 : std_logic_vector(7 downto 0);
+signal display_state : std_logic_vector(1 downto 0);
+signal output : std_logic_vector(7 downto 0);
+-- Description
+begin
+ -- Multiplex to link the internal memories to the display
+ display_mux : mux8_4 port map(display_state, val1, val2, val3, val4, output);
+ -- Link output of the multiplexer to the output lines going to the display
+ a <= output(0);
+ b <= output(1);
+ c <= output(2);
+ d <= output(3);
+ e <= output(4);
+ f <= output(5);
+ g <= output(6);
+ dp <= output(7);
+ -- Display scanning
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (oe = '1') then
+ case display_state is
+ when "00" => display_state <= "01";
+ an0 <= '1';
+ an1 <= '0';
+ an2 <= '1';
+ an3 <= '1';
+ when "01" => display_state <= "10";
+ an0 <= '1';
+ an1 <= '1';
+ an2 <= '0';
+ an3 <= '1';
+ when "10" => display_state <= "11";
+ an0 <= '1';
+ an1 <= '1';
+ an2 <= '1';
+ an3 <= '0';
+ when "11" => display_state <= "00";
+ an0 <= '0';
+ an1 <= '1';
+ an2 <= '1';
+ an3 <= '1';
+ when others => display_state <= "00";
+ an0 <= '0';
+ an1 <= '1';
+ an2 <= '1';
+ an3 <= '1';
+ end case;
+ else
+ an0 <= '1';
+ an1 <= '1';
+ an2 <= '1';
+ an3 <= '1';
+ end if;
+ end if;
+ end process;
+ -- Manage the loading of the internal memory
+ process (dok)
+ begin
+ if (dok'event and dok='1') then
+ case add is
+ when "00" => val1 <= data;
+ when "01" => val2 <= data;
+ when "10" => val3 <= data;
+ when "11" => val4 <= data;
+ when others => null;
+ end case;
+ end if;
+ end process;
+end Behavioral;
hooks/post-receive
--
krobot-resources
|
|
From: Xavier L. <Sup...@us...> - 2010-01-15 23:40:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "UNNAMED PROJECT".
The branch, master has been updated
via 42a764ec6bb089a794a4a4cd2a88e8af5ca67fb6 (commit)
from 09d628ca3f2eea7918516539737a9f3e0fae073c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 42a764ec6bb089a794a4a4cd2a88e8af5ca67fb6
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 00:40:24 2010 +0100
Ajout d'un decodeur BCD vers 7 segments (+ point décimal)
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/decoder_7seg.vhd b/fpga/components/decoder_7seg.vhd
new file mode 100644
index 0000000..dcf698b
--- /dev/null
+++ b/fpga/components/decoder_7seg.vhd
@@ -0,0 +1,162 @@
+----------------------------------------------------------------------------------
+-- Create Date: 15/01/2010
+-- Module Name: decoder_7seg
+-- Authors : X. Lagorce
+-- Description: Decodes a BCD value into its representation on a 7 segments
+-- diplay
+--
+-- Dependencies: /
+--
+-- Revision:
+-- Revision 0.1 : First implementation
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity decoder_7seg is
+ port(val : in std_logic_vector(3 downto 0);
+ pti : in std_logic;
+ a : out std_logic;
+ b : out std_logic;
+ c : out std_logic;
+ d : out std_logic;
+ e : out std_logic;
+ f : out std_logic;
+ g : out std_logic;
+ pt : out std_logic
+ );
+end decoder_7seg;
+
+architecture hexa_dec of decoder_7seg is
+begin
+ process(val, pti)
+ begin
+ case val is
+ when "0000" => a <= '1'; -- 0
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '0';
+ when "0001" => a <= '0'; -- 1
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "0010" => a <= '1'; -- 2
+ b <= '1';
+ c <= '0';
+ d <= '1';
+ e <= '1';
+ f <= '0';
+ g <= '1';
+ when "0011" => a <= '1'; -- 3
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '0';
+ f <= '0';
+ g <= '1';
+ when "0100" => a <= '0'; -- 4
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '1';
+ g <= '1';
+ when "0101" => a <= '1'; -- 5
+ b <= '0';
+ c <= '1';
+ d <= '1';
+ e <= '0';
+ f <= '1';
+ g <= '1';
+ when "0110" => a <= '1'; -- 6
+ b <= '0';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '1';
+ when "0111" => a <= '1'; -- 7
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ when "1000" => a <= '1'; -- 8
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '1';
+ when "1001" => a <= '1'; -- 9
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '0';
+ f <= '1';
+ g <= '1';
+ when "1010" => a <= '1'; -- A
+ b <= '1';
+ c <= '1';
+ d <= '0';
+ e <= '1';
+ f <= '1';
+ g <= '1';
+ when "1011" => a <= '0'; -- B
+ b <= '0';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '1';
+ when "1100" => a <= '1'; -- C
+ b <= '0';
+ c <= '0';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '0';
+ when "1101" => a <= '0'; -- D
+ b <= '1';
+ c <= '1';
+ d <= '1';
+ e <= '1';
+ f <= '0';
+ g <= '1';
+ when "1110" => a <= '1'; -- E
+ b <= '0';
+ c <= '0';
+ d <= '1';
+ e <= '1';
+ f <= '1';
+ g <= '1';
+ when "1111" => a <= '1'; -- F
+ b <= '0';
+ c <= '0';
+ d <= '0';
+ e <= '1';
+ f <= '1';
+ g <= '1';
+ when others => a <= '0'; -- shouldn't happen
+ b <= '0';
+ c <= '0';
+ d <= '0';
+ e <= '0';
+ f <= '0';
+ g <= '0';
+ end case;
+ end process;
+ pt <= pti;
+end hexa_dec;
hooks/post-receive
--
UNNAMED PROJECT
|
|
From: Xavier L. <Sup...@us...> - 2010-01-15 23:11:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "UNNAMED PROJECT".
The branch, master has been updated
via 09d628ca3f2eea7918516539737a9f3e0fae073c (commit)
from 9eb0bf1daac3d4a94cf8c181825e4528c49ab713 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 09d628ca3f2eea7918516539737a9f3e0fae073c
Author: Xavier Lagorce <Xav...@cr...>
Date: Sat Jan 16 00:11:26 2010 +0100
Ajout d'un multiplexeur 4 entrées de 8 bits
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/mux8_4.vhd b/fpga/components/mux8_4.vhd
new file mode 100644
index 0000000..3dad34d
--- /dev/null
+++ b/fpga/components/mux8_4.vhd
@@ -0,0 +1,41 @@
+----------------------------------------------------------------------------------
+-- Create Date: 15/01/2010
+-- Module Name: mux8_4
+-- Authors : X. Lagorce
+-- Description: multiplexer 4 inputs of 8 bits to one output
+--
+-- Dependencies: /
+--
+-- Revision:
+-- Revision 0.1 : First implementation
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity mux8_4 is
+ Port ( c : in STD_LOGIC_VECTOR (1 downto 0);
+ e0 : in STD_LOGIC_VECTOR (7 downto 0);
+ e1 : in STD_LOGIC_VECTOR (7 downto 0);
+ e2 : in STD_LOGIC_VECTOR (7 downto 0);
+ e3 : in STD_LOGIC_VECTOR (7 downto 0);
+ s : out STD_LOGIC_VECTOR (7 downto 0));
+end mux8_4;
+
+architecture Behavioral of mux8_4 is
+begin
+ process(e0, e1, e2, e3, c)
+ begin
+ case c is
+ when "00" => s <= e0;
+ when "01" => s <= e1;
+ when "10" => s <= e2;
+ when "11" => s <= e3;
+ when others => s <= "00000000"; -- shouldn't happen
+ end case;
+ end process;
+end Behavioral;
+
hooks/post-receive
--
UNNAMED PROJECT
|
|
From: Xavier L. <Sup...@us...> - 2010-01-15 22:25:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "UNNAMED PROJECT".
The branch, master has been updated
via 9eb0bf1daac3d4a94cf8c181825e4528c49ab713 (commit)
from dd33d9d9d64f8d99756af9ec22019c996a2dcbc4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9eb0bf1daac3d4a94cf8c181825e4528c49ab713
Author: Xavier Lagorce <Xav...@cr...>
Date: Fri Jan 15 23:25:23 2010 +0100
Correction d'une erreur et accélération de l'horloge pour le driver PS2
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/div_clk.vhd b/fpga/components/div_clk.vhd
index ac8d65a..355d385 100644
--- a/fpga/components/div_clk.vhd
+++ b/fpga/components/div_clk.vhd
@@ -21,22 +21,23 @@ entity div_clk is
reset : in STD_LOGIC;
clkout1 : out STD_LOGIC; -- 1.19 Hz
clkout2 : out STD_LOGIC; -- 153 Hz
- clkout3 : out STD_LOGIC; -- 19.5 kHz
+ clkout3 : out STD_LOGIC; -- 78 kHz
clkout4 : out STD_LOGIC); -- 1.25 MHz
+end div_clk;
- architecture Behavioral of div_clk is
- signal compt : std_logic_vector(23 downto 0);
+architecture Behavioral of div_clk is
+ signal compt : std_logic_vector(23 downto 0);
+begin
+ process (clkin, reset)
begin
- process (clkin, reset)
- begin
- if (reset = '1') then
- compt <= "000000000000000000000000";
- elsif (clkin'event and clkin = '1') then
- compt <= compt + 1;
- end if;
- end process;
- clkout1 <= compt(23);
- clkout2 <= compt(16);
- clkout3 <= compt(9);
- clkout4 <= compt(4);
- end Behavioral;
+ if (reset = '1') then
+ compt <= "000000000000000000000000";
+ elsif (clkin'event and clkin = '1') then
+ compt <= compt + 1;
+ end if;
+ end process;
+ clkout1 <= compt(23);
+ clkout2 <= compt(16);
+ clkout3 <= compt(7);
+ clkout4 <= compt(4);
+end Behavioral;
hooks/post-receive
--
UNNAMED PROJECT
|
|
From: Xavier L. <Sup...@us...> - 2010-01-15 22:14:23
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "UNNAMED PROJECT".
The branch, master has been updated
via dd33d9d9d64f8d99756af9ec22019c996a2dcbc4 (commit)
from acdc9b71a05928bcdd16a71b9ccf4ec5b785c41d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit dd33d9d9d64f8d99756af9ec22019c996a2dcbc4
Author: Xavier Lagorce <Xav...@cr...>
Date: Fri Jan 15 23:14:04 2010 +0100
Ajout d'un composant diviseur d'horloge
-----------------------------------------------------------------------
Changes:
diff --git a/fpga/components/div_clk.vhd b/fpga/components/div_clk.vhd
new file mode 100644
index 0000000..ac8d65a
--- /dev/null
+++ b/fpga/components/div_clk.vhd
@@ -0,0 +1,42 @@
+----------------------------------------------------------------------------------
+-- Create Date: 15/01/2010
+-- Module Name: div_clk - Behavioral
+-- Authors : X. Lagorce
+-- Description: Clock divider with multiple outputs
+--
+-- Dependencies: /
+--
+-- Revision:
+-- Revision 0.1 : Simple implementation
+-- Additional Comments: This should use integrated clock circuits
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity div_clk is
+ Port (clkin : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ clkout1 : out STD_LOGIC; -- 1.19 Hz
+ clkout2 : out STD_LOGIC; -- 153 Hz
+ clkout3 : out STD_LOGIC; -- 19.5 kHz
+ clkout4 : out STD_LOGIC); -- 1.25 MHz
+
+ architecture Behavioral of div_clk is
+ signal compt : std_logic_vector(23 downto 0);
+ begin
+ process (clkin, reset)
+ begin
+ if (reset = '1') then
+ compt <= "000000000000000000000000";
+ elsif (clkin'event and clkin = '1') then
+ compt <= compt + 1;
+ end if;
+ end process;
+ clkout1 <= compt(23);
+ clkout2 <= compt(16);
+ clkout3 <= compt(9);
+ clkout4 <= compt(4);
+ end Behavioral;
hooks/post-receive
--
UNNAMED PROJECT
|