#10 MOVD/MOVQ in 64-bit (was: Another MMX code problem)

[Anonymous]

Hi Japheth,

This is a minor MMX code problem happening in a 64-bit code segment (use64).
1. "movq rcx,mm0" generates "Invalid Instruction operands"
2. "movd rcx,mm0" generates code for item 1.

The transfer between mm0 and rcx is a 64-bit move and would be better to use
mnemonic "MOVQ" instead of "MOVD" as Intel's Doc & NASM did.

Thanks & Regards

[Nobody/Anonymous]

The problem is that Masm (ML64) also prefers to use the MOVD opcode if one of the operands is a GPR. The error msg is different and somewhat strange ("word register cannot be first operand"), but this is a minor issue. IIRC this syntax is taken from the original AMD x64 docs.

Since I want JWasm to stay as Masm compatible as possible, there's no good reason to switch the current behavior IMO.

japheth

[Diederik Huys]

I don't agree with the previous comment.
First it is not consistent: MASM chooses to optimize LEA <reg1>,[<reg2>] to MOV <reg1>,<reg2> ; yet jwasm chooses to leave the decision up to the programmer.

The same applies in this case: if the CPU supports it and the code is reasonable, then it should be possible to code it. Allowing both instructions will not break compatibility.