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[Jnode-svn-commits] SF.net SVN: jnode: [3177] trunk/net/src/driver/org/jnode/driver/net
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From: <ls...@us...> - 2007-05-02 20:43:28
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Revision: 3177
http://jnode.svn.sourceforge.net/jnode/?rev=3177&view=rev
Author: lsantha
Date: 2007-05-02 13:43:25 -0700 (Wed, 02 May 2007)
Log Message:
-----------
via-rhine nic driver, initial commit.
Added Paths:
-----------
trunk/net/src/driver/org/jnode/driver/net/via_rhine/
trunk/net/src/driver/org/jnode/driver/net/via_rhine/ViaRhineConstants.java
Added: trunk/net/src/driver/org/jnode/driver/net/via_rhine/ViaRhineConstants.java
===================================================================
--- trunk/net/src/driver/org/jnode/driver/net/via_rhine/ViaRhineConstants.java (rev 0)
+++ trunk/net/src/driver/org/jnode/driver/net/via_rhine/ViaRhineConstants.java 2007-05-02 20:43:25 UTC (rev 3177)
@@ -0,0 +1,474 @@
+/*
+ * $Id$
+ */
+package org.jnode.driver.net.via_rhine;
+
+/**
+ * @author Levente S\xE1ntha
+ */
+public interface ViaRhineConstants {
+ byte ioaddr = 0;
+ byte byPAR0 = ioaddr;
+ byte byRCR = ioaddr + 6;
+ byte byTCR = ioaddr + 7;
+ byte byCR0 = ioaddr + 8;
+ byte byCR1 = ioaddr + 9;
+ byte byISR0 = ioaddr + 0x0c;
+ byte byISR1 = ioaddr + 0x0d;
+ byte byIMR0 = ioaddr + 0x0e;
+ byte byIMR1 = ioaddr + 0x0f;
+ byte byMAR0 = ioaddr + 0x10;
+ byte byMAR1 = ioaddr + 0x11;
+ byte byMAR2 = ioaddr + 0x12;
+ byte byMAR3 = ioaddr + 0x13;
+ byte byMAR4 = ioaddr + 0x14;
+ byte byMAR5 = ioaddr + 0x15;
+ byte byMAR6 = ioaddr + 0x16;
+ byte byMAR7 = ioaddr + 0x17;
+ int dwCurrentRxDescAddr = ioaddr + 0x18;
+ int dwCurrentTxDescAddr = ioaddr + 0x1c;
+ int dwCurrentRDSE0 = ioaddr + 0x20;
+ int dwCurrentRDSE1 = ioaddr + 0x24;
+ int dwCurrentRDSE2 = ioaddr + 0x28;
+ int dwCurrentRDSE3 = ioaddr + 0x2c;
+ int dwNextRDSE0 = ioaddr + 0x30;
+ int dwNextRDSE1 = ioaddr + 0x34;
+ int dwNextRDSE2 = ioaddr + 0x38;
+ int dwNextRDSE3 = ioaddr + 0x3c;
+ int dwCurrentTDSE0 = ioaddr + 0x40;
+ int dwCurrentTDSE1 = ioaddr + 0x44;
+ int dwCurrentTDSE2 = ioaddr + 0x48;
+ int dwCurrentTDSE3 = ioaddr + 0x4c;
+ int dwNextTDSE0 = ioaddr + 0x50;
+ int dwNextTDSE1 = ioaddr + 0x54;
+ int dwNextTDSE2 = ioaddr + 0x58;
+ int dwNextTDSE3 = ioaddr + 0x5c;
+ int dwCurrRxDMAPtr = ioaddr + 0x60;
+ int dwCurrTxDMAPtr = ioaddr + 0x64;
+ int byMPHY = ioaddr + 0x6c;
+ int byMIISR = ioaddr + 0x6d;
+ int byBCR0 = ioaddr + 0x6e;
+ int byBCR1 = ioaddr + 0x6f;
+ int byMIICR = ioaddr + 0x70;
+ int byMIIAD = ioaddr + 0x71;
+ int wMIIDATA = ioaddr + 0x72;
+ int byEECSR = ioaddr + 0x74;
+ int byTEST = ioaddr + 0x75;
+ int byGPIO = ioaddr + 0x76;
+ int byCFGA = ioaddr + 0x78;
+ int byCFGB = ioaddr + 0x79;
+ int byCFGC = ioaddr + 0x7a;
+ int byCFGD = ioaddr + 0x7b;
+ int wTallyCntMPA = ioaddr + 0x7c;
+ int wTallyCntCRC = ioaddr + 0x7d;
+ int bySTICKHW = ioaddr + 0x83;
+ int byWOLcrClr = ioaddr + 0xA4;
+ int byWOLcgClr = ioaddr + 0xA7;
+ int byPwrcsrClr = ioaddr + 0xAC;
+
+/*--------------------- Exioaddr Definitions -------------------------*/
+
+/*
+ * Bits in the RCR register
+ */
+
+ int RCR_RRFT2 = 0x80;
+ int RCR_RRFT1 = 0x40;
+ int RCR_RRFT0 = 0x20;
+ int RCR_PROM = 0x10;
+ int RCR_AB = 0x08;
+ int RCR_AM = 0x04;
+ int RCR_AR = 0x02;
+ int RCR_SEP = 0x01;
+
+/*
+ * Bits in the TCR register
+ */
+
+ int TCR_RTSF = 0x80;
+ int TCR_RTFT1 = 0x40;
+ int TCR_RTFT0 = 0x20;
+ int TCR_OFSET = 0x08;
+ int TCR_LB1 = 0x04; /* loopback[1] */
+ int TCR_LB0 = 0x02; /* loopback[0] */
+
+/*
+ * Bits in the CR0 register
+ */
+
+ int CR0_RDMD = 0x40; /* rx descriptor polling demand */
+ int CR0_TDMD = 0x20; /* tx descriptor polling demand */
+ int CR0_TXON = 0x10;
+ int CR0_RXON = 0x08;
+ int CR0_STOP = 0x04; /* stop NIC, default = 1 */
+ int CR0_STRT = 0x02; /* start NIC */
+ int CR0_INIT = 0x01; /* start init process */
+
+/*
+* Bits in the CR1 register
+*/
+
+ int CR1_SFRST = 0x80 /* software reset */;
+ int CR1_RDMD1 = 0x40 /* RDMD1 */;
+ int CR1_TDMD1 = 0x20 /* TDMD1 */;
+ int CR1_KEYPAG = 0x10 /* turn on par/key */;
+ int CR1_DPOLL = 0x08 /* disable rx/tx auto polling */;
+ int CR1_FDX = 0x04 /* full duplex mode */;
+ int CR1_ETEN = 0x02 /* early tx mode */;
+ int CR1_EREN = 0x01 /* early rx mode */;
+
+/*
+ * Bits in the CR register
+ */
+
+ int CR_RDMD = 0x0040 /* rx descriptor polling demand */;
+ int CR_TDMD = 0x0020 /* tx descriptor polling demand */;
+ int CR_TXON = 0x0010;
+ int CR_RXON = 0x0008;
+ int CR_STOP = 0x0004 /* stop NIC, default = 1 */;
+ int CR_STRT = 0x0002 /* start NIC */;
+ int CR_INIT = 0x0001 /* start init process */;
+ int CR_SFRST = 0x8000 /* software reset */;
+ int CR_RDMD1 = 0x4000 /* RDMD1 */;
+ int CR_TDMD1 = 0x2000 /* TDMD1 */;
+ int CR_KEYPAG = 0x1000 /* turn on par/key */;
+ int CR_DPOLL = 0x0800 /* disable rx/tx auto polling */;
+ int CR_FDX = 0x0400 /* full duplex mode */;
+ int CR_ETEN = 0x0200 /* early tx mode */;
+ int CR_EREN = 0x0100 /* early rx mode */;
+
+/*
+ * Bits in the IMR0 register
+ */
+
+ int IMR0_CNTM = 0x80;
+ int IMR0_BEM = 0x40;
+ int IMR0_RUM = 0x20;
+ int IMR0_TUM = 0x10;
+ int IMR0_TXEM = 0x08;
+ int IMR0_RXEM = 0x04;
+ int IMR0_PTXM = 0x02;
+ int IMR0_PRXM = 0x01;
+
+/* define imrshadow */
+
+ int IMRShadow = 0x5AFF;
+
+/*
+ * Bits in the IMR1 register
+ */
+
+ int IMR1_INITM = 0x80;
+ int IMR1_SRCM = 0x40;
+ int IMR1_NBFM = 0x10;
+ int IMR1_PRAIM = 0x08;
+ int IMR1_RES0M = 0x04;
+ int IMR1_ETM = 0x02;
+ int IMR1_ERM = 0x01;
+
+/*
+ * Bits in the ISR register
+ */
+
+ int ISR_INITI = 0x8000;
+ int ISR_SRCI = 0x4000;
+ int ISR_ABTI = 0x2000;
+ int ISR_NORBF = 0x1000;
+ int ISR_PKTRA = 0x0800;
+ int ISR_RES0 = 0x0400;
+ int ISR_ETI = 0x0200;
+ int ISR_ERI = 0x0100;
+ int ISR_CNT = 0x0080;
+ int ISR_BE = 0x0040;
+ int ISR_RU = 0x0020;
+ int ISR_TU = 0x0010;
+ int ISR_TXE = 0x0008;
+ int ISR_RXE = 0x0004;
+ int ISR_PTX = 0x0002;
+ int ISR_PRX = 0x0001;
+
+/*
+ * Bits in the ISR0 register;
+ */
+
+ int ISR0_CNT = 0x80;
+ int ISR0_BE = 0x40;
+ int ISR0_RU = 0x20;
+ int ISR0_TU = 0x10;
+ int ISR0_TXE = 0x08;
+ int ISR0_RXE = 0x04;
+ int ISR0_PTX = 0x02;
+ int ISR0_PRX = 0x01;
+
+/*
+ * Bits in the ISR1 register
+ */
+
+ int ISR1_INITI = 0x80;
+ int ISR1_SRCI = 0x40;
+ int ISR1_NORBF = 0x10;
+ int ISR1_PKTRA = 0x08;
+ int ISR1_ETI = 0x02;
+ int ISR1_ERI = 0x01;
+
+/* ISR ABNORMAL CONDITION */
+
+ int ISR_ABNORMAL = ISR_BE + ISR_RU + ISR_TU + ISR_CNT + ISR_NORBF + ISR_PKTRA;
+
+/*
+ * Bits in the MIISR register;
+ */
+
+ int MIISR_MIIERR = 0x08;
+ int MIISR_MRERR = 0x04;
+ int MIISR_LNKFL = 0x02;
+ int MIISR_SPEED = 0x01;
+
+/*
+ * Bits in the MIICR register;
+ */
+
+ int MIICR_MAUTO = 0x80;
+ int MIICR_RCMD = 0x40;
+ int MIICR_WCMD = 0x20;
+ int MIICR_MDPM = 0x10;
+ int MIICR_MOUT = 0x08;
+ int MIICR_MDO = 0x04;
+ int MIICR_MDI = 0x02;
+ int MIICR_MDC = 0x01;
+
+/*
+ * Bits in the EECSR register;
+ */
+
+ int EECSR_EEPR = 0x80 /* eeprom programed status, 73h means programed */;
+ int EECSR_EMBP = 0x40 /* eeprom embeded programming */;
+ int EECSR_AUTOLD = 0x20 /* eeprom content reload */;
+ int EECSR_DPM = 0x10 /* eeprom direct programming */;
+ int EECSR_CS = 0x08 /* eeprom CS pin */;
+ int EECSR_SK = 0x04 /* eeprom SK pin */;
+ int EECSR_DI = 0x02 /* eeprom DI pin */;
+ int EECSR_DO = 0x01 /* eeprom DO pin */;
+
+/*
+ * Bits in the BCR0 register;
+ */
+
+ int BCR0_CRFT2 = 0x20;
+ int BCR0_CRFT1 = 0x10;
+ int BCR0_CRFT0 = 0x08;
+ int BCR0_DMAL2 = 0x04;
+ int BCR0_DMAL1 = 0x02;
+ int BCR0_DMAL0 = 0x01;
+
+ /*
+ * Bits in the BCR1 register;
+ */
+ int BCR1_CTSF = 0x20;
+ int BCR1_CTFT1 = 0x10;
+ int BCR1_CTFT0 = 0x08;
+ int BCR1_POT2 = 0x04;
+ int BCR1_POT1 = 0x02;
+ int BCR1_POT0 = 0x01;
+
+ /*
+ * Bits in the CFGA register;
+ */
+ int CFGA_EELOAD = 0x80 /* enable eeprom embeded and direct programming */;
+ int CFGA_JUMPER = 0x40;
+ int CFGA_MTGPIO = 0x08;
+ int CFGA_T10EN = 0x02;
+ int CFGA_AUTO = 0x01;
+
+ /*
+ * Bits in the CFGB register;
+ */
+ int CFGB_PD = 0x80;
+ int CFGB_POLEN = 0x02;
+ int CFGB_LNKEN = 0x01;
+
+ /*
+ * Bits in the CFGC register;
+ */
+ int CFGC_M10TIO = 0x80;
+ int CFGC_M10POL = 0x40;
+ int CFGC_PHY1 = 0x20;
+ int CFGC_PHY0 = 0x10;
+ int CFGC_BTSEL = 0x08;
+ int CFGC_BPS2 = 0x04 /* bootrom select[2] */;
+ int CFGC_BPS1 = 0x02 /* bootrom select[1] */;
+ int CFGC_BPS0 = 0x01 /* bootrom select[0] */;
+
+ /*
+ * Bits in the CFGD register;
+ */
+ int CFGD_GPIOEN = 0x80;
+ int CFGD_DIAG = 0x40;
+ int CFGD_MAGIC = 0x10;
+ int CFGD_RANDOM = 0x08;
+ int CFGD_CFDX = 0x04;
+ int CFGD_CEREN = 0x02;
+ int CFGD_CETEN = 0x01;
+
+ /* Bits in RSR */
+ int RSR_RERR = 0x00000001;
+ int RSR_CRC = 0x00000002;
+ int RSR_FAE = 0x00000004;
+ int RSR_FOV = 0x00000008;
+ int RSR_LONG = 0x00000010;
+ int RSR_RUNT = 0x00000020;
+ int RSR_SERR = 0x00000040;
+ int RSR_BUFF = 0x00000080;
+ int RSR_EDP = 0x00000100;
+ int RSR_STP = 0x00000200;
+ int RSR_CHN = 0x00000400;
+ int RSR_PHY = 0x00000800;
+ int RSR_BAR = 0x00001000;
+ int RSR_MAR = 0x00002000;
+ int RSR_RXOK = 0x00008000;
+ int RSR_ABNORMAL = RSR_RERR + RSR_LONG + RSR_RUNT;
+
+ /* Bits in TSR */
+ int TSR_NCR0 = 0x00000001;
+ int TSR_NCR1 = 0x00000002;
+ int TSR_NCR2 = 0x00000004;
+ int TSR_NCR3 = 0x00000008;
+ int TSR_COLS = 0x00000010;
+ int TSR_CDH = 0x00000080;
+ int TSR_ABT = 0x00000100;
+ int TSR_OWC = 0x00000200;
+ int TSR_CRS = 0x00000400;
+ int TSR_UDF = 0x00000800;
+ int TSR_TBUFF = 0x00001000;
+ int TSR_SERR = 0x00002000;
+ int TSR_JAB = 0x00004000;
+ int TSR_TERR = 0x00008000;
+ int TSR_ABNORMAL = TSR_TERR + TSR_OWC + TSR_ABT + TSR_JAB + TSR_CRS;
+ int TSR_OWN_BIT = 0x80000000;
+
+ int CB_DELAY_LOOP_WAIT = 10; /* 10ms */
+
+ /* enabled mask value of irq */
+ int W_IMR_MASK_VALUE = 0x1BFF; /* initial value of IMR */
+
+ /* Ethernet address filter type */
+ int PKT_TYPE_DIRECTED = 0x0001; /* obsolete, directed address is always accepted */
+ int PKT_TYPE_MULTICAST = 0x0002;
+ int PKT_TYPE_ALL_MULTICAST = 0x0004;
+ int PKT_TYPE_BROADCAST = 0x0008;
+ int PKT_TYPE_PROMISCUOUS = 0x0020;
+ int PKT_TYPE_LONG = 0x2000;
+ int PKT_TYPE_RUNT = 0x4000;
+ int PKT_TYPE_ERROR = 0x8000; /* accept error packets, e.g. CRC error */
+
+ /* Loopback mode */
+ int NIC_LB_NONE = 0x00;
+ int NIC_LB_INTERNAL = 0x01;
+ int NIC_LB_PHY = 0x02; /* MII or Internal-10BaseT loopback */
+
+ int TX_RING_SIZE = 2;
+ int RX_RING_SIZE = 2;
+ int PKT_BUF_SZ = 1536; /* Size of each temporary Rx buffer. */
+
+ int PCI_REG_MODE3 = 0x53;
+ int MODE3_MIION = 0x04; /* in PCI_REG_MOD3 OF PCI space */
+
+/* Offsets to the device registers. */
+ /*
+enum register_offsets {
+ StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
+ IntrStatus=0x0C, IntrEnable=0x0E,
+ MulticastFilter0=0x10, MulticastFilter1=0x14,
+ RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
+ MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
+ MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
+ ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
+ RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
+ StickyHW=0x83, IntrStatus2=0x84, WOLcrClr=0xA4, WOLcgClr=0xA7,
+ PwrcsrClr=0xAC,
+};
+*/
+
+/* Offsets to the device registers. */
+ int StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
+ IntrStatus=0x0C, IntrEnable=0x0E,
+ MulticastFilter0=0x10, MulticastFilter1=0x14,
+ RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
+ MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
+ MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
+ ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
+ RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
+ StickyHW=0x83, IntrStatus2=0x84, WOLcrClr=0xA4, WOLcgClr=0xA7,
+ PwrcsrClr=0xAC;
+
+
+/* Bits in the interrupt status/mask registers. */
+ /*
+enum intr_status_bits {
+ IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
+ IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
+ IntrPCIErr=0x0040,
+ IntrStatsMax=0x0080, IntrRxEarly=0x0100,
+ IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
+ IntrTxAborted=0x2000, IntrLinkChange=0x4000,
+ IntrRxWakeUp=0x8000,
+ IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
+ IntrTxDescRace=0x080000, // mapped from IntrStatus2
+ IntrTxErrSummary=0x082218,
+};
+/* Bits in the interrupt status/mask registers. */
+
+ int IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
+ IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
+ IntrPCIErr=0x0040,
+ IntrStatsMax=0x0080, IntrRxEarly=0x0100,
+ IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
+ IntrTxAborted=0x2000, IntrLinkChange=0x4000,
+ IntrRxWakeUp=0x8000,
+ IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
+ IntrTxDescRace=0x080000, // mapped from IntrStatus2
+ IntrTxErrSummary=0x082218;
+
+
+
+//#define DEFAULT_INTR (IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | \
+// IntrRxDropped | IntrRxNoBuf)
+
+ int DEFAULT_INTR = IntrRxDone | IntrRxErr | IntrRxEmpty|
+ IntrRxOverflow | IntrRxDropped | IntrRxNoBuf;
+
+//enum rhine_revs {
+// int VT86C100A = 0x00;
+// int VTunknown0 = 0x20;
+// int VT6102 = 0x40;
+// int VT8231 = 0x50; /* Integrated MAC */
+// int VT8233 = 0x60; /* Integrated MAC */
+// int VT8235 = 0x74; /* Integrated MAC */
+// int VT8237 = 0x78; /* Integrated MAC */
+// int VTunknown1 = 0x7C;
+// int VT6105 = 0x80;
+// int VT6105_B0 = 0x83;
+// int VT6105L = 0x8A;
+// int VT6107 = 0x8C;
+// int VTunknown2 = 0x8E;
+// int VT6105M = 0x90;
+//};
+
+//enum rhine_revs {
+ int VT86C100A = 0x00;
+ int VTunknown0 = 0x20;
+ int VT6102 = 0x40;
+ int VT8231 = 0x50; /* Integrated MAC */
+ int VT8233 = 0x60; /* Integrated MAC */
+ int VT8235 = 0x74; /* Integrated MAC */
+ int VT8237 = 0x78; /* Integrated MAC */
+ int VTunknown1 = 0x7C;
+ int VT6105 = 0x80;
+ int VT6105_B0 = 0x83;
+ int VT6105L = 0x8A;
+ int VT6107 = 0x8C;
+ int VTunknown2 = 0x8E;
+ int VT6105M = 0x90;
+//};
+
+}
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