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[rvm-commits] SF.net SVN: jikesrvm: [13837] rvmroot/trunk/rvm/src
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From: <cap...@us...> - 2007-10-31 10:31:10
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Revision: 13837
http://jikesrvm.svn.sourceforge.net/jikesrvm/?rev=13837&view=rev
Author: captain5050
Date: 2007-10-31 03:31:06 -0700 (Wed, 31 Oct 2007)
Log Message:
-----------
RVM-331: Support for MMX MM registers (currently disabled in the OPT compiler as they don't appear in the physical register set). This patch also does a bit to tidy how SSE operations are generated by the IA32 assembler generator script.
Modified Paths:
--------------
rvmroot/trunk/rvm/src/org/jikesrvm/compilers/baseline/ia32/VM_Compiler.java
rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_AssemblerBase.java
rvmroot/trunk/rvm/src/org/jikesrvm/ia32/VM_RegisterConstants.java
rvmroot/trunk/rvm/src-generated/ia32-assembler/VM_Assembler.in
rvmroot/trunk/rvm/src-generated/ia32-assembler/genAssembler.sh
rvmroot/trunk/rvm/src-generated/ia32-assembler-opt/GenerateAssembler.java
Modified: rvmroot/trunk/rvm/src/org/jikesrvm/compilers/baseline/ia32/VM_Compiler.java
===================================================================
--- rvmroot/trunk/rvm/src/org/jikesrvm/compilers/baseline/ia32/VM_Compiler.java 2007-10-30 05:29:14 UTC (rev 13836)
+++ rvmroot/trunk/rvm/src/org/jikesrvm/compilers/baseline/ia32/VM_Compiler.java 2007-10-31 10:31:06 UTC (rev 13837)
@@ -1156,7 +1156,7 @@
asm.emitPOP_Reg(T0); // shift amount (6 bits)
asm.emitMOVQ_Reg_RegInd(XMM1, SP); // XMM1 <- [SP]
asm.emitAND_Reg_Imm(T0, 0x3F); // mask to 6bits
- asm.emitMOVDr_Reg_Reg(XMM0, T0); // XMM0 <- T0
+ asm.emitMOVD_Reg_Reg(XMM0, T0); // XMM0 <- T0
asm.emitPSLLQ_Reg_Reg(XMM1, XMM0); // XMM1 <<= XMM0
asm.emitMOVQ_RegInd_Reg(SP, XMM1); // [SP] <- XMM1
} else {
@@ -1213,7 +1213,7 @@
asm.emitPOP_Reg(T0); // shift amount (6 bits)
asm.emitMOVQ_Reg_RegInd(XMM1, SP); // XMM1 <- [SP]
asm.emitAND_Reg_Imm(T0, 0x3F); // mask to 6bits
- asm.emitMOVDr_Reg_Reg(XMM0, T0); // XMM0 <- T0
+ asm.emitMOVD_Reg_Reg(XMM0, T0); // XMM0 <- T0
asm.emitPSRLQ_Reg_Reg(XMM1, XMM0); // XMM1 >>>= XMM0
asm.emitMOVQ_RegInd_Reg(SP, XMM1); // [SP] <- XMM1
} else {
Modified: rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_AssemblerBase.java
===================================================================
--- rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_AssemblerBase.java 2007-10-30 05:29:14 UTC (rev 13836)
+++ rvmroot/trunk/rvm/src/org/jikesrvm/compilers/opt/ia32/OPT_AssemblerBase.java 2007-10-31 10:31:06 UTC (rev 13837)
@@ -192,6 +192,10 @@
return isReg(op);
}
+ boolean isMM_Reg(OPT_Operand op) {
+ return false; // MM registers not currently supported in the OPT compiler
+ }
+
boolean isXMM_Reg(OPT_Operand op) {
return isReg(op);
}
@@ -281,6 +285,11 @@
return (FPR)getMachineRegister(op.asRegister().getRegister());
}
+ MM getMM_Reg(OPT_Operand op) {
+ VM._assert(false, "MM registers not currently supported in the opt compiler");
+ return null;
+ }
+
XMM getXMM_Reg(OPT_Operand op) {
return (XMM)getMachineRegister(op.asRegister().getRegister());
}
Modified: rvmroot/trunk/rvm/src/org/jikesrvm/ia32/VM_RegisterConstants.java
===================================================================
--- rvmroot/trunk/rvm/src/org/jikesrvm/ia32/VM_RegisterConstants.java 2007-10-30 05:29:14 UTC (rev 13836)
+++ rvmroot/trunk/rvm/src/org/jikesrvm/ia32/VM_RegisterConstants.java 2007-10-31 10:31:06 UTC (rev 13837)
@@ -103,6 +103,35 @@
return vals[num];
}
}
+ /**
+ * Representation of MMX MM registers
+ * N.B. MM and x87 FPR registers alias
+ */
+ public enum MM implements Register {
+ MM0(0), MM1(1), MM2(2), MM3(3), MM4(4), MM5(5), MM6(6), MM7(7);
+ /** Local copy of the backing array. Copied here to avoid calls to clone */
+ private static final MM[] vals = values();
+ /** Constructor a register with the given encoding value */
+ MM(int v) {
+ if (v != ordinal()) {
+ throw new Error("Invalid register ordinal");
+ }
+ }
+ /** @return encoded value of this register */
+ @Pure
+ public byte value() {
+ return (byte)ordinal();
+ }
+ /**
+ * Convert encoded value into the MM it represents
+ * @param num encoded value
+ * @return represented MM
+ */
+ @Pure
+ public static MM lookup(int num) {
+ return vals[num];
+ }
+ }
/**
* Representation of SSE XMM registers
@@ -157,6 +186,15 @@
FPR FP6 = FPR.FP6;
FPR FP7 = FPR.FP7;
+ MM MM0 = MM.MM0;
+ MM MM1 = MM.MM1;
+ MM MM2 = MM.MM2;
+ MM MM3 = MM.MM3;
+ MM MM4 = MM.MM4;
+ MM MM5 = MM.MM5;
+ MM MM6 = MM.MM6;
+ MM MM7 = MM.MM7;
+
XMM XMM0 = XMM.XMM0;
XMM XMM1 = XMM.XMM1;
XMM XMM2 = XMM.XMM2;
Modified: rvmroot/trunk/rvm/src-generated/ia32-assembler/VM_Assembler.in
===================================================================
--- rvmroot/trunk/rvm/src-generated/ia32-assembler/VM_Assembler.in 2007-10-30 05:29:14 UTC (rev 13836)
+++ rvmroot/trunk/rvm/src-generated/ia32-assembler/VM_Assembler.in 2007-10-31 10:31:06 UTC (rev 13837)
@@ -1884,6 +1884,20 @@
if (lister != null) lister.RXD(miStart, "CMPXCHG8B", base2, index2, scale2, disp2);
}
+ /**
+ * Empty MMX technology state
+ * <PRE>
+ * emms
+ * </PRE>
+ */
+ @Inline
+ public final void emitEMMS() {
+ int miStart = mi;
+ setMachineCodes(mi++, (byte) 0x0F);
+ setMachineCodes(mi++, (byte) 0x77);
+ if (lister != null) lister.OP(miStart, "EMMS");
+ }
+
/*
* BELOW HERE ARE AUTOMATICALLY-GENERATED INSTRUCTIONS. DO NOT EDIT.
*
Modified: rvmroot/trunk/rvm/src-generated/ia32-assembler/genAssembler.sh
===================================================================
--- rvmroot/trunk/rvm/src-generated/ia32-assembler/genAssembler.sh 2007-10-30 05:29:14 UTC (rev 13836)
+++ rvmroot/trunk/rvm/src-generated/ia32-assembler/genAssembler.sh 2007-10-31 10:31:06 UTC (rev 13837)
@@ -1538,37 +1538,27 @@
condLine="
setMachineCodes(mi++, (byte) ${condByte});"
fi
+
+ prefix1Line=
+ if [[ x$prefix != xnone ]]; then
+ prefix1Line="
+ setMachineCodes(mi++, (byte) ${prefix});"
+ fi
+
+ prefix2Line=
+ if [[ x$prefix2 != xnone ]]; then
+ prefix2Line="
+ setMachineCodes(mi++, (byte) ${prefix2});"
+ fi
- if [ x$opCode == xnone ]; then
+ if [ x$opCode != xnone ]; then
cat >> $FILENAME <<EOF
// dstReg ${opStr}= $code srcReg
@Inline
public final void emit${acronym}_Reg_Reg($toRegType dstReg, $fromRegType srcReg) {
- int miStart = mi;
- setMachineCodes(mi++, (byte) ${prefix2});
+ int miStart = mi;$prefix1Line
setMachineCodes(mi++, (byte) 0x0F);
- setMachineCodes(mi++, (byte) ${opCode2});
- emitRegRegOperands(srcReg, dstReg);$condLine
- if (lister != null) lister.RR(miStart, "${acronym}", dstReg, srcReg);
- }
-EOF
-
- else
- cat >> $FILENAME <<EOF
-
- // dstReg ${opStr}= $code srcReg
- @Inline
- public final void emit${acronym}_Reg_Reg($toRegType dstReg, $fromRegType srcReg) {
- int miStart = mi;
-EOF
- if [ x$prefix != xnone ]; then
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) ${prefix});
-EOF
- fi
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode});
emitRegRegOperands(srcReg, dstReg);$condLine
if (lister != null) lister.RR(miStart, "${acronym}", dstReg, srcReg);
@@ -1577,14 +1567,7 @@
// dstReg ${opStr}= $code [srcReg + srcDisp]
@Inline
public final void emit${acronym}_Reg_RegDisp($toRegType dstReg, GPR srcReg, Offset disp) {
- int miStart = mi;
-EOF
- if [ x$prefix != xnone ]; then
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) ${prefix});
-EOF
- fi
- cat >> $FILENAME <<EOF
+ int miStart = mi;$prefix1Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode});
emitRegDispRegOperands(srcReg, disp, dstReg);$condLine
@@ -1594,14 +1577,7 @@
// dstReg ${opStr}= $code [srcIndex<<scale + srcDisp]
@Inline
public final void emit${acronym}_Reg_RegOff($toRegType dstReg, GPR srcIndex, short scale, Offset srcDisp) {
- int miStart = mi;
-EOF
- if [ x$prefix != xnone ]; then
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) ${prefix});
-EOF
- fi
- cat >> $FILENAME <<EOF
+ int miStart = mi;$prefix1Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode});
emitRegOffRegOperands(srcIndex, scale, srcDisp, dstReg);$condLine
@@ -1611,14 +1587,7 @@
// dstReg ${opStr}= $code [srcDisp]
@Inline
public final void emit${acronym}_Reg_Abs($toRegType dstReg, Offset srcDisp) {
- int miStart = mi;
-EOF
- if [ x$prefix != xnone ]; then
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) ${prefix});
-EOF
- fi
- cat >> $FILENAME <<EOF
+ int miStart = mi;$prefix1Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode});
emitAbsRegOperands(srcDisp, dstReg);$condLine
@@ -1628,14 +1597,7 @@
// dstReg ${opStr}= $code [srcBase + srcIndex<<scale + srcDisp]
@Inline
public final void emit${acronym}_Reg_RegIdx($toRegType dstReg, GPR srcBase, GPR srcIndex, short scale, Offset srcDisp) {
- int miStart = mi;
-EOF
- if [ x$prefix != xnone ]; then
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) ${prefix});
-EOF
- fi
- cat >> $FILENAME <<EOF
+ int miStart = mi;$prefix1Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode});
emitSIBRegOperands(srcBase, srcIndex, scale, srcDisp, dstReg);$condLine
@@ -1645,14 +1607,7 @@
// dstReg ${opStr}= $code [srcReg]
@Inline
public final void emit${acronym}_Reg_RegInd($toRegType dstReg, GPR srcReg) {
- int miStart = mi;
-EOF
- if [ x$prefix != xnone ]; then
- cat >> $FILENAME <<EOF
- setMachineCodes(mi++, (byte) ${prefix});
-EOF
- fi
- cat >> $FILENAME <<EOF
+ int miStart = mi;$prefix1Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode});
emitRegIndirectRegOperands(srcReg, dstReg);$condLine
@@ -1661,10 +1616,25 @@
EOF
fi
+
+ if [[ x$opCode2 != xnone ]] && [[ x$opCode == xnone ]]; then
+ cat >> $FILENAME <<EOF
+ // dstReg ${opStr}= $code srcReg
+ @Inline
+ public final void emit${acronym}_Reg_Reg($toRegType dstReg, $fromRegType srcReg) {
+ int miStart = mi;$prefix2Line
+ setMachineCodes(mi++, (byte) 0x0F);
+ setMachineCodes(mi++, (byte) ${opCode2});
+ emitRegRegOperands(srcReg, dstReg);$condLine
+ if (lister != null) lister.RR(miStart, "${acronym}", dstReg, srcReg);
+ }
+EOF
+ fi
+
if [ x$opCode2 != xnone ]; then
cat >> $FILENAME <<EOF
-
+
/**
* Generate a register--register ${acronym}. That is,
* <PRE>
@@ -1676,8 +1646,7 @@
*/
@Inline
public final void emit${acronym}_RegInd_Reg(GPR dstReg, $fromRegType srcReg) {
- int miStart = mi;
- setMachineCodes(mi++, (byte) ${prefix2});
+ int miStart = mi;$prefix2Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode2});
emitRegIndirectRegOperands(dstReg, srcReg);
@@ -1697,8 +1666,7 @@
*/
@Inline
public final void emit${acronym}_RegOff_Reg${ext}(GPR dstIndex, short dstScale, Offset dstDisp, $fromRegType srcReg) {
- int miStart = mi;
- setMachineCodes(mi++, (byte) ${prefix2});
+ int miStart = mi;$prefix2Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode2});
emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
@@ -1708,8 +1676,7 @@
// [dstDisp] ${opStr}= $code srcReg
@Inline
public final void emit${acronym}_Abs_Reg${ext}(Offset dstDisp, $fromRegType srcReg) {
- int miStart = mi;
- setMachineCodes(mi++, (byte) ${prefix2});
+ int miStart = mi;$prefix2Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode2});
emitAbsRegOperands(dstDisp, srcReg);
@@ -1719,8 +1686,7 @@
// [dstBase + dstIndex<<scale + dstDisp] ${opStr}= $code srcReg
@Inline
public final void emit${acronym}_RegIdx_Reg${ext}(GPR dstBase, GPR dstIndex, short scale, Offset dstDisp, $fromRegType srcReg) {
- int miStart = mi;
- setMachineCodes(mi++, (byte) ${prefix2});
+ int miStart = mi;$prefix2Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode2});
emitSIBRegOperands(dstBase, dstIndex, scale, dstDisp, srcReg);
@@ -1730,8 +1696,7 @@
// [dstReg + dstDisp] ${opStr}= $code srcReg
@Inline
public final void emit${acronym}_RegDisp_Reg${ext}(GPR dstReg, Offset disp, $fromRegType srcReg) {
- int miStart = mi;
- setMachineCodes(mi++, (byte) ${prefix2});
+ int miStart = mi;$prefix2Line
setMachineCodes(mi++, (byte) 0x0F);
setMachineCodes(mi++, (byte) ${opCode2});
emitRegDispRegOperands(dstReg, disp, srcReg);
@@ -1748,8 +1713,8 @@
emitSSE2Op 0xF3 none MULSS 0x59 none
emitSSE2Op 0xF3 none DIVSS 0x5E none
emitSSE2Op 0xF3 0xF3 MOVSS 0x10 0x11
-emitSSE2Op 0xF3 none CVTSI2SS 0x2A none none GPR XMM
emitSSE2Op 0xF3 none CVTSS2SD 0x5A none
+emitSSE2Op 0xF3 none CVTSI2SS 0x2A none none GPR XMM
emitSSE2Op 0xF3 none CVTSS2SI 0x2D none none XMM GPR
emitSSE2Op 0xF3 none CVTTSS2SI 0x2C none none XMM GPR
@@ -1765,9 +1730,13 @@
emitSSE2Op 0xF3 none CMPORDSS 0xC2 none 7
# Generic data move ops.
+emitSSE2Op none none MOVD none 0x7E none MM GPR
+emitSSE2Op none none MOVD 0x6E none none GPR MM
emitSSE2Op none 0x66 MOVD none 0x7E none XMM GPR
-emitSSE2Op none 0x66 MOVDr none 0x6E none GPR XMM
-emitSSE2Op 0xF3 0x66 MOVQ 0x7E 0xD6
+emitSSE2Op 0x66 none MOVD 0x6E none none GPR XMM
+# NB there is a related MOVQ for x86 64 that handles 64bit GPRs to/from MM/XMM registers
+emitSSE2Op none none MOVQ 0x6F 0x7F none MM MM
+emitSSE2Op 0xF3 0x66 MOVQ 0x7E 0xD6 none XMM XMM
# Double precision FP ops.
emitSSE2Op 0xF2 none ADDSD 0x58 none
@@ -1792,8 +1761,10 @@
emitSSE2Op 0xF2 none CMPORDSD 0xC2 none 7
# Long ops.
-emitSSE2Op 0x66 0x0F PSLLQ 0xF3 none
-emitSSE2Op 0x66 0x0F PSRLQ 0xD3 none
+emitSSE2Op none none PSLLQ 0xF3 none none MM MM
+emitSSE2Op none none PSRLQ 0xD3 none none MM MM
+emitSSE2Op 0x66 none PSLLQ 0xF3 none
+emitSSE2Op 0x66 none PSRLQ 0xD3 none
emitFloatMemAcc() {
local acronym=$1
Modified: rvmroot/trunk/rvm/src-generated/ia32-assembler-opt/GenerateAssembler.java
===================================================================
--- rvmroot/trunk/rvm/src-generated/ia32-assembler-opt/GenerateAssembler.java 2007-10-30 05:29:14 UTC (rev 13836)
+++ rvmroot/trunk/rvm/src-generated/ia32-assembler-opt/GenerateAssembler.java 2007-10-31 10:31:06 UTC (rev 13837)
@@ -1072,6 +1072,7 @@
excludedOpcodes.add("ENTER");
excludedOpcodes.add("JMP");
excludedOpcodes.add("JCC");
+ excludedOpcodes.add("EMMS");
}
/**
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