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biasgen
On-chip bias current generators in jAER
jAER includes resources for building on-chip fixed and programmable bias current generators.
Design kits and documentation are part of the repository contents under the biasgen branch of the jAER repository at http://svn.code.sf.net/p/jaer/code/biasgen/. You can check this SVN folder out to obtain the latest versions or use the automatically-generated link there to obtain a GNU tarball.
News
- June 2012: Added link to ISCAS 2012 paper about new coarse-fine architecture for programmable bias currents.
- October 2009: Added design kit for UMC 180nm CIS fully configurable bias generator in conjunction with submitted ISCAS 2010 conference paper. See biasgenDesignKitCIS180v1 for the design kit files and delbruckfullyconfigbiasgeniscas2010.pdf (www.ini.uzh.ch) for the conference paper 32-bit Configurable bias current generator with sub-off-current capability, T. Delbruck, P. Lichtsteiner, R. Berner, C. Dualibe, ISCAS 2010.
Introduction
There are two basic classes of design kits for on-chip bias current generators:
- A design kit for compiling MOSIS SCMOS layout and schematics for generating a predetermined set of fixed bias currents. This kit is no longer maintained or used.
- Various design resources for submicron (AMS 0.35u and UMC 180nm) CMOS for generating on-chip digitally programmable biases.
The programmable biases are supported in jAER by PCB firmware and explicit Java classes for persistent bias settings, USB interfacing to the PCBs, and GUI control of biases].
Use of off-chip DACs for voltage biasing are also supported by the VDAC class and by a reference design for the Optical Flow Sensor that includes firmware and PCB layout.
The bias generators are all based on a _master bias Widlar bootstrapped mirror feeding a Bult and Geelen _current splitter, as shown below. Individual biases are read out by the diode connected nfets on the current splitter outputs. The bias currents possibly span a very wide range but the current splitter can span 120dB quite easily, from 10uA to 10pA. The overall scale of the currents is set by the single external resistor on the master bias. The master bias current is independent of threshold voltage, supply voltage, and other process variations, and the generated currents have a PTAT-like behavior, so they tend to maintain constant transconductance with temperature variations.
For an overview of these circuits see for example these slides, which are used for teaching these circuits to the Neuromorphic Engineering course at the ETH Zurich.
Bias generator downloads
To obtain the design resources, check out a subversion working copy of the biasgen branch of the jAER repository using the URL https://svn.code.sf.net/p/jaer/code/biasgen.
Generating Fixed Bias currents
If you want to make a chip that only requires a set of fixed bias currents, but that doesn't require any pots or external digital components, then you can use these fixed bias circuits. Andre van Schaik and Tobi Delbruck developed these circuits in the period 1999-2004, and during the summer of 2003 we made a design kit that greatly simplifies the automatic generation of bias generator layout. Patrick Lichtsteiner and I fabricated this layout on a 0.35u design and it works as specified. This fixed-current bias generator is also used on the http://www.ini.uzh.ch/~tobi/friend Physiologist's Friend Chip.
The kit compiles a bias generated from a set of currents specified by special cells in a the Tanner Tools S-Edit schematic editor.
Requirements for fixed bias currents
- The compiler requires the Tanner EDA chip design tools (L-Edit, S-Edit, T-Spice, etc.), version 12+.
- The design kit is designed for the MOSIS SCMOS_SUBM scalable rules. It uses only single poly and 2 metals, and is shielded for use in chips with light shining on them.
Documentation for fixed bias current generators
|| T. Delbruck, A. van Schaik (2005). Bias current generators with wide dynamic range. Analog Integrated Circuits and Signal Processing, vol . 43, pp. 247-268. || Download PDF ||
|| T. Delbruck, A. van Schaik, Bias current generators with wide dynamic range],2004 International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, Canada, May 23-25 2004 pp. I-337-340 || Download PDF
Generating digitally programmable bias currents
If you need programmable currents then you may want to use the programmable bias generator.
The idea of these circuits is that each bias uses the same, reconfigurable block of layout. All the individual biases get a copy of same master current source and all the biases share a daisy-chained serial
shift register. Each bias is programmed to a fraction of the master bias, and each bias voltage is actively buffered out to the chip core.
These circuits require more layout area and need an off-chip microcontroller but they are much more flexible. They are used on the Dynamic Vision Sensor and several other on-going projects, and have been integrated into chips designed by the Boahen lab and the Universithy of Edinbourough.
Requirements for programmable bias generator
- The design files are for Tanner EDA chip design tools (L-Edit, S-Edit, T-Spice, etc.), version 12+.
- The reference designs are built for the Austria Micro Systems 0.35u BYM 4M-2P process offered by Europractice using AMS rules.
Documents for programmable bias generators
|| M. Yang, S.C. Liu, C. Li, T. Delbruck, Addressable Current Reference Array with 170dB Dynamic Range, in ISCAS 2012, || Download PDF ||
||T. Delbruck, P. Lichtsteiner, R. Berner, C. Dualibe, 32-bit Configurable bias current generator with sub-off-current capability, in ISCAS 2010, Paris, pp. 1647–1650. || Download PDF ||
|| T. Delbruck, P. Lichtsteiner, Fully Programmable Bias Current Generator with 24 Bit Resolution Per Bias, (2006) International Symposium on Circuits and Systems (ISCAS 2006),. 21-24 May 2006 Page(s):2849 - 2852. || Download PDF ||
Programmable biases integration guide
Following is a guide for interfacing a chip with programmable bias generator (e.g. the DVS128 silicon retina) to an external microcontroller. The trickiest part of getting the bias generators to actually work is getting the bit polarities correct and in correct phase with the biasClock.
An overview of the integrated bias generators is in the following figure. The figure is inaccurate with regard to what is actually on-chip because the shift-register shift direction as shown below is opposite to what is actually implemented on-chip. The bits are actually loaded from the lsb end, not the msb end as shown. The bits are loaded starting with the msb (bit 23) of last bias on the shift register (Bias 1/Splitter 1). The last bit loaded is the lsb (bit 0) of the first bias on the shift register (Bias m/Splitter m). This ordering (big-endian-like) is like the hardware SPI output from many microcontrollers, msb first, lsb last. SplitterBias 1 bits are loaded first and Splitter/Bias m bits are loaded last. There are 24 bits per bias.
Signal definitions
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 | |
Timing and signal polarities
The interface is SPI-like (Serial Peripheral Interconnect) but probably not exactly SPI (it is hard to find this "standard").
12 biases load in a little less than 1 ms on present implementations. That means the clock frequency is about 300 kHz. There are reports that in AMS 0.35u the clock can go as high as 3MHz.
The polarities and phases of the bias bits, the bias clock and the latch are important. The procedure is as follows
- Set the bit to be loaded on biasBitIn
- Toggle biasClock up and down
- Repeat 1&2 for all bits
- Toggle biasLatch down and back up
Leave biasClock low after finishing. Leave biasBitIn in last state.
The latest version of the Bias Generator comprises 12 additional cells in the shift register, 4 cells are for testing and debugging purposes, 8 cells are used to program the current value of the BufferBias Splitter that is the global bias current for the active current mirrors that buffer out the bias voltages to the core from each bias. A nonzero value need to be loaded there, or none of the biases will be driven from the biasgen to the core. It doesn't matter too much what the value is as long as it is nonzero.
The new procedure is as follows:
- Set the bit to be loaded on biasBitIn
- Toggle biasClock up and down
- Repeat 1&2 for all bits
- Set the bit for the test cells
- Toggle biasClock up and down
- Repeat 4&5 for 4 bits
- Set the bit for the BufferBiasSplitter
- Toggle biasClock up and down
- Repeat 7&8 for 8 bits
- Toggle biasLatch down and back up
The following figure shows the timing and signal polarities for the latest version of the BiasGen. Th timing was established empirically and it works, it might go faster but it has not been tested.
These actual code snippets show biasgen interface from 8051 microcontroller: (Silicon Labs C8051F320 or CypressFX2LP)
The following are microcontroller output port bit definitions
sbit BIAS_CLOCK=P0^0; // biasgen clock, put this high and low after biasbit change
sbit BIAS_BITIN=P0^2; // biasgen input bit (for chip, output bit from here), active high to enable current splitter output
sbit BIAS_LATCH=P2^7; // biasgen latch, 0=transparent, 1=opaque
sbit BIAS_POWERDOWN=P0^3; // biasgen powerDown input, active high to power down
The following is loop writes out bias bytes. This loop writes out the bytes that have been preordered on the host so that each bias is stored at the pread pointer in MSB to LSB order (3 bytes). It then latches the new bias values.
while(x++<numBytes){
y= *pread;
spiwritebyte(y);
pread++;
}
BIAS_LATCH=0; // make the bias latches transparent
_nop_(); // these nop's are probably not necessary
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
BIAS_LATCH=1; // make latch opaque
The following is assembly code for sending one bias byte and shows clock and bit phases. The bits are written out in msb to lsb order.
;; all the bits are bit-addressable
CLKBIT BIT 0x80^0; this is biasClock
DATABIT BIT 0x80^2 ; this is biasBitIn
_spiwritebyte:
mov R6, #8 ;set up loop for 8 bits
loop:
mov A, R7 ;move data to send to A -- R7 is register that has argument
rlc A ;rotate left through carry
mov R7, A ;save rotated for later
jc highbit ;if carry bit is high jump (jump if carry bit (msb) is set)
; bit is low
clr DATABIT
sjmp skip ;skip setting bit high
highbit:
setb DATABIT
skip:
setb CLKBIT ; toggle clock high and then low
clr CLKBIT
djnz R6, loop ;repeat eight times
The following java code snippet show the host pre-processing of the int (32 bit) bias values to reorder the bytes for loading over the serial interface to the chip
byte[] bytes=new byte[iPotArray.getNumPots()*MAX_BYTES_PER_BIAS];
int byteIndex=0;
Iterator i=iPotArray.getShiftRegisterIterator();
while(i.hasNext()){
// for each bias starting with the first one (the one closest to the ** END ** of the shift register
// we get the bitValue and from MSB ro LSB stuff these values into the byte array
IPot iPot=(IPot)i.next();
for(int k=iPot.getNumBytes()-1;k>=0;k--){ // for k=2..0
bytes[byteIndex++]=(byte)((iPot.getBitValue()>>>k*8)&0xff);
}
}
byte[] toSend=new byte[byteIndex];
System.arraycopy(bytes, 0, toSend, 0, byteIndex);
sendBiasBytes(toSend);
Provide feedback using the Help Forum if there are things not clearly explained here.
Licensing:
By using these bias generator design resources, you agree to the following terms:
These design kits are distributed under the terms of the GNU Public License (http://www.gnu.org/licenses/licenses.html - TOCGPL), with the following additions:
- You are responsible for any use of these resources that infringe on existing patents. (We are not aware of any such existing IP.)
- We have built these circuits on several chips and they function correctly, but chip design is a tricky business, so there is absolutely no warranty as to functionality of these circuits.
- Users of this resource on chips that result in publications must cite our relevant publications.
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