I'm trying to interfacing several chips to the USB2AER board. The /Req and /Ack from each chip are combined using logic gates, but it has to use multi-sender AER. I realise that the board accepts the single-sender single-receiver protocol by default. Is there a solution to this?
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Raphael - This is one for you. I think the board does multisender protocol - reads address after ack is asserted by the board - but am not sure about this.
There is a modified version of the CPLD configuration that makes the board into a 2-chip monitor, but requires a xilinx programmer to modify the CPLD configuration.
Tobi
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
I think the board currently reads the address when /REQ goes low. For multi-sender, address should be read some time after ACK is asserted, or when /REQ goes high again.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
if you want to reprogram the CPLD, you need Xilinx ISE, which can be downloaded for free, and a programmer cable...
implementing a switch which lets you chose p2p or multisender unfortunately doesn't fit into the CPLD, you would have to program a multisender only version or drop something else (like synchronising).
BTW, tobi, do you have any news regarding the CPLD programming with the microcontroller?
raphael
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
I'm trying to interfacing several chips to the USB2AER board. The /Req and /Ack from each chip are combined using logic gates, but it has to use multi-sender AER. I realise that the board accepts the single-sender single-receiver protocol by default. Is there a solution to this?
Raphael - This is one for you. I think the board does multisender protocol - reads address after ack is asserted by the board - but am not sure about this.
There is a modified version of the CPLD configuration that makes the board into a 2-chip monitor, but requires a xilinx programmer to modify the CPLD configuration.
Tobi
I think the board currently reads the address when /REQ goes low. For multi-sender, address should be read some time after ACK is asserted, or when /REQ goes high again.
Yes, correct, the board presently reads the addr on req going low.
Can the CPLD configuration be modified for multisender mode?
Raphael - What hardware and software is necessary for CPLD tweaking?
Tobi
if you want to reprogram the CPLD, you need Xilinx ISE, which can be downloaded for free, and a programmer cable...
implementing a switch which lets you chose p2p or multisender unfortunately doesn't fit into the CPLD, you would have to program a multisender only version or drop something else (like synchronising).
BTW, tobi, do you have any news regarding the CPLD programming with the microcontroller?
raphael
I don't mind converting the board into multi-sender only. What kind of programming cable do I need?
you need a JTAG cable. there exist several versions from xilinx, either parallel or USB. but i guess, any JTAG programmer should do...
here is the webpage with a list of xilinx programmers and also supported 3rd party programmers.
http://www.xilinx.com/products/design_resources/config_sol/
here you can download the free Xilinx webpack software, with which you can compile VHDL and download it to the CPLD
http://www.xilinx.com/ise/logic_design_prod/webpack.htm
Thanks. I'll check them out.
The CPLD can now easily by programmed through USB, no JTAG programmer cable is needed anymore.