#88 sdw_lvalconcat2 always passes

closed-accepted
nobody
None
5
2009-02-03
2009-01-31
Nick Gasson
No

This test tries to verify statements like this:

assign {a,b} = c;

However, all the tests on the values a and b, and the updates to c, occur in an initial block at time-0 and in all the comparisons the value of a and b is z. The comparison uses != so the test passes regardless. (You can see this if you change all the comparisons to !== .)

I've attached a patch which changes the comparisons to !== and adds a #1 before each test.

(Noticed this when I was getting problems with the comparisons involving 'U' in the VHDL translation.)

Discussion

  • Stephen Williams

    • status: open --> closed-accepted
     
  • Stephen Williams

    Already applied?

     

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