[Iverilog-devel] Make iverilog accept (but ignore) unsupported SDF constructs.

[Stefan D. <Dr...@ri...>]

Hi everyone,

I was trying to run a post-synthesis simulation using iverilog with a netlist generated by Xilinx Vivado.

I ran into a problem that iverilog complains about the SDF file containing invalid syntax, as some of the keywords are not implemented in iverilogs sdf parser. The problematic constructs for my case are `PATHPULSEPERCENT` within the `DELAY` construct and `PERIOD` within the `TIMINGCHECK` construct. See the end of the email for a snippet of the sdf file.

 

I checked the IEEE1497-2001 standard and the problematic constructs are valid as far as I can see (so no Xilinx specific weirdness here)

 

I dont really need the functionality offered by these constructs, but it would be nice if iverilog could still accept the file as valid and simulate only with the supported subset, maybe printing a warning about what was ignored.

 

The problematic sdf code:

 

(DELAYFILE 

(SDFVERSION "3.0" )

(DESIGN "top")

(DATE "Tue Aug 13 18:03:42 2019")

(VENDOR "XILINX")

(PROGRAM "Vivado")

(VERSION "2019.1")

(DIVIDER /)

(TIMESCALE 1ps)

(CELL 

  (CELLTYPE "BUFGCE")

  (INSTANCE clk_IBUF_BUFG_inst)

  (DELAY 

    (PATHPULSEPERCENT (30,0))

    (ABSOLUTE 

      (IOPATH I O (40.0:47.0:47.0) (40.0:47.0:47.0))

    )

  )

    (TIMINGCHECK

      (SETUPHOLD (posedge CE) (posedge I) (84.0:275.0:275.0) (0.0:0.0:0.0))

      (SETUPHOLD (negedge CE) (posedge I) (84.0:275.0:275.0) (0.0:0.0:0.0))

      (PERIOD (posedge I) (1499.0:1499.0:1499.0))

      (PERIOD (negedge I) (1499.0:1499.0:1499.0))

      (WIDTH (negedge CE) (550.0:550.0:550.0))

      (WIDTH (posedge CE) (550.0:550.0:550.0))

    )

)

)

 

 

Kind Regards, Stefan