[Iverilog-devel] Time 0 races

[Martin W. <ic...@ma...>]

Evan Lavelle wrote:
> Here's one I spent a few hours on:
> 
> module test;
>    event done;
>    initial begin
>      // #0;
>      foo;   // may or may not finish in zero time
>      -> done;
>    end
>    always @(done)
>      ...    // may or may not fire
> endmodule
> 
> There's a race between event creation and event triggering, and this code 
> "fails" in 4/7 simulators (including Incisive). Uncommenting the #0 makes 
> it run on all 7 simulators.
> ?!

I delved into the Icarus compiler code, and found the rules for 
prioritising always constructs are more complex than I remembered. It tries 
to identify always constructs that are modelling combinatorial logic, and 
only prioritises those. Your example above doesn't qualify - I think 
because it is sensitive to an event, not a signal.

I tested this example:

module test();
   reg i, q;
   initial i = 1;
   always @(i) q = i;
   initial #1 $display(q);
endmodule

Icarus and Riveria Pro output '1'. CVer and Veriwell output 'x'. Moving the 
always construct to before the initial constructs results in all four 
outputing '1'.