Re: [Iverilog-devel] possible regression in 0.10 when simulating Lattice FF

[Galen S. <ga...@se...>]

On 8/8/19 4:13 PM, Martin Whitaker wrote:
> Galen Seitz wrote:
>> I was hesitant to post a link to Lattice copyrighted code, as I wasn't 
>> sure whether that was acceptable on the list.  That github project 
>> link contains the entire simulation library for the XP2 family, so 
>> I've decided not to worry about posting a link to a few files from the 
>> MachXO3 family.
>>
>> <https://www.edaplayground.com/x/3EKT>
>>
>> After running the simulation, from the EPWave window, click "Get 
>> Signals", then select the ".ff" instance.  Click the "Append All" 
>> button.  These are the ports of the .ff instance of the FD1P3DX 
>> module, which are the signals I've been looking at.
>>
>> If accessing EDA playground is a problem, let me know, and I will 
>> arrange other access to the files.
>>
>> My test design that demonstrates the problem consists of a testbench 
>> and four files from the Lattice library.  GSR.v is a global reset, and 
>> should be unused.  PUR.v is a power up reset which generates a 1 ns 
>> reset pulse starting at time 0.  FD1P3DX.v is some sort of wrapper 
>> around the UDFDL5E_UDP_X.v primitive.  When I grep the Lattice library 
>> I find that there are six modules that instance this particular UDP 
>> primitive.
>>
>> My testbench generates a reset signal that is 2 clocks long.  The D 
>> input is tied to 0, and the enable is tied to 1.  Notifier is an 
>> internal signal of FD1P3DX and is X, but that doesn't seem to impact 
>> the simulation.
>>
>> With iverilog 0.10.0, the Q output is X at time 0 and remains X for 
>> the entire simulation.  With any other simulator on EDA playground, Q 
>> is 0 at time 0, and remains 0 for the entire simulation.  This 
>> includes iverilog 0.9.7 and 0.9.6.
> 
> If you look inside the FD1P3DX module, the QB signal output from the UDP 
> is correctly set to 0. The problem appears to be a race between the 
> execution of the "initial Q=1'b0;" inside the UDP and the execution of 
> the "always @ QB" inside the FD1P3DX module. If the initial statement is 
> executed first, the "@ QB" will never trigger.

I have created a simplified design for testing.  I replaced the Lattice 
UDP with this:

primitive dummy_udp(Q, D);
input D;
output Q;
	table
	   ? : 0;
	endtable
endprimitive


And what was the flip-flop wrapper now looks like this:

`timescale 1ns/100ps

module dummy(D, Q);
   input D;
   output Q;
   reg Q;
   wire QB;

   dummy_udp u2 (QB, D);

   always @ QB
   begin
       Q <= QB;
   end

endmodule



Using this design, I still get the same unknown from the "always @ QB". 
The full design is here:

<https://www.edaplayground.com/x/4yBY>

It seems odd to me that only iverilog 0.10 gives this result when all 
other simulators on EDA playground show the output at 0.  I know next to 
nothing about simulator internals.  Am I being unrealistic in expecting 
this to work?  Given that the original flip-flop where I encountered 
this is Lattice code and not my own, my naïve expectation is that their 
models would operate correctly.


galen
-- 
Galen Seitz
ga...@se...