[Iverilog-devel] possible regression in 0.10 when simulating Lattice FF

[Galen S. <ga...@se...>]

Hi,

I just stumbled onto a simulation issue while simulating a Lattice 
MachXO3 design.  I've narrowed it down to the FD1P3DX.v (a simple 
flip-flop) and UDFDL5E_UDP_X.v (the underlying primitive) simulation 
files that come with the Lattice tools (Diamond 3.11_x64 under CentOS 
7.6).  With Icarus version 10.2 (from epel), the output of the flip-flop 
is X at time 0 even though reset is being asserted.  I built and tested 
using iverilog from the HEAD of the v10 branch (commit b7b22660) and I 
get the same results.

Using EDA playground I get the following iverilog results:
iverilog 0.9.6		flip-flop Q = 0
iverilog 0.9.7		flip-flop Q = 0
iverilog 0.10.0		flip-flop Q = X

All of the other simulators that I have tried on EDA playground give 
flip-flop Q = 0 as a result.  This includes Synopsys, Cadence, and 
Aldec, as well as Cver and VeriWell.  It seems that something changed in 
0.10 to break this particular simulation.

The simulation files are copyright Lattice, but are included in any 
Diamond installation.  Currently I have a playground configured that 
shows the problem (by looking at the wave output).  I can share a link 
to the playground.  Is that acceptable?

thanks,
galen
-- 
Galen Seitz
ga...@se...