[Iverilog-devel] Looking for co-founder startup partner

[Le N. T. <lnt...@gm...>]

Hello,

I am Nguyen Tran, and I am look for for a co-founder startup partner. If
any one of you are interested in my idea, please do not hesitate to contact
me.

I introduce shortly about myself here. I have PhD degree and more than 10
years of working experience in ASIC design. My main fields are computer
architecture and ASIC design. I am currently a chip designer for a very
reputable company.

My idea is to develop a very fast RTL simulator. The key point is using
FPGA to accelerate the simulation. We do not use FPGA as an emulator.
Instead, we implement a custom many-core processor to run RTL simulation.
We believe that the normal currently CPU (like from Intel or AMD) are not
efficient for RTL simulation. Although the CPU has a number of cores,
utilising all of them for RTL simulation is not very efficient due to the
high overhead for thread synchronization. If we implement a custom
processor using FPGA, we can minimize thread synchronization, offer 4-level
logic ('1', '0', 'x', 'z') calculation, and utilize parallel simulation
among modules and processes... That accelerates RTL simulation.

Our RTL simulator will support DPI so that it can work with other tools
like Incisive, VCS, Questa. In this case, the RTL simulation is handled by
our tool, and the UVM verification is handled by the other one. That allows
our tool can be integrated easily in many current ASIC design flows.

To develop our simulator, I will handle the FPGA development part. I
expected to have a co-founder partner develop a RTL compiler for it.

I look forward to hearing from you and thank you so much for your time.

Best regards,

Nguyen.