[Iverilog-devel] VHDL function overloading

[David F. <da...@ch...>]

Hi,

Does iverilog support VHDL function overloading such as this simple type conversion ?

For example, below there are three same named functions but with different inputs.

function tost(v:std_logic_vector) return string is
. . .

function tost(v:std_logic) return string is
. . .

function tost(i: integer) return string is
. . .

Thanks,

David