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From: David F. <da...@ch...> - 2018-07-02 22:05:49
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Hi, Does iverilog support VHDL function overloading such as this simple type conversion ? For example, below there are three same named functions but with different inputs. function tost(v:std_logic_vector) return string is . . . function tost(v:std_logic) return string is . . . function tost(i: integer) return string is . . . Thanks, David |