[Iverilog-devel] Support for "var" keyword?

[Robert B. <rob...@gm...>]

It appears to be in parse.y, but not referenced.

Here's my input, transparent_latch.sv:

module transparent_latch(
output var q);
endmodule : transparent_latch

And the output:

$ iverilog -g2012 -v -o thing transparent_latch.sv

Icarus Verilog version 11.0 (devel) (s20150603-553-g6c39348)

(snipped copyright message)

translate: /usr/local/lib/ivl/ivlpp  -v -L -F"/tmp/ivrlg2288d4707"
-f"/tmp/ivrlg288d4707" -p"/tmp/ivrli288d4707" | /usr/local/lib/ivl/ivl -v
-C"/tmp/ivrlh288d4707" -C"/usr/local/lib/ivl/vvp.conf" -- -
Icarus Verilog Preprocessor version 11.0 (devel) (s20150603-553-g6c39348)

(snipped copyright message)

/usr/local/lib/ivl/system.sft: Processing System Function Table file.
/usr/local/lib/ivl/vhdl_sys.sft: Processing System Function Table file.
/usr/local/lib/ivl/vhdl_textio.sft: Processing System Function Table file.
/usr/local/lib/ivl/v2005_math.sft: Processing System Function Table file.
/usr/local/lib/ivl/va_math.sft: Processing System Function Table file.
/usr/local/lib/ivl/v2009.sft: Processing System Function Table file.
Using language generation: IEEE1800-2012,no-specify,xtypes,icarus-misc
PARSING INPUT
transparent_latch.sv:2: syntax error
transparent_latch.sv:1: Errors in port declarations.

Replacing "var" with "reg" works. But really, I'd like to use the "new"
syntax.

--Rob