Re: [Iverilog-devel] Simulation in iverilog producing different values when compared to Xilinx simulator

[Martin W. <ic...@ma...>]

$dumpvars is the way to dump changes, but that only shows the final values 
at the end of each time step. I always recommend adding a small delay to 
non-blocking assignments, e.g.

`ifdef DEBUG
`define DLY #0.1
`else
`define DLY
`endif

mem_0[addr_block]<= `DLY mem_write_data[2*`PIXEL_WIDTH-1:0]

which, when DEBUG is defined, moves the changes resulting from a clock edge 
into a different time step, making it easier to see cause and effect in the 
waveform viewer.

You may be able to get more details by single-stepping. Compile your code 
with the -pfileline=1 option, and add a $stop system call to create a 
breakpoint. When vvp executes the $stop, it will drop out to a command 
prompt. Type help to show the available commands.

Sab VS wrote:
> Hi Martin,
> 
> Apprciate the response. I will check the write enable and get back. Is
> there anyway to see what exactly is happening at the timestep level in
> iverilog? Is there some file that I can produce to see how the simulator is
> doing the write?
> 
> On Mon, Apr 23, 2018 at 2:31 PM, Martin Whitaker <
> ic...@ma...> wrote:
> 
>> Sab VS wrote:
>>
>>> Hi,
>>>
>>> I am currently trying to debug a piece of code which is not working
>>> correctly in the iverilog simulator.
>>>
>>> The code shows that the mem_write_data changes every clock cycle.
>>>
>>> However, the mem_0 is not changing. I am writing into mem_0 using the
>>> following
>>>
>>> mem_0[addr_block]<=mem_write_data[2*`PIXEL_WIDTH-1:0]
>>>
>>> In Xilinx I see the expected value. Is this an iverilog problem or am I
>>> doing something wrong?
>>>
>>> I have created a short gist
>>> https://gist.github.com/raiderark/9a857fc48d5ce9bac9bfa5b54acc3e9c .
>>> Please
>>> comment out the unused modules in order to compile.
>>>
>>> Could someone please help me out?
>>>
>>
>> Not easily, no. Your test case fails to compile, due to a missing include
>> file.
>>
>> The chances are that there is a race in your code, leading to different
>> results with different simulators. Check the timing of your memory write
>> enable signal - is it guaranteed to be stable before the clock edge?
>>
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> 
> 
> 
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