Re: [Iverilog-devel] Icarus compiler crash

[Martin W. <ic...@ma...>]

Don Haire wrote:
> This was originally sent 2/24/2018 while SourceForge was down:

If SourceForge is down, you can instead submit bug reports on GitHub. 
Whilst it would be better if all the bug reports were in one place, many 
users are submitting reports on GitHub, so one more won't hurt...

...
> -------------------------------------------
> 
> On 2/27/2018, I found the code which incited the crash, lines 48, 74, and 
> 187.  Each of these lines contains an implicit type conversion at an 
> assignment.  Making the conversion explicit removes the crash.  For example,
> 
>     names[i] = temp_str;  // implicit, compiler crashes
> 
>     names[i] = reg  [NAME_MAX_LENGTH*8:1] '(temp_str);  // explicit, 
> compiler does not crash
> 
> Fixing the code is my problem, of course, but I believe that the compiler 
> should not crash when it encounters this.

Quite right!

The IEEE standard isn't particularly clear, but as I read it, an explicit 
cast is required here, so the compiler should output an error message. I've 
patched it locally to do this, both for this case and for other cases where 
an explicit cast is required. Unfortunately this has exposed a case where 
the VHDL preprocessor is generating illegal SystemVerilog. This occurs with 
the br986 test case in the test suite. The generated code is

   module \ibufds #(parameter \diff_term = \false) (
     input wire logic \i[],
     input wire logic \ib,
     output wire logic \o);
     // ivltests/br986.vhd:51
     assign \o  = \i ;
   endmodule

which is assigning a dynamic array to a single bit. The VHDL code that 
produces this is

   entity ibufds is
     generic (
       DIFF_TERM : boolean := FALSE
     );
     port (
       i     : in  std_logic_vector;
       ib    : in  std_logic;
       o     : out std_logic
     );
   end ibufds;

   architecture ibufds_sim of ibufds is
   begin
     o <= i;
   end ibufds_sim;

I'm surprised assigning a std_logic_vector variable to a std_logic variable 
is legal in VHDL. Can someone who knows VHDL confirm this is allowed?

Martin