iverilog-devel — Conversations on matters of Icarus Verilog development

Re: [Iverilog-devel] System verilog support in Icarus

[Cary R. <cy...@ya...>]

 A quick question on the following from 1800-2012 page 171.
    Variables on the left-hand side of assignments within an always_comb procedure, including vari-
    ables from the contents of a called function, shall not be written to by any other processes
Does this apply to procedural continuous assignments (force/assign) statements? Basically is the following an error?

module top;  reg a;
  reg test;  initial begin    a = 1'b0;    force test = 1'b1;
  end  always_comb    test = a;
endmodule
I would expect procedural force/assign statements to be okay since they are used to patch/override logic.
Cary
    On Wednesday, December 27, 2017, 3:15:38 PM PST, Cary R. via Iverilog-devel <ive...@li...> wrote:  
 
  I have committed more basic synthesis construct checking for the always_* processes and a number of other fixes. The big remaining items are checking that L-values are assigned correctly and that the blocks have the correct constructs for the block type (synthesize correctly). I have a few more cleanup issues that I need to take care of and then I plan to look at the L-value checking. I would be interested in knowing if the latest checks match what people are expecting. At the moment there is not a disable for these, but that could easily be added. The question is at what granularity should they be disabled if this is needed?

Cary

    On Sunday, December 3, 2017, 8:35:16 PM PST, Cary R. via Iverilog-devel <ive...@li...> wrote:  
 
 My goal is to work on the shall (required) parts and work on the more user friendly (should) parts if they are not too complicated.Support for the T0 trigger for always_comb/latch has been added as the first event in the inactive region. Support for converting this to vlog95 has also been added.
Cary
 

    On Friday, November 24, 2017, 4:07:19 AM PST, Martin Whitaker <ic...@ma...> wrote:  
 
 Niels Möller wrote:
> Martin Whitaker <ic...@ma...> writes:
>
>> Did you not see Cary's announcement about this (3 days ago)?
>>
>> If not, see the mailing list archive:
>>
>> https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711
>
> Thanks for the pointer. And no, I didn't see it. It seems I was somehow
> kicked out from the list a few months ago and I haven't received list
> mail since April 23 (and I've not had any reason to post, either). First
> attempt at sending this question, a few days ago, failed with a
> non-member bounce, and I had to resubscribe.

I had similar problems. And the lack of response to my recent posts makes 
me wonder how many others we've lost...

> I'm reading Cary's announcement as good progress, but not yet quite
> useful for my purposes. And I totally agree it makes sense to have
> correctness for valid code as the top priority, even if my main interest
> is in stricter compile-time checks for incorrect code.

The checks are likely to be more tricky. At the moment the compiler 
calculates sensitivities down to the individual variable level, but to 
correctly implement the checks you need to know the sensitivities down to 
the individual bit level. The synthesis code in the compiler has the same 
problem when it is trying to detect latches.

Martin

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Re: [Iverilog-devel] System verilog support in Icarus

[Cary R. <cy...@ya...>]

 I have committed more basic synthesis construct checking for the always_* processes and a number of other fixes. The big remaining items are checking that L-values are assigned correctly and that the blocks have the correct constructs for the block type (synthesize correctly). I have a few more cleanup issues that I need to take care of and then I plan to look at the L-value checking. I would be interested in knowing if the latest checks match what people are expecting. At the moment there is not a disable for these, but that could easily be added. The question is at what granularity should they be disabled if this is needed?

Cary

    On Sunday, December 3, 2017, 8:35:16 PM PST, Cary R. via Iverilog-devel <ive...@li...> wrote:  
 
 My goal is to work on the shall (required) parts and work on the more user friendly (should) parts if they are not too complicated.Support for the T0 trigger for always_comb/latch has been added as the first event in the inactive region. Support for converting this to vlog95 has also been added.
Cary
 

    On Friday, November 24, 2017, 4:07:19 AM PST, Martin Whitaker <ic...@ma...> wrote:  
 
 Niels Möller wrote:
> Martin Whitaker <ic...@ma...> writes:
>
>> Did you not see Cary's announcement about this (3 days ago)?
>>
>> If not, see the mailing list archive:
>>
>> https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711
>
> Thanks for the pointer. And no, I didn't see it. It seems I was somehow
> kicked out from the list a few months ago and I haven't received list
> mail since April 23 (and I've not had any reason to post, either). First
> attempt at sending this question, a few days ago, failed with a
> non-member bounce, and I had to resubscribe.

I had similar problems. And the lack of response to my recent posts makes 
me wonder how many others we've lost...

> I'm reading Cary's announcement as good progress, but not yet quite
> useful for my purposes. And I totally agree it makes sense to have
> correctness for valid code as the top priority, even if my main interest
> is in stricter compile-time checks for incorrect code.

The checks are likely to be more tricky. At the moment the compiler 
calculates sensitivities down to the individual variable level, but to 
correctly implement the checks you need to know the sensitivities down to 
the individual bit level. The synthesis code in the compiler has the same 
problem when it is trying to detect latches.

Martin

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[Iverilog-devel] Thank you all for iverilog

[Brian C. <cra...@gm...>]

Hello Guys,

I just wanted to thank you all for iverilog. I've used your tool for a
couple years now on various hobby projects and self learning. Its awesome
and it helped me learn and have fun and I just wanted to say thank you.

Brian Crafton

Re: [Iverilog-devel] New SV constructs in devel

[Cary R. <cy...@ya...>]

 
Support for the T0 trigger has been added to always_comb and always_latch. This should give correct functionality thought all the checks are still missing.
Cary
    On Monday, November 20, 2017, 8:21:05 AM PST, Cary R. via Iverilog-devel <ive...@li...> wrote:  
 
 Over the weekend I added support for the wild comparison operators (==? and !=?) and as a bonus I added basic/preliminary support for always_comb, always_ff and always_latch. The always_* work is not complete. Specifically always comb and always_latch do not currently have support for the automatic time zero trigger and none of the special compile time checks have been added (only one block writing to a variable, other statement limitations, etc.). Fixing the runtime issue to get correct functionality is my top priority. I believe the compiler is correctly calculating the sensitivity for the comb and latch processes so this is ready to use/testing as long as you keep the above runtime limitation and missing checks in mind.
It is not obvious how to convert the wild operators to something that the vlog95 target can support. The always_* processes are converted to an always statement with the appropriate sensitivity. This is basically @* plus descending into the body of functions  minus the output variables.
If you have any questions or comments please let me know.

Cary
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Re: [Iverilog-devel] System verilog support in Icarus

[Cary R. <cy...@ya...>]

My goal is to work on the shall (required) parts and work on the more user friendly (should) parts if they are not too complicated.Support for the T0 trigger for always_comb/latch has been added as the first event in the inactive region. Support for converting this to vlog95 has also been added.
Cary
 

    On Friday, November 24, 2017, 4:07:19 AM PST, Martin Whitaker <ic...@ma...> wrote:  
 
 Niels Möller wrote:
> Martin Whitaker <ic...@ma...> writes:
>
>> Did you not see Cary's announcement about this (3 days ago)?
>>
>> If not, see the mailing list archive:
>>
>> https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711
>
> Thanks for the pointer. And no, I didn't see it. It seems I was somehow
> kicked out from the list a few months ago and I haven't received list
> mail since April 23 (and I've not had any reason to post, either). First
> attempt at sending this question, a few days ago, failed with a
> non-member bounce, and I had to resubscribe.

I had similar problems. And the lack of response to my recent posts makes 
me wonder how many others we've lost...

> I'm reading Cary's announcement as good progress, but not yet quite
> useful for my purposes. And I totally agree it makes sense to have
> correctness for valid code as the top priority, even if my main interest
> is in stricter compile-time checks for incorrect code.

The checks are likely to be more tricky. At the moment the compiler 
calculates sensitivities down to the individual variable level, but to 
correctly implement the checks you need to know the sensitivities down to 
the individual bit level. The synthesis code in the compiler has the same 
problem when it is trying to detect latches.

Martin

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Re: [Iverilog-devel] System verilog support in Icarus

[Martin W. <ic...@ma...>]

Niels Möller wrote:
> Martin Whitaker <ic...@ma...> writes:
>
>> Did you not see Cary's announcement about this (3 days ago)?
>>
>> If not, see the mailing list archive:
>>
>> https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711
>
> Thanks for the pointer. And no, I didn't see it. It seems I was somehow
> kicked out from the list a few months ago and I haven't received list
> mail since April 23 (and I've not had any reason to post, either). First
> attempt at sending this question, a few days ago, failed with a
> non-member bounce, and I had to resubscribe.

I had similar problems. And the lack of response to my recent posts makes 
me wonder how many others we've lost...

> I'm reading Cary's announcement as good progress, but not yet quite
> useful for my purposes. And I totally agree it makes sense to have
> correctness for valid code as the top priority, even if my main interest
> is in stricter compile-time checks for incorrect code.

The checks are likely to be more tricky. At the moment the compiler 
calculates sensitivities down to the individual variable level, but to 
correctly implement the checks you need to know the sensitivities down to 
the individual bit level. The synthesis code in the compiler has the same 
problem when it is trying to detect latches.

Martin

Re: [Iverilog-devel] System verilog support in Icarus

[<ni...@ly...>]

Martin Whitaker <ic...@ma...> writes:

> Did you not see Cary's announcement about this (3 days ago)?
>
> If not, see the mailing list archive:
>
> https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711

Thanks for the pointer. And no, I didn't see it. It seems I was somehow
kicked out from the list a few months ago and I haven't received list
mail since April 23 (and I've not had any reason to post, either). First
attempt at sending this question, a few days ago, failed with a
non-member bounce, and I had to resubscribe.

I'm reading Cary's announcement as good progress, but not yet quite
useful for my purposes. And I totally agree it makes sense to have
correctness for valid code as the top priority, even if my main interest
is in stricter compile-time checks for incorrect code.

Thanks a lot,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677.
Internet email is subject to wholesale government surveillance.

Re: [Iverilog-devel] System verilog support in Icarus

[Martin W. <ic...@ma...>]

Niels Möller wrote:
> Stephen Williams <st...@ic...> writes:
>
>> For the scheduling part, there is an internal attribute that elaboration
>> can attach to the process (the NetProc instance?) to adjust scheduling
>> at startup. That would probably be the best way to handle it.
>
> This is from a thread on support for always_comb and always_ff, one and
> a half year ago. When I pulled today, I noticed
>
> commit 585a0232cbd54e20d1dc41d2cb7712e18784bb8d
> Author: Cary R <cy...@ya...>
> Date:   Mon Nov 20 07:48:35 2017 -0800
>
>     Add preliminary support for always_comb, always_ff and always_latch
>
> Can you say something more about status and plans?

Did you not see Cary's announcement about this (3 days ago)?

If not, see the mailing list archive:

https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711

Re: [Iverilog-devel] System verilog support in Icarus

[<ni...@ly...>]

Stephen Williams <st...@ic...> writes:

> For the scheduling part, there is an internal attribute that elaboration
> can attach to the process (the NetProc instance?) to adjust scheduling
> at startup. That would probably be the best way to handle it.

This is from a thread on support for always_comb and always_ff, one and
a half year ago. When I pulled today, I noticed

commit 585a0232cbd54e20d1dc41d2cb7712e18784bb8d
Author: Cary R <cy...@ya...>
Date:   Mon Nov 20 07:48:35 2017 -0800

    Add preliminary support for always_comb, always_ff and always_latch

Can you say something more about status and plans?

Being able to use these (and getting clear and reliable errors for
incorrect usage) would help me write less buggy code, as I try to
use separate processes for combinational and stateful logic. So I'm
really happy for progress on this front.

Best regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677.
Internet email is subject to wholesale government surveillance.

[Iverilog-devel] New SV constructs in devel

[Cary R. <cy...@ya...>]

Over the weekend I added support for the wild comparison operators (==? and !=?) and as a bonus I added basic/preliminary support for always_comb, always_ff and always_latch. The always_* work is not complete. Specifically always comb and always_latch do not currently have support for the automatic time zero trigger and none of the special compile time checks have been added (only one block writing to a variable, other statement limitations, etc.). Fixing the runtime issue to get correct functionality is my top priority. I believe the compiler is correctly calculating the sensitivity for the comb and latch processes so this is ready to use/testing as long as you keep the above runtime limitation and missing checks in mind.
It is not obvious how to convert the wild operators to something that the vlog95 target can support. The always_* processes are converted to an always statement with the appropriate sensitivity. This is basically @* plus descending into the body of functions  minus the output variables.
If you have any questions or comments please let me know.

Cary

Re: [Iverilog-devel] Incorrect handling of timeunit/timeprecision in compilation unit scope

[Martin W. <ic...@ma...>]

Martin Whitaker wrote:
> I'm working on adding support in the compiler for treating each file as
> a separate compilation unit (as required by the SystemVerilog standard).
> I've run into a problem with the way Icarus handles timeunit and
> timeprecision declarations.
>
> Currently the compiler allows timeunit and timeprecision declarations
> to change the timescale in the compilation unit scope (and there are
> tests in the test suite that do this). This is explicitly forbidden by
> the SystemVerilog standard (1800-2012 section 3.14.2.2).
>
> Does anyone want to argue against fixing the compiler to be compliant
> with the standard?

I've taken silence as a no. In devel, the compiler now enforces the 
standard rules. A few other bugs in handling timescales have been fixed 
along the way.

There is now support in the compiler for treating each file as a separate 
compilation unit. Use the new iverilog '-u' option to enable this.

The compiler also now recognises the $unit scope identifier. However, there 
are several places where the compiler should accept a scope identifier but 
doesn't, e.g. when calling tasks. My attempts to fix this have run into the 
usual shift/reduce conflicts in the parser.

Compilation unit scopes are handled internally as packages. These are named 
as $unit#<n> (where <n> is a unique number for each compilation unit) or 
just $unit if separate compilation is not enabled. This has the potential 
to collide with user package names (if the user is mad enough to use 
escaped identifiers for package names) but the risk seems low enough to not 
worry about.

It should now be relatively easy to add support for parameters and 
variables in the compilation unit scope.

Re: [Iverilog-devel] Passing arrays

[Martin W. <ic...@ma...>]

This failure only occurs if you compile this module in isolation. When I 
added a top level module that instantiated it, I could compile and run 
without any errors.

It looks like the section of the compiler that ties off root-level module 
ports didn't get updated when support for this SystemVerilog feature was added.

Kustaa Nyholm wrote:
> Hi,
>
> I'm more or less noobie as far as Verilog is concerned, just at the beginning of trying to find my bearings.
> My background is sw (+35 years) with some basic level uni courses in VHDL thrown in.
>
> As a naive starting point for what I'm trying to do I googled around came up with this skeleton:
>
>  module correlator (
>   input [LENGTH-1:0] datain [WIDTH-1:0],
>   input clk,
>   input reset,
>   output [WIDTH-1 : 0] out
> );
>
>    parameter LENGTH = 4;
>    parameter WIDTH = 8;
>
>    reg [WIDTH-1 : 0]   out;
>    wire       clk, reset;
>
>   always @(posedge clk)
>     out <= out + 1;
>
>   always @reset
>     if (reset)
>       assign out = 0;
>     else
>       deassign out;
>
> endmodule
> // #(int LENGTH, DEPTH)
>
> compiling this crashes with:
>
> iverilog -g2005-sv -o test  correlator.v
>
> correlator.v:2: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1
>
> sh: line 1: 31244 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg21f4c2686" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg1f4c2686" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli1f4c2686"
>
>      31245 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh1f4c2686" -C"/usr/local/lib/ivl/vvp.conf" -- -
>
> macbook-pro:verilogexp nyholku$ iverilog -g2005-sv -o test  correlator.v
>
> correlator.v:2: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1
>
> sh: line 1: 40581 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg228a6aa75" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg28a6aa75" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli28a6aa75"
>
>      40582 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh28a6aa75" -C"/usr/local/lib/ivl/vvp.conf" -- -
>
> So my questions is if there is a workaround for this or is my verilog faulty?
>
> I also tried
> module correlator #(int LENGTH, WIDTH)
> and the compiler said it gave up on line 1.
>
> Is there a workaround for this?
>
> I think I'm running latest development branch from github (v10) but how can I check?
>
> As at this point in time I do not know the how many inputs my correlator module will take so I want to parametrise that .
>
> My ultimate goal is to create a massively parallel sea (also parametrised) of this correlator module so any pointers to examples of this would be highly appreciated...
>
> wbr Kusti

Re: [Iverilog-devel] Passing arrays

[Kustaa N. <Kus...@pl...>]

Now it compiles! Thanks a billion!

wbr Kusti


From: Michael Strelnikov <mic...@gm...<mailto:mic...@gm...>>
Reply-To: Discussions concerning Icarus Verilog development <ive...@li...<mailto:ive...@li...>>
Date: Monday, 23 October 2017 11:36
To: Discussions concerning Icarus Verilog development <ive...@li...<mailto:ive...@li...>>
Subject: Re: [Iverilog-devel] Passing arrays

Correction: "input [LENGTH*WIDTH-1:0] datain,"

Best regards,
Michael Strelnikov

On 23 October 2017 at 19:35, Michael Strelnikov <mic...@gm...<mailto:mic...@gm...>> wrote:
It could be an input array. Change it to "input datain [LENGTH*WIDTH-1:0],". Later you'll need to choose right bits. Or assemble an array from this vector.

Best regards,
Michael Strelnikov

On 23 October 2017 at 19:30, Kustaa Nyholm <Kus...@pl...<mailto:Kus...@pl...>> wrote:
Thanks, now it compiles but crashes:


cat correlator.v

module correlator #(

   parameter

   LENGTH = 4,

   WIDTH = 8

)

(

  input [LENGTH-1:0] datain [WIDTH-1:0],

  input clk,

  input reset,

  output reg [WIDTH-1 : 0] out

);


  always @(posedge reset, posedge clk)

    if(reset)

       out <= 0;

    else

       out <= out + 1;


endmodule

macbook-pro-3:modelsim-exp nyholku$ iverilog -g2012 -o correlator  correlator.v

correlator.v:7: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1

sh: line 1: 17396 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg2116cc4de" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg116cc4de" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli116cc4de"

     17397 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh116cc4de" -C"/usr/local/lib/ivl/vvp.conf" -- -

macbook-pro-3:modelsim-exp nyholku$

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Re: [Iverilog-devel] Passing arrays

[Michael S. <mic...@gm...>]

Correction: "input [LENGTH*WIDTH-1:0] datain,"

Best regards,
Michael Strelnikov

On 23 October 2017 at 19:35, Michael Strelnikov <mic...@gm...> wrote:

> It could be an input array. Change it to "input datain
> [LENGTH*WIDTH-1:0],". Later you'll need to choose right bits. Or assemble
> an array from this vector.
>
> Best regards,
> Michael Strelnikov
>
> On 23 October 2017 at 19:30, Kustaa Nyholm <Kus...@pl...>
> wrote:
>
>> Thanks, now it compiles but crashes:
>>
>> cat correlator.v
>>
>> module correlator #(
>>
>>    parameter
>>
>>    LENGTH = 4,
>>
>>    WIDTH = 8
>>
>> )
>>
>> (
>>
>>   input [LENGTH-1:0] datain [WIDTH-1:0],
>>
>>   input clk,
>>
>>   input reset,
>>
>>   output reg [WIDTH-1 : 0] out
>>
>> );
>>
>>
>>   always @(posedge reset, posedge clk)
>>
>>     if(reset)
>>
>>        out <= 0;
>>
>>     else
>>
>>        out <= out + 1;
>>
>>
>> endmodule
>>
>> macbook-pro-3:modelsim-exp nyholku$ iverilog -g2012 -o correlator
>> correlator.v
>>
>> correlator.v:7: assert: elaborate.cc:6410: failed assertion
>> netnet->pin_count()==1
>>
>> sh: line 1: 17396 Done                    /usr/local/lib/ivl/ivlpp -L
>> -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg2116cc4de"
>> -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg116cc4de"
>> -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli116cc4de"
>>
>>      17397 Abort trap: 6           | /usr/local/lib/ivl/ivl
>> -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh116cc4de"
>> -C"/usr/local/lib/ivl/vvp.conf" -- -
>>
>> macbook-pro-3:modelsim-exp nyholku$
>>
>> ------------------------------------------------------------
>> ------------------
>> Check out the vibrant tech community on one of the world's most
>> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>>
>

Re: [Iverilog-devel] Passing arrays

[Michael S. <mic...@gm...>]

It could be an input array. Change it to "input datain
[LENGTH*WIDTH-1:0],". Later you'll need to choose right bits. Or assemble
an array from this vector.

Best regards,
Michael Strelnikov

On 23 October 2017 at 19:30, Kustaa Nyholm <Kus...@pl...>
wrote:

> Thanks, now it compiles but crashes:
>
> cat correlator.v
>
> module correlator #(
>
>    parameter
>
>    LENGTH = 4,
>
>    WIDTH = 8
>
> )
>
> (
>
>   input [LENGTH-1:0] datain [WIDTH-1:0],
>
>   input clk,
>
>   input reset,
>
>   output reg [WIDTH-1 : 0] out
>
> );
>
>
>   always @(posedge reset, posedge clk)
>
>     if(reset)
>
>        out <= 0;
>
>     else
>
>        out <= out + 1;
>
>
> endmodule
>
> macbook-pro-3:modelsim-exp nyholku$ iverilog -g2012 -o correlator
> correlator.v
>
> correlator.v:7: assert: elaborate.cc:6410: failed assertion
> netnet->pin_count()==1
>
> sh: line 1: 17396 Done                    /usr/local/lib/ivl/ivlpp -L
> -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg2116cc4de"
> -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg116cc4de"
> -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli116cc4de"
>
>      17397 Abort trap: 6           | /usr/local/lib/ivl/ivl
> -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh116cc4de"
> -C"/usr/local/lib/ivl/vvp.conf" -- -
>
> macbook-pro-3:modelsim-exp nyholku$
>
> ------------------------------------------------------------
> ------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

Re: [Iverilog-devel] Passing arrays

[Kustaa N. <Kus...@pl...>]

Thanks, now it compiles but crashes:


cat correlator.v

module correlator #(

   parameter

   LENGTH = 4,

   WIDTH = 8

)

(

  input [LENGTH-1:0] datain [WIDTH-1:0],

  input clk,

  input reset,

  output reg [WIDTH-1 : 0] out

);


  always @(posedge reset, posedge clk)

    if(reset)

       out <= 0;

    else

       out <= out + 1;


endmodule

macbook-pro-3:modelsim-exp nyholku$ iverilog -g2012 -o correlator  correlator.v

correlator.v:7: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1

sh: line 1: 17396 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg2116cc4de" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg116cc4de" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli116cc4de"

     17397 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh116cc4de" -C"/usr/local/lib/ivl/vvp.conf" -- -

macbook-pro-3:modelsim-exp nyholku$

Re: [Iverilog-devel] Passing arrays

[Michael S. <mic...@gm...>]

Add 'parameter' word:

module correlator #(
  parameter
   LENGTH = 4,
   WIDTH = 8
)
(
  input [LENGTH-1:0] datain [WIDTH-1:0],
  input clk,
  input reset,
  output reg [WIDTH-1 : 0] out
);

  always @(posedge reset, posedge clk)
    if(reset)
       out <= 0;
    else
       out <= out + 1;

endmodule


Best regards,
Michael Strelnikov

On 23 October 2017 at 17:56, Kustaa Nyholm <Kus...@pl...>
wrote:

> Hi Michael
>
> and thanks, unfortunately iverilog gives up on that too, am I missing some
> flags on the command line  or something?
>
> wbr Kusti
>
>
> MacBook-Pro:iverilog-exp nyholku$ cat correlator.v
>
> module correlator #(
>
>    LENGTH = 4,
>
>    WIDTH = 8
>
> )
>
> (
>
>   input [LENGTH-1:0] datain [WIDTH-1:0],
>
>   input clk,
>
>   input reset,
>
>   output reg [WIDTH-1 : 0] out
>
> );
>
>
>   always @(posedge reset, posedge clk)
>
>     if(reset)
>
>        out <= 0;
>
>     else
>
>        out <= out + 1;
>
>
> endmodule
>
> MacBook-Pro:iverilog-exp nyholku$ iverilog -g2012 -o correlator
> correlator.v
>
> correlator.v:2: syntax error
>
> I give up.
>
>
> From: Michael Strelnikov <mic...@gm...>
> Reply-To: Discussions concerning Icarus Verilog development <
> ive...@li...>
> Date: Monday, 23 October 2017 02:55
> To: Discussions concerning Icarus Verilog development <
> ive...@li...>
> Subject: Re: [Iverilog-devel] Passing arrays
>
> This one should work for system verilog:
>
> module correlator #(
>    LENGTH = 4,
>    WIDTH = 8
> )
> (
>   input [LENGTH-1:0] datain [WIDTH-1:0],
>   input clk,
>   input reset,
>   output reg [WIDTH-1 : 0] out
> );
>
>   always @(posedge reset, posedge clk)
>     if(reset)
>        out <= 0;
>     else
>        out <= out + 1;
>
> endmodule
>
>
> Best regards,
> Michael Strelnikov
>
> On 17 October 2017 at 17:57, Kustaa Nyholm <Kus...@pl...>
> wrote:
>
>> Hi,
>>
>> I'm more or less noobie as far as Verilog is concerned, just at the
>> beginning of trying to find my bearings.
>> My background is sw (+35 years) with some basic level uni courses in VHDL
>> thrown in.
>>
>> As a naive starting point for what I'm trying to do I googled around came
>> up with this skeleton:
>>
>>  module correlator (
>>  input [LENGTH-1:0] datain [WIDTH-1:0],
>>  input clk,
>>  input reset,
>>  output [WIDTH-1 : 0] out
>> );
>>
>>    parameter LENGTH = 4;
>>    parameter WIDTH = 8;
>>
>>    reg [WIDTH-1 : 0]   out;
>>    wire       clk, reset;
>>
>>   always @(posedge clk)
>>     out <= out + 1;
>>
>>   always @reset
>>     if (reset)
>>       assign out = 0;
>>     else
>>       deassign out;
>>
>> endmodule
>> // #(int LENGTH, DEPTH)
>>
>> compiling this crashes with:
>>
>> iverilog -g2005-sv -o test  correlator.v
>>
>> correlator.v:2: assert: elaborate.cc:6410: failed assertion
>> netnet->pin_count()==1
>>
>> sh: line 1: 31244 Done                    /usr/local/lib/ivl/ivlpp -L
>> -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg21f4c2686"
>> -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg1f4c2686"
>> -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli1f4c2686"
>>
>>      31245 Abort trap: 6           | /usr/local/lib/ivl/ivl
>> -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh1f4c2686"
>> -C"/usr/local/lib/ivl/vvp.conf" -- -
>>
>> macbook-pro:verilogexp nyholku$ iverilog -g2005-sv -o test  correlator.v
>>
>> correlator.v:2: assert: elaborate.cc:6410: failed assertion
>> netnet->pin_count()==1
>>
>> sh: line 1: 40581 Done                    /usr/local/lib/ivl/ivlpp -L
>> -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg228a6aa75"
>> -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg28a6aa75"
>> -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli28a6aa75"
>>
>>      40582 Abort trap: 6           | /usr/local/lib/ivl/ivl
>> -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh28a6aa75"
>> -C"/usr/local/lib/ivl/vvp.conf" -- -
>>
>> So my questions is if there is a workaround for this or is my verilog
>> faulty?
>>
>> I also tried
>> module correlator #(int LENGTH, WIDTH)
>> and the compiler said it gave up on line 1.
>>
>> Is there a workaround for this?
>>
>> I think I'm running latest development branch from github (v10) but how
>> can I check?
>>
>> As at this point in time I do not know the how many inputs my correlator
>> module will take so I want to parametrise that .
>>
>> My ultimate goal is to create a massively parallel sea (also
>> parametrised) of this correlator module so any pointers to examples of this
>> would be highly appreciated...
>>
>> wbr Kusti
>>
>>
>>
>>
>> ------------------------------------------------------------
>> ------------------
>> Check out the vibrant tech community on one of the world's most
>> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>>
>
> ------------------------------------------------------------
> ------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

Re: [Iverilog-devel] Passing arrays

[Kustaa N. <Kus...@pl...>]

Hi Michael

and thanks, unfortunately iverilog gives up on that too, am I missing some flags on the command line  or something?

wbr Kusti



MacBook-Pro:iverilog-exp nyholku$ cat correlator.v

module correlator #(

   LENGTH = 4,

   WIDTH = 8

)

(

  input [LENGTH-1:0] datain [WIDTH-1:0],

  input clk,

  input reset,

  output reg [WIDTH-1 : 0] out

);


  always @(posedge reset, posedge clk)

    if(reset)

       out <= 0;

    else

       out <= out + 1;


endmodule

MacBook-Pro:iverilog-exp nyholku$ iverilog -g2012 -o correlator  correlator.v

correlator.v:2: syntax error

I give up.


From: Michael Strelnikov <mic...@gm...<mailto:mic...@gm...>>
Reply-To: Discussions concerning Icarus Verilog development <ive...@li...<mailto:ive...@li...>>
Date: Monday, 23 October 2017 02:55
To: Discussions concerning Icarus Verilog development <ive...@li...<mailto:ive...@li...>>
Subject: Re: [Iverilog-devel] Passing arrays

This one should work for system verilog:

module correlator #(
   LENGTH = 4,
   WIDTH = 8
)
(
  input [LENGTH-1:0] datain [WIDTH-1:0],
  input clk,
  input reset,
  output reg [WIDTH-1 : 0] out
);

  always @(posedge reset, posedge clk)
    if(reset)
       out <= 0;
    else
       out <= out + 1;

endmodule


Best regards,
Michael Strelnikov

On 17 October 2017 at 17:57, Kustaa Nyholm <Kus...@pl...<mailto:Kus...@pl...>> wrote:
Hi,

I'm more or less noobie as far as Verilog is concerned, just at the beginning of trying to find my bearings.
My background is sw (+35 years) with some basic level uni courses in VHDL thrown in.

As a naive starting point for what I'm trying to do I googled around came up with this skeleton:

 module correlator (
 input [LENGTH-1:0] datain [WIDTH-1:0],
 input clk,
 input reset,
 output [WIDTH-1 : 0] out
);

   parameter LENGTH = 4;
   parameter WIDTH = 8;

   reg [WIDTH-1 : 0]   out;
   wire       clk, reset;

  always @(posedge clk)
    out <= out + 1;

  always @reset
    if (reset)
      assign out = 0;
    else
      deassign out;

endmodule
// #(int LENGTH, DEPTH)

compiling this crashes with:

iverilog -g2005-sv -o test  correlator.v

correlator.v:2: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1

sh: line 1: 31244 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg21f4c2686" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg1f4c2686" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli1f4c2686"

     31245 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh1f4c2686" -C"/usr/local/lib/ivl/vvp.conf" -- -

macbook-pro:verilogexp nyholku$ iverilog -g2005-sv -o test  correlator.v

correlator.v:2: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1

sh: line 1: 40581 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg228a6aa75" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg28a6aa75" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli28a6aa75"

     40582 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh28a6aa75" -C"/usr/local/lib/ivl/vvp.conf" -- -

So my questions is if there is a workaround for this or is my verilog faulty?

I also tried
module correlator #(int LENGTH, WIDTH)
and the compiler said it gave up on line 1.

Is there a workaround for this?

I think I'm running latest development branch from github (v10) but how can I check?

As at this point in time I do not know the how many inputs my correlator module will take so I want to parametrise that .

My ultimate goal is to create a massively parallel sea (also parametrised) of this correlator module so any pointers to examples of this would be highly appreciated...

wbr Kusti




------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Iverilog-devel mailing list
Ive...@li...<mailto:Ive...@li...>
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] Passing arrays

[Michael S. <mic...@gm...>]

This one should work for system verilog:

module correlator #(
   LENGTH = 4,
   WIDTH = 8
)
(
  input [LENGTH-1:0] datain [WIDTH-1:0],
  input clk,
  input reset,
  output reg [WIDTH-1 : 0] out
);

  always @(posedge reset, posedge clk)
    if(reset)
       out <= 0;
    else
       out <= out + 1;

endmodule


Best regards,
Michael Strelnikov

On 17 October 2017 at 17:57, Kustaa Nyholm <Kus...@pl...>
wrote:

> Hi,
>
> I'm more or less noobie as far as Verilog is concerned, just at the
> beginning of trying to find my bearings.
> My background is sw (+35 years) with some basic level uni courses in VHDL
> thrown in.
>
> As a naive starting point for what I'm trying to do I googled around came
> up with this skeleton:
>
>  module correlator (
>   input [LENGTH-1:0] datain [WIDTH-1:0],
>   input clk,
>   input reset,
>   output [WIDTH-1 : 0] out
> );
>
>    parameter LENGTH = 4;
>    parameter WIDTH = 8;
>
>    reg [WIDTH-1 : 0]   out;
>    wire       clk, reset;
>
>   always @(posedge clk)
>     out <= out + 1;
>
>   always @reset
>     if (reset)
>       assign out = 0;
>     else
>       deassign out;
>
> endmodule
> // #(int LENGTH, DEPTH)
>
> compiling this crashes with:
>
> iverilog -g2005-sv -o test  correlator.v
>
> correlator.v:2: assert: elaborate.cc:6410: failed assertion
> netnet->pin_count()==1
>
> sh: line 1: 31244 Done                    /usr/local/lib/ivl/ivlpp -L
> -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg21f4c2686"
> -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg1f4c2686"
> -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli1f4c2686"
>
>      31245 Abort trap: 6           | /usr/local/lib/ivl/ivl
> -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh1f4c2686"
> -C"/usr/local/lib/ivl/vvp.conf" -- -
>
> macbook-pro:verilogexp nyholku$ iverilog -g2005-sv -o test  correlator.v
>
> correlator.v:2: assert: elaborate.cc:6410: failed assertion
> netnet->pin_count()==1
>
> sh: line 1: 40581 Done                    /usr/local/lib/ivl/ivlpp -L
> -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg228a6aa75"
> -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg28a6aa75"
> -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli28a6aa75"
>
>      40582 Abort trap: 6           | /usr/local/lib/ivl/ivl
> -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh28a6aa75"
> -C"/usr/local/lib/ivl/vvp.conf" -- -
>
> So my questions is if there is a workaround for this or is my verilog
> faulty?
>
> I also tried
> module correlator #(int LENGTH, WIDTH)
> and the compiler said it gave up on line 1.
>
> Is there a workaround for this?
>
> I think I'm running latest development branch from github (v10) but how
> can I check?
>
> As at this point in time I do not know the how many inputs my correlator
> module will take so I want to parametrise that .
>
> My ultimate goal is to create a massively parallel sea (also parametrised)
> of this correlator module so any pointers to examples of this would be
> highly appreciated...
>
> wbr Kusti
>
>
>
>
> ------------------------------------------------------------
> ------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>

[Iverilog-devel] Incorrect handling of timeunit/timeprecision in compilation unit scope

[Martin W. <ic...@ma...>]

I'm working on adding support in the compiler for treating each file as a 
separate compilation unit (as required by the SystemVerilog standard). I've 
run into a problem with the way Icarus handles timeunit and timeprecision 
declarations.

Currently the compiler allows timeunit and timeprecision declarations to 
change the timescale in the compilation unit scope (and there are tests in 
the test suite that do this). This is explicitly forbidden by the 
SystemVerilog standard (1800-2012 section 3.14.2.2).

Does anyone want to argue against fixing the compiler to be compliant with 
the standard?

Note that the case where you have different timescales in different files 
is handled by treating each file as a separate compilation unit.

[Iverilog-devel] Passing arrays

[Kustaa N. <Kus...@pl...>]

Hi,

I'm more or less noobie as far as Verilog is concerned, just at the beginning of trying to find my bearings.
My background is sw (+35 years) with some basic level uni courses in VHDL thrown in.

As a naive starting point for what I'm trying to do I googled around came up with this skeleton:

 module correlator (
  input [LENGTH-1:0] datain [WIDTH-1:0],
  input clk,
  input reset,
  output [WIDTH-1 : 0] out
);

   parameter LENGTH = 4;
   parameter WIDTH = 8;

   reg [WIDTH-1 : 0]   out;
   wire       clk, reset;

  always @(posedge clk)
    out <= out + 1;

  always @reset
    if (reset)
      assign out = 0;
    else
      deassign out;

endmodule
// #(int LENGTH, DEPTH)

compiling this crashes with:

iverilog -g2005-sv -o test  correlator.v

correlator.v:2: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1

sh: line 1: 31244 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg21f4c2686" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg1f4c2686" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli1f4c2686"

     31245 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh1f4c2686" -C"/usr/local/lib/ivl/vvp.conf" -- -

macbook-pro:verilogexp nyholku$ iverilog -g2005-sv -o test  correlator.v

correlator.v:2: assert: elaborate.cc:6410: failed assertion netnet->pin_count()==1

sh: line 1: 40581 Done                    /usr/local/lib/ivl/ivlpp -L -F"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg228a6aa75" -f"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlg28a6aa75" -p"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrli28a6aa75"

     40582 Abort trap: 6           | /usr/local/lib/ivl/ivl -C"/var/folders/yv/fzmkhkkn1s95b0qwn48ghbj00000gn/T//ivrlh28a6aa75" -C"/usr/local/lib/ivl/vvp.conf" -- -

So my questions is if there is a workaround for this or is my verilog faulty?

I also tried
module correlator #(int LENGTH, WIDTH)
and the compiler said it gave up on line 1.

Is there a workaround for this?

I think I'm running latest development branch from github (v10) but how can I check?

As at this point in time I do not know the how many inputs my correlator module will take so I want to parametrise that .

My ultimate goal is to create a massively parallel sea (also parametrised) of this correlator module so any pointers to examples of this would be highly appreciated...

wbr Kusti

Re: [Iverilog-devel] Problem in opening gtkwave through terminal

[<by...@nc...>]

| My GTKWave is not able to load, when I try open it through terminal window
| with this command
| 
| $ open gtkwave -a full_adder.vcd

Your usage of "open" implies to me that you are a Mac user.

If you have unzipped the native OSX zip file found here as a gtkwave.app bundle into ~/Desktop:
https://sourceforge.net/projects/gtkwave/files/gtkwave-3.3.85-osx-app/

...then you might want to look at its perl command line launcher script
gtkwave.app/Contents/Resources/bin/gtkwave

Do not confuse it with the gtkwave file found in the gtkwave.app/Contents/MacOS location.

Starting the OSX version from the command line is not the same as for Linux as it requires some reformatting of command line arguments due to the syntax for open.  If you are running from a shell script or a makefile, you might have additional problems with the asynchronous behavior of open.  As I do not use OSX, I can't help you with that.

-Tony

Re: [Iverilog-devel] Regarding root file

[Stephen W. <st...@ic...>]

Yes, the "-s half_adder.v" is incorrect. Just drop that part of the command
line.
The compiler should be able to infer the root module by noting the module
that is not otherwise instantiated.


On Sat, Sep 2, 2017 at 12:15 PM, chandan kumar <ck9...@gm...> wrote:

> I am simulating full adder using a half adder. Files are as half_adder.v
> and full_adder.v . I compile these files using half_adder.v as root file
> using command
>  $ iverilog -s half_adder.v -o sim_full_adder full_adder.v full_adder_tb.v
>
> This gives an error
>    error: unable to find the root module "half_adder" in verilog source.
>         : Perhaps ''-s half_adder'' is incorrect?
>
>
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Re: [Iverilog-devel] Problem in opening gtkwave through terminal

[chandan k. <ck9...@gm...>]

It also doesn't work.

On Thu, Sep 28, 2017 at 10:57 PM, Paulo Ferreira <pa...@ke...> wrote:

>
> > On 21/09/2017, at 18:55, chandan kumar <ck9...@gm...> wrote:
> >
> > My GTKWave is not able to load, when I try open it through terminal
> window with this command
> >
> > $ open gtkwave -a full_adder.vcd
> >
> > It shows an error showing
> >
> > "/Desktop/tutorial1/gtkwave does not exist"
> >
> Try:
> gtkwave -a full_adder.vcd
>
>
>
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> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
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>

Re: [Iverilog-devel] Problem in opening gtkwave through terminal

[Paulo F. <pa...@ke...>]

> On 21/09/2017, at 18:55, chandan kumar <ck9...@gm...> wrote:
> 
> My GTKWave is not able to load, when I try open it through terminal window with this command
> 
> $ open gtkwave -a full_adder.vcd
> 
> It shows an error showing 
> 
> "/Desktop/tutorial1/gtkwave does not exist"
> 
Try:  
gtkwave -a full_adder.vcd