Please browse the reported bugs/issues for Icarus Verilog at your pleasure. If you think you have found a bug of your own, first browse the existing bugs and feature requests to determine whether your bug has already been reported by someone else. It is far better to expound on an existing bug report then to create a new bug report for the same thing. If you find that your issue matches an existing report, then click on that issue page to get details. You have the option of adding comments to the bug report. Also, you will be able to monitor any existing bug report. If you have convinced yourself that your bug really is unique, then use the Submit link to start the bug submission.
The priority breakdown reflects the priority that the Icarus Verilog development team intends given the nature of the problem. This is how the Icarus Verilog team assigns priority:
3 - minor issues like invalid or missing warnings, spelling fixes, etc.
4 - functionality that is missing, but is not currently needed or can be worked around with code changes,
5 - The catch all for run-of-the-mill bugs, or unreviewed bugs,
6 - an invalid result without a warning that can be worked around; or use this priority for a program crash that is preventing one from using Icarus Verilog,
7 - An invalid result without a warning that cannot be worked around reasonably.
9 - Imminent nuclear death, meteor impact, or hysterical screaming boss.
The "Owner" field is used by the core Icarus Verilog developers to claim a bug report. Somebody may be working on unassigned reports, but when it is assigned then that individual is explicitly stating that they are (intend) to work on it. If you wish to contribute towards fixing a claimed bug report, please coordinate with the claimant.
|610||Add full leading zero support and unify $display and $swrite||v0.9||closed-fixed||Cary R.||2008-12-30||2009-01-15||5|
|607||Wildcard sensitivity list of block with delay segfaults||v0.9||closed-fixed||Cary R.||2008-12-27||2008-12-29||5|
|606||Unary operator in index expression causes assertion failure||v0.9||closed-fixed||2008-12-22||2009-01-03||5|
|604||Uninitialised real net causes assertion failure in vvp||v0.9||closed-fixed||Cary R.||2008-12-22||2009-01-02||5|
|603||Real ternary with mixed types fails/asserts||v0.9||closed-fixed||Stephen Williams||2008-12-20||2009-01-06||6|
|601||Variable vector part selects don't produce correct results||v0.9||closed-fixed||2008-12-19||2008-12-19||6|
|600||VHDL "Initial visit to scope" traverses full hierarchy, slow||v0.9||closed||Nick Gasson||2008-12-18||2009-01-17||5|
|598||Constant part/bit selects with an unknown select value fail||v0.9||closed-fixed||2008-12-16||2009-01-02||6|
|597||Sign can be lost/is missing in parameter calculation||v0.9||closed-fixed||Stephen Williams||2008-12-14||2008-12-20||6|
|596||Shift operators and unknown right operand result is wrong||v0.9||closed-fixed||Cary R.||2008-12-14||2008-12-14||6|
|595||Wrong requirements for width||v0.9||closed-works-for-me||2008-12-12||2008-12-12||5|
|593||Conditional expression in signal range causes assert error||v0.9||closed-works-for-me||2008-12-10||2009-01-13||5|
|590||0'b0 crashes Icarus||v0.9||closed||2008-12-06||2009-01-16||5|
|583||assertion "tname == VHDL_TYPE_UNSIGNED || ..."||v0.9||closed-fixed||Nick Gasson||2008-11-30||2008-12-13||5|
|548||VHDL: only casex statements with constant labels ..||v0.9||closed-fixed||Cary R.||2008-10-28||2008-12-18||5|
|514||Value of $realtime, $time, etc. don't propagate in a CA.||v0.9||closed-fixed||Martin Whitaker||2008-09-22||2008-12-22||5|
|242||Part select of signal ports not implemented||v0.9||closed-fixed||Stephen Williams||2007-05-22||2008-12-12||4|