I think I was (and maybe still am) thinking that the the
`begin_keywords directive is the right way to handle this, but
that is not yet implemented in the core compiler. I'm thinking
that, because outside the VHDL code, the user should be able to
stick with whatever version of Verilog they want, and not be
compelled to deal with SystemVerilog just because some VHDL is
being mixed in.

A proper implementation of begin_keywords/end_keywords would
make this problem really easy to solve. That's my thinking.

On 12/09/2013 12:25 PM, Martin Whitaker wrote:

The problem here is that Icarus Verilog handles VHDL files by running a
pre-processor that converts them to Verilog before running the main
Verilog compiler. However, in many cases it will use SystemVerilog
constructs to represent the VHDL behaviour. To get the compiler to
accept SystemVerilog constructs, you need to add the appropriate
"generation" option, e.g.

iverilog -g2009 test.vhd

It could be argued that the compiler driver should automatically add
this option when compiling VHDL files, but this could lead to problems
if someone wants to do mixed VHDL/Verilog simulation. I'll wait to see
if the other Icarus developers have an opinion on this.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."