#937 VVP Error doesn't match problem when file_name is too long.

v0.9
closed-fixed
None
5
2013-10-08
2013-09-22
James Edgar
No

I'm running:

bash-4.2$ vvp -V
Icarus Verilog runtime version 0.9.7 (v0_9_7)

on Fedora

It appears that when a filename is provided that is larger than 64 bytes, an unrelated error is caused.

This input:

vvp -M /home/Jamie/projects/xilinx/minsoc/trunk/bench/verilog/vpi/ -mjp-io-vpi /home/Jamie/projects/xilinx/minsoc/trunk/sim/run/minsoc_bench +file_name=/home/Jamie/projects/xilinx/minsoc/trunk/sim/run/ping-twobyte-sizefirst.hex

Causes this error:

vvp: vvp_net.h:386
void vvp_vector4_t::set_bit(unsigned int, vvp_bit4_t)
Assertion 'idx < size_' failed

If I simply change the file_name to be less than 64 characters, everything works. (same file, just renamed or moved so path + file name does not exceed 64 characters.)

While this is easy to fix, the error does not suggest the cause (my impression is that this error is for port size mismatches, and can be valid in other cases.)

Thanks,

James

Discussion

  • Cary R.

    Cary R. - 2013-09-23

    Hi James,

    Since you did not attach an example I'm not sure which path you are talking about. Is it the +file_name argument and it so what does the appropriate $value$plusargs statement look like. If it's files loaded with the -M then I can likely create my own test code, but from what you wrote I would assume this is concerning the +file_name argument.

     
  • Martin Whitaker

    Martin Whitaker - 2013-09-28

    I think I have managed to reproduce the problem. This error will occur if both these conditions are true:

    • the vector variable (second argument) passed to $value$plusargs() is not big enough to hold the string supplied on the command line
    • the vector variable is not an exact multiple of eight bits

    Running the attached test case with the argument +string=0123456789 results in the same assertion failure that James reports.

    The bug is present in development as well as v0.9.

    James, could you confirm whether your code matches both the above conditions.

     
  • Martin Whitaker

    Martin Whitaker - 2013-09-28

    I've pushed a fix for the bug I've identified to both the development and v0.9 branches on github. I'll wait for James to confirm whether this is the fault he is seeing before closing this bug report.

     
  • Cary R.

    Cary R. - 2013-09-30
    • status: open --> pending
    • assigned_to: Martin Whitaker
     
  • Cary R.

    Cary R. - 2013-09-30

    I'm marking this pending since we are waiting for a response from the original reporter. This also gives us an indication that we believe it is fixed.

     
  • Cary R.

    Cary R. - 2013-10-08
    • status: pending --> closed-fixed
     
  • Cary R.

    Cary R. - 2013-10-08

    It has been over a week without a reply so I'm closing this bug as fixed. If the fix Martin submitted did not fix the original issue then please let one of us know and we can reopen this report. If the fix does not work then we need a simple Verilog example to reproduce the problem or at least a few critical lines.

     

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