#929 Semantics for ==/!= and X


Was running a testbench today and noticed that this statement:

if (dec_5_0.yout_ph1 != 14'd6) begin $display("Mismatch ph1"); end

didn't print "Mismatch ph1" when yout_ph1 was X's. Changed it to ! around an == and same thing.

Is this correct Verilog semantics? I was under the impressions that both == and != should fail when present with X's, not succeed.



  • Andrew P. Lentvorski, Jr.

    Err, sorry. I'm on OS X 10.6.8 with Icarus Verilog version 0.9.5

  • Cary R.

    Cary R. - 2013-05-01

    In general it would be best if you verify that your problem is not a misunderstanding on your part before creating a bug report.

    The == and != operators return 1'bx if either operand has an undefined bit. The ! operator when given a value with undefined bits also returns 1'bx. 1'bx in the context of an if statement is never true. With all this Icarus is working exactly as it should. You can use the === or !== operators to compare values that have undefined bits in them. These two operators never return an undefined value.

    This is an invalid report so I'm closing it.

  • Cary R.

    Cary R. - 2013-05-01
    • status: open --> closed-invalid
    • Group: devel --> v0.9

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