#917 syntax error inside the output file

Iztok Jeras


I get a syntax error report for the output file. This is the first time I encounter issues with the output file. The sources are SystemVerilog, and they were not yet tested on another simulator, so it is possible there is an issue with source files not detected by the parser. I detected the issue about 6 months ago but I did not have the time to report it till now, I also hoped this was a transitional issue on the devel.

To reproduce ti please do:
$ git clone git://github.com/jeras/zbus.git zbus-test
$ cd zbus-test/
$ cd sim/
$ ./iverilog_gtkwave.sh

What I get is:
zstr.out:147: syntax error

Iztok Jeras


  • Cary R.

    Cary R. - 2013-01-01

    I can confirm this failure in development. The problem appears to be that two state variable arrays or at least the type you are trying to instantiate are not handled by the runtime. I'm busy working on vvp to get it valgrind clean and I'll try to look at this when I get to a stopping point. I can likely reduce this to a much simpler test case. Since I'm working in vvp and specifically have some array changes pending no one should work on this until I push my changes.

  • Cary R.

    Cary R. - 2013-01-03

    I have not had time to see how hard this is going to be to implement. It appears that vvp does not currently support two-state arrays (I didn't actually check net arrays, but variable arrays are confirmed by this report). For example:

    int sarr [3:0] is translated into .array/2s and
    bit [7:0] uarr [3:0] is translated into .array/2u

    and neither of these constructs are parsed correctly. I may have time to look at this later, but I still have valgrind cleanup that I'm working on. I have pushed the array changes I mentioned above. FYI you have to declare and use the array to get it to appear in the compiler output.

  • Stephen Williams

    I've attached a simplified example that seems to demonstrate the
    issue. I can look into tackling this issue, since I probably created
    it in the first place.

    Last edit: Stephen Williams 2013-01-03
  • Stephen Williams

    I've pushed into Icarus Verilog git master runtime support for unpacked arrays of the atom2 types. This handles most of the cases that this report brings up. What's missing is arbitrary dimension bit types. It turns out that dynamic arrays also don't support bit vectors, so we should work that as a separate patch.

    I've also added to the ivtest suite (git master) some regression tests for the cases that we now support.

  • Stephen Williams

    The example as attached is working now (I think) so I'm going to close this report.

  • Stephen Williams

    • status: open --> closed-fixed

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