#915 Crash: 'repeat' with conditional expression


Segmentation fault occurs if 'repeat' contain conditional expression.

Original code was:
repeat(extend > 2 ? extend-2 : 0) #3 $display(" Test: extend = %d", extend);

Actually even following conditional expression gives a seg_fault:
repeat(1 ? 2 : 3) #3 $display(" Test: extend = %d", extend);

Additional info
OS: Windows 7
Iverilog 0.9.6
Test module: testcase.v (see attachment)
Execution script: ‘testcase.bat’
set a=E:\demo\iverilog\bin
set b=E:\testcase
cd %a%
iverilog.exe -m testcase -o %b%\testcase.vvp -tvvp %b%\testcase.v
REM vvp.exe %b%\testcase.vvp
cd %b%
E:\testcase\testcase.v:19: assert: ../verilog-0.9.6/elab_expr.cc:3520: failed assertion use_wid > 0


  • Alexey

    Alexey - 2012-12-05

    Verilog source code

  • Martin Whitaker

    Martin Whitaker - 2012-12-05

    I have confirmed this bug is still present in the latest v0.9 code from git, but is fixed in devel (v0.10). I'm attaching a reworked version of the test case that is ready for inclusion in the test suite.

    FYI, devel is generally stable enough for real use. I use it exclusively, as it contains many bug fixes that can't be back-ported to v0.9.

  • Martin Whitaker

    Martin Whitaker - 2012-12-05

    Reworked test for inclusion in test suite

  • Martin Whitaker

    Martin Whitaker - 2013-01-20

    I have posted a patch that fixes this bug on the patch tracker.

  • Cary R.

    Cary R. - 2013-01-22
    • status: open --> closed
  • Cary R.

    Cary R. - 2013-01-22

    I have applied and pushed the patch. It is available from git and the next V0.9 release whenever that happens.


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