The attached module can be compiled without error by iverilog. The resulting output, however, will yield the following error when run:
./a.out:14: syntax error
It appears that iverilog truncates the very long line in such a way that the output contains an unterminated string.
I observed this behavior with version 0.9.2 and version 0.9.5. Strangely, this bug is not present with the older version 0.8.6.
It would be ideal if iverilog could compile (and simulate) this module properly. However, at the very least, iverilog should
report an error rather than silently ignoring the problem and generating corrupt output.
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