According with the Standard of Verilog, since Verilog 2001 and in Vorilog 2005 also the following module description is valid:
module register #(
parameter integer MSB = 32
input [MSB-1:0] D,
output [MSB-1:0]Q, // Q is a reg since it is assigned in an always block
output [MSB-1:0] Q_
for(i=0;i < MSB; i = i+1)
DFF r (.rstn(rstn), .clk(clk), .ce(ce), .D(D[i]), .Q(Q[i]), .Q_(Q_[i]));
Although The Icarus compiler complains of the parameter, saying it is invalid. The case is: it is valid and correct, I'm synthesizing a MIPS design that contains the above description and for synplify it is ok.
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