#891 Icarus not compliant with standard 200X for parameters

devel
closed-fixed
5
2012-05-18
2012-05-15
No

According with the Standard of Verilog, since Verilog 2001 and in Vorilog 2005 also the following module description is valid:

`timescale 1ns/100ps

module register #(
parameter integer MSB = 32
)
(
input rstn,
input clk,
input ce,
input [MSB-1:0] D,
output [MSB-1:0]Q, // Q is a reg since it is assigned in an always block
output [MSB-1:0] Q_
);

genvar i;
generate
for(i=0;i < MSB; i = i+1)
begin:muxer32
DFF r (.rstn(rstn), .clk(clk), .ce(ce), .D(D[i]), .Q(Q[i]), .Q_(Q_[i]));
end
endgenerate

endmodule

Although The Icarus compiler complains of the parameter, saying it is invalid. The case is: it is valid and correct, I'm synthesizing a MIPS design that contains the above description and for synplify it is ok.

Discussion

  • Martin Whitaker

    Martin Whitaker - 2012-05-15
    • milestone: 896955 --> devel
     
  • Martin Whitaker

    Martin Whitaker - 2012-05-15

    I agree this is valid syntax. This also fails in current development, so I'm switching this report to development, as that is where it will be fixed first.

    As a temporary workaround, you can comment out the "integer" in the parameter declaration - providing you only ever assign integer values to MSB, the behaviour will be the same.

     
  • Martin Whitaker

    Martin Whitaker - 2012-05-17

    After a bit of a battle with yacc shift/reduce conflicts, I think I've found a way to fix this, so will take this bug.

     
  • Martin Whitaker

    Martin Whitaker - 2012-05-17
    • assigned_to: nobody --> martinwhitaker
     
  • Luís Vitório Cargnini

    Ok,
    Great to hear that it can be fixed without major changes.

     
  • Martin Whitaker

    Martin Whitaker - 2012-05-18
    • status: open --> closed-fixed
     
  • Martin Whitaker

    Martin Whitaker - 2012-05-18

    I've submitted patches on the patch tracker that fix this bug in both devel and v0.9.

     

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No, thanks