line 7 of this file contains:
discipline \logic ;
It seems that backslash before "logic" may be deleted.
The backslash before logic cannot be deleted since logic is a keyword in SystemVerilog and Verilog-AMS requires that discipline be followed with an identifier. By using a \ we are creating an escaped identifier which allows us to create a discipline with the appropriate name. The SystemVerilog and Verilog-A integration is still in progress so there may be a different solution, but for now this is what we are doing.
Also please not ethat any future Verilog-AMS development will be done in the development branch. V0.9 will never support Verilog-AMS. No one is currently working on Verilog-AMS.
I'm marking this bug invalid and closing the report
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