I am using icarus verilog 0.8.5 (the release delviered with Ubuntu Hardy)
I have a very small verilog file, that's compiling with other verilog simulators, but that fails with icarus verilog.
I reduced the testfile to the absolute minimum.
The original file was part of legacy verilog.
To produce the bug:
the output is:
ivl: eval_expr.c:1794: draw_ufunc_expr: Assertion `res.wid <= ivl_signal_pins(port)' failed.
to show the responsible line run
iverilog reswid_assert.v -DNO_BUG
to see, that the bug disappears
I hope this info helps you to reproduce the bug.
So far I didn't try to identify a work a round.
I'll look into this in the next days.
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