#648 assert res.wid <= ivl_signal_pins(port)


I am using icarus verilog 0.8.5 (the release delviered with Ubuntu Hardy)

I have a very small verilog file, that's compiling with other verilog simulators, but that fails with icarus verilog.

I reduced the testfile to the absolute minimum.
The original file was part of legacy verilog.

To produce the bug:

iverilog reswid_assert.v

the output is:

ivl: eval_expr.c:1794: draw_ufunc_expr: Assertion `res.wid <= ivl_signal_pins(port)' failed.

to show the responsible line run
iverilog reswid_assert.v -DNO_BUG

to see, that the bug disappears

I hope this info helps you to reproduce the bug.
So far I didn't try to identify a work a round.
I'll look into this in the next days.


  • Somebody

    Somebody - 2009-02-10

    the file, that provokes the assertion bug

  • Somebody

    Somebody - 2009-02-10

    this file suggests a work around

  • Somebody

    Somebody - 2009-02-10

    I found a workaround (usage of an intermediate variable)

    Please download the new attachement (reswid_assert_2.v) and run it with

    iverilog reswid_assert_2.v -DNO_BUG

    File Added: reswid_assert_2.v

  • Cary R.

    Cary R. - 2009-02-10

    This still asserts with the latest version of 0.8 from git, but appears to work when using V0.9.devel. Since you have a work around and given we plan to release V0.9 fairly soon this will likely not be fixed in V0.8 and will be closed when we release V0.9 as the next stable release.

  • Cary R.

    Cary R. - 2009-02-10
    • priority: 5 --> 4
  • Cary R.

    Cary R. - 2009-03-23

    We have released a new stable version of Icarus Verilog (V0.9) that for normal usage replaces the version this report was filed against (V0.8). The reported bug does not exist in the V0.9 release and V0.8 will no longer be supported. We are closing this report and suggest that you upgrade to V0.9 as soon as possible.

  • Cary R.

    Cary R. - 2009-03-23
    • status: open --> closed-out-of-date

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