#643 VHDL module name containing __ needs to be translated

v0.9
closed
nobody
5
2009-02-05
2009-02-01
thiede
No

module test();
a__a a_(
.b_buf(b),
.b (b)
);
endmodule

module a__a(b_buf, b);
output b_buf;
input b;
assign b_buf = 1'b0;
endmodule

iverilog -thvdl generates illegal VHDL

Discussion

  • thiede

    thiede - 2009-02-01

    Today's rename patch renames a__a to a_a, but fails to check whether it clashes with existing module names.

    I know that I'm getting picky here, the likelyhood of this kind of verilog is getting smaller, but it's out there. Today's bugreports all show when trying to convert the OpenSparc 2.1 code.

    module test();
    a__a a__();
    a_a a_();
    endmodule

    module a__a();
    endmodule

    module a_a();
    endmodule

     
  • thiede

    thiede - 2009-02-05
    • status: open --> closed
     

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