module a__a(b_buf, b);
assign b_buf = 1'b0;
iverilog -thvdl generates illegal VHDL
Today's rename patch renames a__a to a_a, but fails to check whether it clashes with existing module names.
I know that I'm getting picky here, the likelyhood of this kind of verilog is getting smaller, but it's out there. Today's bugreports all show when trying to convert the OpenSparc 2.1 code.
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