#583 assertion "tname == VHDL_TYPE_UNSIGNED || ..."

v0.9
closed-fixed
5
2008-12-13
2008-11-30
thiede
No

(s20080905-267-gfc00bd9)

iverilog -tvhdl test.v
assertion ": file "vhdl_syntax.cc", line 477

module test ( c );
input c;

a #(1) ua( .c(c), .b(h));
endmodule
module a(
c,
b,
);
parameter e = 2;

input c;
output [e-1:0] b;

reg [e-1:0] f;
reg [e-1:0] g;
reg [e-1:0] b;
integer d;

always @(posedge c) begin
for(d=0; d<e; d=d+1)
b[d] <= (f[d] & (b[d] | g[d]));
end
endmodule

Discussion

  • thiede

    thiede - 2008-11-30

    File Added: test.v

     
  • thiede

    thiede - 2008-11-30
     
  • Cary R.

    Cary R. - 2008-12-02

    I did some quick debug. This is starting in expr.cc, translate_select(), line 471 (set_slice call). This is being triggered by the the r-value bit selects in the b[d] <= line. It's not obvious to me what needs to be done so I will leave this for Nick. At least he has a better idea where to start ;-).

     
  • Cary R.

    Cary R. - 2008-12-02
    • assigned_to: nobody --> nickga
     
  • Cary R.

    Cary R. - 2008-12-12
    • milestone: 530321 --> v0.9
     
  • Nick Gasson

    Nick Gasson - 2008-12-12

    Posted a patch to the tracker to fix this.

     
  • Stephen Williams

    Fixed in git master.

     
  • Stephen Williams

    • status: open --> closed-fixed
     

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