#31 simulation error, sig goes X

devel
closed-fixed
nobody
Other (110)
5
2006-05-18
2006-04-10
Anonymous
No

on a structural testbench instantiating a bunch of
flipflops, some go X. Other simulators (cver,
ncverilog) don't.

make sim
displays errors.

make sim SIMULATOR=cver
passes

the flipflop cnr_tb.cnr0.in0_23 Q goes x at t=20ns on
the 'make wave' target. I don't think it should.

(vp is a preprocessor that makes cnr.v from cnr.vp
I have supplied both. I don't think its related.)

Discussion

  • Nobody/Anonymous

    testcase

     
  • jrsheahan

    jrsheahan - 2006-04-10

    Logged In: YES
    user_id=1168632

    I should add an email address as submitter
    jrsheahan@optushome.com.au
    and it relates to versions 0.8.1 through verilog-20060409 at
    least, on both i386 and amd64.
    john

     
  • Stephen Williams

    Logged In: YES
    user_id=97566

    The attached patch fixes this problem and should apply to the 20060409
    snapshot. Or, it is in the current cvs.

     
  • Stephen Williams

    patch for devel snapshot 20060409

     
  • Stephen Williams

    • status: open --> closed-fixed
     

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