iverilog bug.v
bug.v:11: error: Part select expressions must be constant.
bug.v:11: : This msb expression violates the rule:
(i)*('sd4)
Elaboration failed
While the tool correctly compiles the 2001 syntax for
bit select in a register when on the rhs of the = sign,
it fails on the lhs. Below is a simple example that
fails to compile. It seems to dislike the use of a
variable in the start reference of the bit select e.g.
the integer "i".
module bug;
reg [31:0] a;
integer i;
initial
begin
i=4;
a=0;
a[i*4+:2] = 2'b11;
$display("%h",a);
end
endmodule
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I've attached a patch that fixes this problem. It should apply to the 20060409
snapshot, or get the fixes from CVS as of 4/14/2006.
Patch to 20060409 to fix this issue.