#23 wrong simulation output

devel
closed-fixed
nobody
6
2006-03-15
2006-03-06
stefan
No

Hi , William

a simple testbench consisting of :

- 16 bit input signal aa[15:0]
- 16 bit output signal zz[15:0]
- 16 bit enable signal ee[15:0]
- 16 instances of a three state buffer 'bts'

each 'bts' takes one 'aa' bit, one 'ee' bit and drives
one 'zz' bit.
the 'zz' output bit is driven to 1'bz if ee==0 else
it is driven to 'aa' with some delay.

The attached picture shows that the testcase is
simulated correctly by verilog-0.8 while
with the last released snapshot (20060215) after
some events the zz bus is incorrectly driven to 'X'.

attached also the 'test.v' testbench.

Best regards

Stefan

stefan@schippers.it

Discussion

  • stefan

    stefan - 2006-03-06

    verilog testbench

     
  • stefan

    stefan - 2006-03-06
     
  • Stephen Williams

    • priority: 5 --> 6
     
  • Stephen Williams

    Logged In: YES
    user_id=97566

    I've confirmed that this is happening. I've raised the
    priority because it is compiling withing warnings but
    generating wrong results.

     
  • Stephen Williams

    • status: open --> closed-fixed
     
  • Stephen Williams

    Logged In: YES
    user_id=97566

    I've attached a path that should apply to the 20060215 snapshot, and will
    be included in later snapshots. I've also added pr1444055.v to the ivtest
    project as a test for this case.

     
  • Stephen Williams

    Patch for devel snapshot 20060215

     

Log in to post a comment.

Get latest updates about Open Source Projects, Conferences and News.

Sign up for the SourceForge newsletter:





No, thanks