Hi , William
a simple testbench consisting of :
- 16 bit input signal aa[15:0]
- 16 bit output signal zz[15:0]
- 16 bit enable signal ee[15:0]
- 16 instances of a three state buffer 'bts'
each 'bts' takes one 'aa' bit, one 'ee' bit and drives
one 'zz' bit.
the 'zz' output bit is driven to 1'bz if ee==0 else
it is driven to 'aa' with some delay.
The attached picture shows that the testcase is
simulated correctly by verilog-0.8 while
with the last released snapshot (20060215) after
some events the zz bus is incorrectly driven to 'X'.
attached also the 'test.v' testbench.
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